Patent Application
20160307833
1. Field of the Invention
The present invention relates to fabrication methods of electronic packages, and more particularly, to a fabrication method of an electronic package for improving the product yield.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Current chip packaging technologies have developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages.
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However, the chemical etching process for removing the silicon wafer 10′ is very time-consuming, thus resulting in a low product yield and an increase in the fabrication cost.
Further, after the silicon wafer 10′ is removed, since the adhesive layer 100 still remains covering the conductive pads 110, the adhesive layer 100 needs to be partially removed by a chemical method so as to form the openings 15 exposing the conductive pads 110. Such a chemical method also reduces the product yield and increases the fabrication cost.
Therefore, how to overcome the above-described drawbacks has become critical.
In view of the above-described drawbacks, the present invention provides an electronic packaging structure, which comprises: a circuit portion having opposite first and second sides; at least an electronic element disposed on the first side of the circuit portion; and a glass carrier disposed on the second side of the circuit portion.
The above-described structure can further comprise an encapsulant formed on the first side of the circuit portion for encapsulating the electronic element.
The present invention further provides a method for fabricating an electronic package, which comprises the steps of: providing an electronic structure, wherein the electronic structure comprises a glass carrier, a circuit portion formed on the glass carrier and at least an electronic element disposed on the circuit portion; forming an encapsulant on the circuit portion for encapsulating the electronic element; and removing the glass carrier.
After removing the glass carrier, the above-described method can further comprise forming a plurality of conductive elements on the circuit portion.
After removing the glass carrier, the above-described method can further comprise performing a singulation process.
In the above-described structure and method, an underfill can be formed between the circuit portion and the electronic element.
In the above-described structure and method, the glass carrier and the circuit portion can be bonded through a release film and the glass carrier can be removed through the release film.
In the above-described structure and method, the electronic element can be exposed from the encapsulant.
Therefore, by replacing a silicon wafer with a glass carrier, the present invention dispenses with an adhesive layer and allows quick removal of the glass carrier, thus saving a large amount of time, increasing the product yield and reducing the fabrication cost.
Further, since the second side of the circuit portion is exposed after the glass carrier is removed, a plurality of solder balls can be directly formed on the second side of the circuit portion or other devices can be directly connected to the second side of the circuit portion. Therefore, the present invention greatly increases the product yield and reduces the fabrication cost.
The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.
It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.
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Each of the electronic elements 22 can be an active element such as a semiconductor chip, a passive element such as a resistor, a capacitor or an inductor, or a combination thereof. In the present embodiment, each of the electronic elements 22 is an active element having an active surface 22a and an inactive surface 22b opposite to the active surface 22a.
The circuit portion 21 has a plurality of dielectric layers 210 and a plurality of circuit layers 211 stacked alternately. The circuit portion 21 has a first side 21a and a second side 21b opposite to the first side 21a. The active surfaces 22a of the electronic elements 22 are bonded to the circuit layer 211 of the first side 21a of the circuit portion 21 through a plurality of conductive bumps 220, and the conductive bumps 220 are encapsulated by the underfill 23. The second side 21b of the circuit portion 21 is bonded to the glass carrier 20. Further, the second side 21b of the circuit portion 21 has a plurality of conductive pads 212.
The circuit layers 211 are wafer-level circuits instead of packaging substrate-level circuits. Currently, the packaging substrate-level circuits have a minimum line width/pitch of 12/12 um, but the wafer-level circuits have a minimum line width/pitch of 3/3 um.
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In the present embodiment, an insulating layer 27 made of such as a solder mask material or PBO is selectively formed on the second side 21b of the circuit portion 21 and has a plurality of openings 270 exposing the conductive pads 212. As such, the conductive elements 28 are formed on the conductive pads 212 in the openings 270 of the insulating layer 27.
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In other embodiments, the singulation process can be performed before formation of the insulating layer 27 and the conductive elements 28.
In a subsequent process, the electronic package 2′ can be disposed on an electronic device such as a circuit board (not shown) through the conductive elements 28, and an underfill (not shown) can be formed between the electronic package 2′ and the electronic device to secure and protect the conductive elements 28.
Therefore, by replacing the conventional silicon wafer with the glass carrier 20 and bonding the glass carrier 20 to the second side 21b of the circuit portion 21 through the release film, the present invention dispenses with the conventional adhesive layer. Compared with the prior art, the glass carrier 20 can be quickly removed through the release film 200 so as to save a large amount of time (by dispensing with such as the conventional mechanical grinding and chemical etching processes), increase the product yield and reduce the fabrication cost.
Further, since the second side 21b of the circuit portion 21 is exposed after the glass carrier 20 is removed through the release film 200, the solder balls 28 can be directly formed on the conductive pads 212 or other devices can be directly connected to the conductive pads 212. As such, the present invention dispenses with such as the conventional process for forming openings in the adhesive layer and hence saves a large amount of time. Therefore, the present invention increases the product yield and reduces the fabrication cost.
The present invention further provides an electronic packaging structure 2, which has: a circuit portion 21 having opposite first and second sides 21a, 21b; at least an electronic element 22 disposed on the first side 21a of the circuit portion 21; and a glass carrier 20 disposed on the second side 21b of the circuit portion 21.
The glass carrier 20 can be disposed on the second carrier 21b of the circuit portion 21 through a release film 200.
In an embodiment, an underfill 23 is formed between the first side 21a of the circuit portion 21 and the electronic element 22.
In an embodiment, an encapsulant 24 is formed on the first side 21a of the circuit portion 21 for encapsulating the electronic element 22.
The electronic element 22 can be selectively exposed from the encapsulant 24.
Therefore, by disposing the glass carrier on the second side of the circuit portion through the release film, the present invention dispenses with the conventional adhesive layer and allows quick removal of the glass carrier, thus saving a large amount of time, increasing the product yield and reducing the fabrication cost.
Further, after the glass carrier is removed, the solder balls can be directly formed on the conductive pads or other devices can be directly connected to the conductive pads, thereby eliminating the need of the conventional process for forming openings in the adhesive layer. Therefore, the present invention increases the product yield and reduces the fabrication cost.
The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims
| Number | Date | Country | Kind |
|---|---|---|---|
| 104111896 | Apr 2015 | TW | national |
