End-Point Detection for Backside Metal Thickness Control

Abstract

A method of controlling the thickness of a layer of material applied to a surface, where the surface has one or more bodies of another material disposed therein, the another material being significantly harder than the first mentioned material, the one or more bodies of another material being disposed on the surface before the layer of material is applied to the surface, the layer of material when applied to the surface having a sufficient thickness to cover the one or more bodies of the another material, the layer of material then being mechanically reduced in thickness, such as by polishing, to expose at least a portion of the one or more bodies of the another material.

Description

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

None.

TECHNICAL FIELD

Semiconductor chip manufacturing: process control for controlling the thickness of a metal (or other) layer.

BACKGROUND

There exists a need in the art for manufacturing a device wafer or chip comprising an integrated circuit having a through-wafer or through-chip receiving cavity (which cavity may be filled, during manufacture, with a small component sometimes referred to as ‘chiplets’), which need is addressed in US patents referred to above. These patents disclose Metal-Embedded Chip Assembly for Microwave Integrated Circuits (MECAMIC) devices and processes and teach the embedding, at the wafer-level, of microelectronic transistor chiplets into a device wafer (which may also be called an interposer) or chip (which again may also be called an interposer) that may have pre-fabricated interconnects and integrated circuits including, for example, passive components. This allows for a much faster manufacturing of the resulting chip or device, at lower cost, and a scaling up of transistor technologies to circuits without cost and cycle time burden techniques, particularly when the chiplets utilize fabrication techniques and components that are more expensive to utilize on a surface area basis than are the techniques and components utilized to make the device wafer or chip which receives one or more chiplets.

The chiplets may comprise a GaN or other semiconductor chemistry devices or even passive devices (resistors, capacitors, for example, on a substrate, such as, for example, a SiC substrate. Such chiplets may be used in the manufacture of the MECAMIC devices described in the aforementioned US patents or in other applications. The device wafers or chips 20 into which the chiplets 10 are embedded may be made by a lower cost manufacturing process than that used for the chiplets. So, the resulting integrated circuit or chip 20 may be primarily of a first material (a dielectric material, for example) and the transistor chiplets 10 may be formed primarily of a second material (such as of a III/V material system material like GaN), the second material being significantly more expensive to obtain and utilize than is the first material. The resulting interposer chip, device or wafer 20 typically contains significantly more of the first material than the second material and desirously has many of the benefits afforded by III/V material system transistors, but with manufacturing costs closer to that of silicon-based technologies.

The MECAMIC technology relies on the integration of the aforementioned transistor chiplets into the volume of device or interposer wafers via a backside electroformed metal anchoring approach. The backside metal provides structural mechanical integrity to the combination of chiplets and device/interposer wafer, as well as DC and RF electrical ground.

The circuit designs in MECAMIC may use microstrips for the matching network and interconnects on 50-μm-thick SiC (or 60-μm-thick high-resistivity silicon). The substrate thickness is critical since it sets the characteristic impedance of the transmission line, and those skilled in the art will recognize that it should be close to 50Ω.

The backside metal thickness is also critical. However, currently there is no known way to measure its thickness in-situ during the process.

This disclosure focuses the design, fabrication and integration of chiplets used for “in-situ end-point detection” for backside thickness control for MECAMIC. Embedded in the wafers, these chiplets provide unique process control, but are not part of the actual product circuit (only seen at the wafer level). The chiplets also provide “polishing stop” capabilities and backside alignment capabilities (required for creating backside dicing streets).

This disclosure provides for the accurate control the backside metal thickness through an in-situ chiplet integration approach (instead of a timed removal which is not accurate). This disclosure also can provide a way to significantly slow down polishing (“polishing stop”) of the chiplets and can provide alignment markers for subsequent frontside and backside processing steps.

BRIEF DESCRIPTION OF THE INVENTION

In one aspect the present invention provides an apparatus comprising an electronic element having a first thickness with one or more end point detection chiplets disposed in cavities in the electronic element, the one or more end point detection chiplets having a second thickness greater than the first thickness and a first hardness, the electronic element being at least partially covered with a material having a hardness less than said first hardness of the end point detection chiplets and having a thickness limited by the thickness of the end point detection chiplets.

In another aspect the present invention provides an apparatus comprising an electronic element having an interior surface with one or more end point detection chiplets disposed in cavities in the electronic element, the one or more end point detection chiplets protruding from said interior surface and having a first hardness, the electronic element being at least partially covered with a material having a hardness less than said first hardness of the end point detection chiplets and having a thickness limited by a distance by which the one or more end point detection chiplets protrude from said first surface.

In yet another aspect the present invention provides a method of controlling the thickness of a layer of material applied to a surface, where the surface has one or more bodies of another material disposed therein, the another material being significantly harder than the first mentioned material, the one or more bodies of another material being disposed on the surface before the layer of material is applied to the surface, the layer of material when applied to the surface having a sufficient thickness to cover the one or more bodies of said another material, the layer of material then being mechanically reduced in thickness, such as by polishing, to expose at least a portion of the one or more bodies of said another material.

BRIEF DESCRIPTION OF THE DRAWINGS AND APPENDICES

FIGS. 1a through 1f depict MECA/MECAMIC technology taught by U.S. Pat. No. 10,998,273 issued 4 May 2021.

FIGS. 2a through 2c show additional details of a step 5 described with reference to FIGS. 1a-1f.

FIG. 3a through 3e depict an embodiment of the subject of presently disclosed technology.

FIGS. 4a through 4c are close up views of an embodiment of the presently disclosed technology corresponding FIGS. 3a-3e with FIG. 4a being a detail of a portion of FIG. 3c, FIG. 4b being a detail of a portion of FIG. 3d, and FIG. 4c being a detail of a portion of FIG. 3e. In this figure, the chiplet alignment marks become visible after metal polishing.

FIG. 5 presents a process flow block diagram.

FIG. 6 depicts alignment markings etched in the chiplets, and will be visible after the metal polishing is completed.

Appendix A depicts an example of a MECAMIC interposer layout wafer 20.

Appendix B depicts an example of a MECAMIC interposer layout reticle (10 mm) and one example of an “end point detection” chiplet 11. This would give a chiplet every 10 mm on the wafer, but denser patterns can also be easily implemented.

DETAILED DESCRIPTION

The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to (i) all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification (the contents of all such papers and documents are incorporated herein by reference) and (ii) all papers and documents which are otherwise incorporated by reference herein (but not physically filed with this specification).

All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

The MECAMIC (Metal Embedded Chiplet Assembly for Microwave Integrated Circuits) process enables rapid demonstration and low-cost manufacturing of RF integrated circuits. A fabrication approach was previously described in U.S. Pat. No. 10,998,273 issued 4 May 2021, and which is depicted by FIGS. 1a-1f hereof.

FIGS. 1a through 1f depict MECAMIC technology taught by U.S. Pat. No. 10,998,273 issued 4 May 2021. Transistor chiplets 10 are integrated into interposer wafers 20, which may be formed of a semiconductor dielectric material such as BCB, SiO₂, SiN, etc. The cross hatched regions denote a metal, preferably commonly used in semiconductor manufacturing. The interposer wafers 20 feature through-substrate chip/chiplet cavities 22. See steps 1 and 2 depicted by FIGS. 1a and 1b. The chiplets 10 are preferably formed on an adhesive-covered temporary carrier wafer 12 (step 3 depicted by FIG. 1c), flip chip bonded into the cavity 22 (see step 4 depicted by FIG. 1d) and then locked into place mechanically into the interposer wafer 20 by backside metal plating and polishing (see step 5 depicted by FIG. 1e). Step 5 is improved, as will be explained, according to inventive aspects of the present disclosure.

After step 5 a step 6 preferably occurs where the adhesive-covered temporary carrier wafer 12 is removed (the interposer wafers 20 with embedded transistors chiplets 10 are demounted from the adhesive-covered temporary carrier wafer 12) and additional interconnect metal (air bridges) are added as needed, for example, and microstrip transmission lines (not shown) to complete the circuits of the interposer 20. The interposer 20 is typically formed a number of passive elements, such as capacitors and/or resistors and a number of transistor chiplets 10. Only two passive elements and one chiplet 10 are shown in FIGS. 1a-1f for ease of illustration and explanation.

Typically, a large number of interposer chips are made simultaneously as a wafer. Only one interposer chip with one imbedded transistor chiplet 10 is shown for ease of illustration, it being understood that typically a large number of interposer chips would be manufactured at the same time as a wafer which is then diced later into individual interposer chips 20 and the individual chips 20 may embody many transistor chiplets 10.

The interposer 20 is typically formed using relatively inexpensive semiconductor processing technologies using, for example, silicon or SiC substrates, as opposed to more expensive semiconductor technologies, although more expensive semiconductor technologies may be used if desired. The chiplets 10, on the other hand, are typically formed using relatively more expensive semiconductor processing technologies using, for example, group III/V materials. So, the MECA/MECAMIC technology of FIGS. 1a-1f permits relatively expensive semiconductor processing technologies to be used to form transistors chiplets (for example) that are embedded in wafers formed utilizing less expensive fabrication technologies.

Interposer wafers, typically embodying many interposer chips (see Appendices A and B) are mated with wafer-disposed or tape-disposed transistor chiplets 10. This allows the interposer wafer to be manufactured using a relatively less expensive fabrication technology while the transistor chiplets 10, which typically only make up a small percentage of the overall area of an interposer chip, to utilize more expensive fabrication technologies.

A single interposer chip is shown in the figures, it being understood that generally speaking a large number of interposer chips would be made at the same time on a wafer. See Appendices A and B which show a wafer (Appendix A) and an individual interposer chip (Appendix B). In the following descriptions, the term wafer is used, but only a single interposer chip is depicted for ease of illustration. Also, the interposer chips (wafers) in the figures are of a far simpler circuit design than the interposer chip of Appendix B or wafer of Appendix A in order to more easily depict and describe the novel, aspects of the technology described herein.

Interposer wafers 20 are pre-fabricated with passive components (step 1), and thinned and etched for cavity fabrication (step 2). In parallel, transistor chiplets 10 are placed face down on a temporary carrier wafer. The chiplets 10 can alternatively be tape mounted as described in U.S. patent application Ser. No. 17/361,186 filed 28 Jun. 2021, entitled “Singulation Process for Chiplets”.

The MECAMIC interposer wafer 20 is placed and bonded (face down) (step 4) with the wafer bearing the transistor chiplets 10, before forming backside metal 26 preferably through a combination of sputtered metal, electroplating, and polishing (step 5). The backside metal enables 1) mechanical locking of the chiplets in the interposer wafer, 2) a backside ground for DC and RF operations of the resulting chip, and 3) thermal management. After demounting the reconstructed wafer with integrated chiplets from the carrier, topside interconnects connecting the chiplets to the wafer are fabricated preferably using traditional microfabrication processes.

FIGS. 2b and 2c show additional details of step 5 described above, where step 5 is split into two steps 5a (see FIGS. 2b) and 5b (see FIG. 2c). FIG. 2a shows the prior step 4 which is also described above with respect to FIG. 1d. The transistor chiplets 10 and the MECAMIC interposer wafer 20 have approximately the same thickness (50 μm) according to the processing described with reference to FIGS. 1a-2c, but sometimes it is desirable to utilize thicker interposer wafers (which can happen if one uses a high-resistivity Si interposer wafer instead of SiC). The high-resistivity Si silicon wafer may be on the order of 60 μm thick to maintain the same characteristic impedance of microstrip transmission lines on the topside of the interposers as interposers made using SiC. Of course, there may be other reasons why the transistor chiplets 10 have a thickness that is different than the thickness of the interposer wafer 20. This thickness differential (60 μm versus 50 μm) presents a manufacturing difficulty as will now be described.

After the chiplets 10 are bonded on temporary carrier wafer 12 with adhesive, the interposer wafer 20 with pre-fabricated cavities 22 and vias is also aligned and placed face down on the temporary carrier wafer 12 (see Step 4 of FIG. 2a (which also appears as FIG. 1d in the discussion above)). In the MECAMIC processing, the chips 10 and interposes wafers 20 are preferably of the same thickness, but it does not necessarily have to be case as explained in the preceding paragraph. Subsequently, metal is sputtered on the stack, and metal plating is carried out. Because of the topography due to the embedded chips and vias, there is thick metal that needs to be polished back down to 5 to 10 μm (see step 5b depicted by FIG. 2c). However, at present, there is no in-situ technique to measure the metal thickness accurately during polishing. Also, with planarized backside metal, one cannot further align layers (such as with a dicing street).

As shown in step 5 (see FIG. 1e and FIG. 2b) the backside metal 26 is overplated and has some topography due to the via 23 and cavity 22 being filled with backside metal 26. As such, polishing is typically performed to make the backside metal 26 thickness more uniform.

The thickness of the backside metal 26 is important, especially as wafers are scaled up in diameter. For instance, wafer warpage can be observed if the backside metal 26 thickness or stresses are too large. As such, it is preferable to polish down (known generically as planarization) to less than 10 μm of thickness of the backside metal 26.

However, according the process described in U.S. Pat. No. 10,998,273 it does not describe a way to accurately control the backside metal 26 thickness during processing, which in turn makes it difficult to control the thickness and uniformity of the backside metal backside metal 26 after planarization. Further, the planarization makes it impossible to subsequently align lithography layers. As an example, the metal would typically be removed in the dicing street while aligning those to the frontside circuits. This cannot be done according to the processes described in the aforementioned US patent because there are no visible reference patterns on the backside of the interposer wafer.

To address these issues, the use of “process control” chiplets (alternatively called “end point detection” chiplets 11 herein) will now be described. Process steps 3, 4 and 5 described above are replaced with new versions thereof described below. Chiplets 11 are preferably formed of a material, such as SiC, and thus, in the disclosed embodiments, do not function as a traditional circuit-embodied chip, but the possibility that chiplets 11 might include circuitry is not excluded from the realm of possibility.

FIGS. 3a and 3b demonstrate a process flow beginning with FIG. 3a and then carrying over to FIG. 3b. The “process control” or “end point detection” chiplets 11 are preferably 5 to 10 μm thicker (taller) than the MECAMIC interposer wafer 20. First, the transistors chiplets 10 are bonded, and then the chiplets 11 are bonded face down (see new step 3 of FIG. 3a). Of course, this could be reversed with the chiplets 11 bonded first followed by chiplets 10. Next, an interposer MECAMIC wafer 20 is also bonded (see new steps 4a-4b and FIGS. 3b-3c). Note that the interposer 20 includes additional cavities 23 for receiving these new chiplets 11. As shown by FIG. 3c, depicting new step 4b, the chiplets 11 protrude out of the back surface of the interposer wafer 20 by a height equal to (or slightly greater than) the desired thickness of the soon-to-be deposited metal layer 26. The backside metal layer 26 is then deposited preferably by sputtering metal and electroplating metal, similar to the original approach described in the aforementioned U.S. patent and shown herein as new step 5a (see FIG. 3d).

After depositing the metal 26, it is polished down with the “process control” or “end point detection” chiplets 11 providing an in-situ endpoint detection surface as depicted by new step 5b (see FIG. 3e). This effectively means that the “process control” or “end point detection” chiplets 11 provide a way to accurately control the thickness of the deposited backside metal 26. The polishing step is completed when the “process control” chiplets become visible, as shown in new step 5b depicted by FIG. 3e. Because the “process control” chiplets do not polish as quickly as does the deposited metal layer (for example, if copper is used as the metal of the metal layer, it polishes away 100 times faster than does SiC, if SiC is the material selected for the chiplets 11), the chiplets 11 not only become visible, but due to their comparatively greater hardness, they also provide an effective “polishing stop”, to prevent significant over-polishing of the metal layer 26.

Chiplets 11 are used for backside metal 26 end point detection and preferably also for backside alignment. These chiplets are 5 to 10 μm thicker than the interposer wafer 20. After metal plating (new step 5a), the backside metal 26 is polished back all the way to these chiplets 11—thus the “end point detection” label sometimes used for these chiplets herein. This process accurately controls the backside metal 26 thickness to provide more uniformity and thickness control, thereby also reducing wafer warpage.

FIG. 5 shows the process utilizing the “process control” or “end point detection” chiplets 11 in a block diagram format.

FIG. 6 shows a close-up view of the “process control” or “end point detection” chiplet 11 as seen through the backside metal 26 electroplating and polishing processes. In this figure, the alignment feature, which preferably includes a recessed (possibly etched) alignment mark or marks. Marks are preferably formed on both the upper and lower surfaces of the chiplets 11 before they are mounted as depicted by FIG. 3a. The chiplet 11 should be harder than the material selected for metal 26. The backside recessed marks are filled with metal 26 during the plating process but visible after polishing, facilitating dicing the wafer 20 into individual interposer chips.

Appendices A and B show how the chiplets 11 can be inserted into a wafer layout. Appendix A shows a wafer with a plurality (72 in this case) of the individual interposer chips, while Appendix B shows an individual chip with one (in this embodiment) “process control” or “end point detection” chiplet 11 and a plurality of transistor chiplets 10. The “process control” or “end point detection” chiplets 11 may be approximately 300×300 μm in size, but can be smaller (100×100 μm, for example) or larger. Preferably placing one “process control” chiplet per chip reticle (every 10 mm in this embodiment). However, the density could either be increased or decreased based on the process margin.

Having now described the invention in accordance with the requirements of the patent statutes, those skilled in this art will understand how to make changes and modifications to the present invention to meet their specific requirements or conditions. Such changes and modifications may be made without departing from the scope and spirit of the invention as disclosed herein.

The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Section 112, as it exists on the date of filing hereof, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . .”

Modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the invention. The components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses may be performed by more, fewer, or other components. The methods may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

Claims

1. An apparatus comprising an electronic element having a first thickness with one or more end point detection chiplets disposed in cavities in the electronic element, the one or more end point detection chiplets having a second thickness greater than the first thickness and a first hardness, the electronic element being at least partially covered with a material having a hardness less than said first hardness of the end point detection chiplets and having a thickness limited by the thickness of the end point detection chiplets.

2. The apparatus of claim 1 wherein the electronic element has additional cavities therein with transistor chiplets disposed therein.

3. The apparatus of claim 2 wherein a number of the additional cavities exceed a number of the cavities in which end point detection chiplets are disposed by at least a factor of 10.

4. The apparatus of claim 2 wherein the electronic element has at least a single cavity in which an end point detection chiplet is disposed and a plurality of additional cavities in which the transistor chiplets are disposed, the electronic component being formed primarily of a first material and the transistor chiplets being formed primarily of a second material, the second material being more expensive to obtain and utilize than is the first material.

5. The apparatus of claim 1 wherein the material is SiC and the material is selected from the group consisting of Cu and Al.

6. The apparatus of claim 1 wherein the one or more end point detection chiplets have one or more alignment marks formed on at least one end surface thereof.

7. An apparatus comprising an electronic element having an interior surface with one or more end point detection chiplets disposed in cavities in the electronic element, the one or more end point detection chiplets protruding from said interior surface and having a first hardness, the electronic element being at least partially covered with a material having a hardness less than said first hardness of the end point detection chiplets and having a thickness limited by a distance by which the one or more end point detection chiplets protrude from said first surface.

8. The apparatus of claim 7 wherein the electronic element has additional cavities therein with transistor chiplets disposed therein.

9. The apparatus of claim 8 wherein a number of the additional cavities far exceed a number of the cavities in which end point detection chiplets are disposed.

10. The apparatus of claim 8 wherein the electronic element has at least a single cavity in which an end point detection chiplet is disposed and a plurality of additional cavities in which the transistor chiplets are disposed.

11. The apparatus of claim 7 wherein the material is SiC and the material is selected from the group consisting of Cu and Al.

12. The apparatus of claim 7 wherein the one or more end point detection chiplets have one or more alignment marks formed on at least one end surface thereof.

13. A method of controlling the thickness of a layer of material applied to a surface, where the surface has one or more bodies of another material disposed therein, the another material being harder than the first mentioned material, the one or more bodies of the another material being disposed on the surface before the layer of the first mentioned material is applied to the surface, the layer of the first mentioned material when applied to the surface having a sufficient thickness to cover the one or more bodies of said another material, the layer of the first mentioned material then being mechanically reduced in thickness, such as by polishing, to expose at least a portion of the one or more bodies of said another material.

14. The method of claim 13 wherein the said surface is a surface of an electronic element, the electronic element having one or more one cavities therein for receiving said one or more bodies of said another material, the one or more bodies of said another material having at least a portion of the one or more bodies of said another material protruding from said surface.

15. The method of claim 14 further including forming the electronic element as one in an array of electronic elements and wherein the at least a portion of the one or more bodies of said another material each include one or more alignment marks formed on at least one end surface of the bodies of said another material, the one or more alignment facilitating dicing the array of electronic elements into individual ones of said electronic elements.