Patent Application
20190198442
The present invention relates to semiconductors devices, and more particularly to field effect transistor (FET) devices for use in power management, communications and applications including semiconductor die, fabricated using wafer-level, front end of line (FEOL), compound semiconductor, including gallium arsenide (GaAs), gallium oxide (Ga2O3), gallium nitride (GaN) process technologies, embedded in a substrate with interconnect layers fabricated using back end of line (BEOL) process technologies.
A device and method are described for a front end of line (FEOL) and integrated back end of line (BEOL) field effect transistor (FET) device. The FET includes one or more semiconductor die, fabricated using FEOL process technologies, embedded in a substrate with multiple metal layers fabricated using BEOL process technologies.
The semiconductor die may be fabricated using wafer-level FEOL gallium arsenide (GaAs), gallium oxide (Ga2O3) or gallium nitride (GaN) process technologies, and may include many chiplets. Each chiplet may be a functional building block including many source, drain and gate fingers in an active area, and source, drain and gate conductors in a non-active area. A gate width per unit area (Wg/A) and, hence, current density of each chiplet may be increased through use of a novel layout, which reduces a source/drain finger pitch in the active FET area, increases the gate width of each finger without materially increasing the non-active area. Thin FEOL metal layers may serve to reduce the size of the source/drain fingers. Lateral current flow in the thin FEOL metal interconnect layers may be a very low current flow in each of many parallel source/drain fingers in each chiplet. In the non-active area, a thin but large cross section area of source, drain and gate conductors interconnect the source, drain and gate fingers, respectively, within each chiplet and provide vertical connections to substantially thicker, hence substantially lower resistance, metal layers fabricated using low cost BEOL process technologies. At completion of FEOL processing, the semiconductor die may not be a fully functional FET because the chiplets may not be fully connected to each other. The FEOL metal layers used for the source, drain and gate conductors are generally relatively thin (typically a few microns), which is sufficient for high current vertical flow to the substantially thicker BEOL metal layers, but may be too thin to interconnect the chiplets on the semiconductor die. The semiconductor die may include one or more metal interconnect layers and a final passivation layer with passivation openings to the source, drain and gate conductors.
One or more of the incomplete semiconductor die may be embedded in a substrate. Low cost BEOL process technologies may be used to form multiple metal layers, each with a progressively increasing thickness and cross section area, and via bars that provide horizontal, in addition to vertical, interconnection of various features in adjacent metal layers. Lateral flow of high current across the large area FET device may traverse these ultra low resistance metal layers and via bars, whose total thickness may exceed 100 microns, which may be more than ten times the total thickness of the FEOL metal layers.
The BEOL metal layers and via bars may employ a larger area than the area of the semiconductor die, which further lowers the electrical and thermal resistance and increases the amount of heat spreading material and, hence, thermal mass/time constant.
Certain embodiments of the present technology are illustrated by the accompanying figures. It will be understood that the figures are not necessarily to scale and that details not necessary for an understanding of the technology or that render other details difficult to perceive may be omitted. It will be understood that the technology is not necessarily limited to the particular embodiments illustrated herein.
While the disclosed technology is available for embodiment in many different forms, there is shown in the drawings and will herein be described in detail several specific embodiments with the understanding that the present disclosure is to be considered as an exemplification of the principles of the technology and is not intended to limit the technology to the embodiments illustrated.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present technology. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used in this specification, the terms “include,” “including,” “for example,” “exemplary,” “e.g.,” and variations thereof, are not intended to be terms of limitation, but rather are intended to be followed by the words “without limitation” or by words with a similar meaning. Definitions in this specification, and all headers, titles and subtitles, are intended to be descriptive and illustrative with the goal of facilitating comprehension, but are not intended to be limiting with respect to the scope of the inventions as recited in the claims. Each such definition is intended to also capture additional equivalent items, technologies or terms that would be known or would become known to a person having ordinary skill in this art as equivalent or otherwise interchangeable with the respective item, technology or term so defined. Unless otherwise required by the context, the verb “may” indicates a possibility that the respective action, step or implementation may be performed or achieved, but is not intended to establish a requirement that such action, step or implementation must be performed or must occur, or that the respective action, step or implementation must be performed or achieved in the exact manner described.
It will be understood that like or analogous elements and/or components, referred to herein, may be identified throughout the drawings with like reference characters. It will be further understood that several of the figures are merely schematic representations of the present technology. As such, some of the components may have been distorted from their actual scale for pictorial clarity.
A FET generally comprises alternating source fingers and drain fingers, and gate fingers disposed between source and drain fingers. Dimensions of the source, drain, and gate fingers may be constrained by interconnections to and from the sources, drains and gates and a breakdown voltage of the FET.
A FET die may contain many small, individual functional building blocks or chiplets. Each chiplet may contain many source, drain and gate fingers. The chiplets may be organized into one or more large individual FETs or one or more pairs configured as a large upper FET connected in a half-bridge configuration to a large lower FET.
FETs for power management, communications and other applications require significant increases in continuous and peak (short duration) current carrying capacity. Methods for increasing current capacity include increasing the gate width per unit area (Wg/A) and, hence, current density of each chiplet; paralleling together multiple chiplets; and reducing their interconnect resistance. Methods for increasing peak current capacity include increasing the thickness and cross sectional area of the FET's metal interconnects to increase the thermal mass/time constant. Increasing current density of the chiplets and a number of chiplets paralleled together may create a need for a low electrical and thermal resistance path from the semiconductor die to its package and printed circuit board.
Conventional FET device fabrication includes producing a fully functional semiconductor die using wafer-level, front end of line (FEOL) process technologies, packaging the semiconductor die using back end of line (BEOL) process technologies, and placing the packaged semiconductor die on a printed circuit board also using BEOL process technologies. In some embodiments the fully functional die is not packaged, and a bare die is mounted onto the PCB or even embedded into the substrate. However unlike the methods described herein, a delineation is made between the FEOL and BEOL processes—the FEOL process technologies, device geometries, design tools, suppliers and manufacturers are different from those used in the BEOL.
FEOL wafer-level processes may employ multiple metal layers, each with progressively increasing thickness and cross section area, to reduce the interconnect resistance, increase the current capacity and bridge the dimensional gap between the fine geometries of the FET's first metal interconnect layer and the course geometries of the FET's last metal layers that connect the FET to its package. However, the FEOL metal layers are expensive and very thin (the total thickness of the FEOL metal layers is typically less than 10 microns), so they have high resistance. The interconnect resistance of large FETs is high due to a need to fully interconnect the many individual FETs that make up the large FET over long distances. Lateral high current flow in thin FEOL metal interconnect layers limits the current carrying capacity and the ability to get the heat out.
As would be understood by persons having ordinary skill in the arts with the present disclosure before them, a FET generally comprises alternating source fingers and drain fingers, and gate fingers disposed between source and drain fingers. Dimensions of the source, drain, and gate fingers are generally constrained by routing of signals and high currents to and from the sources, drains and gates. The spacings between these features may also be constrained by a breakdown voltage of the FET. A person having ordinary skill in the art with the disclosure before them would understand that the die 102 may be considered to be composed of thousands of individual small FETs at the FEOL level, that may be organized into one large FET, or a large upper FET and a large lower FET (or multiple large FETs, eg., 3, 4, 5, 6, 7, 8 or more large FETs) using the BEOL connections. For example, the thousands of individual small FETS fabricated at the FEOL level can then be connected in 1 large FET, 2 large FETs etc., using the BEOL levels. In some embodiments, a decision whether to fabricate 1, 2, or more large FETs and how to configure the BEOL layers can be made before or after completing the FEOL fabrication of GaAs or SI die. Thus, the exact same die can be taken from a wafer upon completing FEOL processing and can be embedded multiple different ways, while deciding how to organize it after fabrication of the die is complete. Furthermore, a standardized die may be processed in the FEOL to optimize the die for yield, and then a wide range of products, each having a desired different performance may be realized utilizing an inexpensive BEOL processing to integrate one or more die together.
The segment 110 may be described as having non-active areas 142 and 144, and active areas 146. The active areas include the sources, drains, and gates.
A first passivation layer may be disposed above the ohmic layer 120 and gate metal layer 122 and below the metal 1 layer 126 to isolate the metal 1 layer 126 from the gate metal layer 122 and the ohmic layer 120. Vias of the via 1 layer 124 may provide communication through the first passivation layer from the metal 1 layer 126 to the gate metal layer 122 and ohmic layer 120.
For example, gate conductor vias 507 of the via 1 layer 124 may provide connection through a first passivation layer from a gate metal 1 conductor 607 of the metal 1 layer 126 to a gate conductor 407 of the gate metal layer 122. Similarly, drain finger vias 504 of the via 1 layer 124 may provide connection through the first passivation from drain metal 1 fingers 604 of the metal 1 layer 126 to ohmic drain fingers 204 of the ohmic layer 120.
Similarly, source finger vias 502 of the via 1 layer 124 may provide connection through the first passivation from source metal 1 fingers 602 of the metal 1 layer 126 to ohmic source fingers 202 of the ohmic layer 120. The first passivation layer may isolate source metal 1 conductors 606 from a gate conductor 407. It is noteworthy that a thin via 1 layer 124 may contribute to a reduction of dimensions of the via features that can be fabricated over the source and drain ohmic metal fingers 202/204, thus, permitting a reduction in dimensions of the source/drain fingers. In some embodiments, the via 1 layer 124 is very thin, e.g., less than 0.1, 0.25, 0.5, 1.0 microns. For example a thin nitride may be used for making small via features of the via 1 layer 124 and/or contacts. This may serve to minimize source and drain finger width. As a result, the thinner passivation layer enables the fabrication of a narrower source/drain, while a thicker passivation layer results in wider source/drain sizes.
The section layers of
Similarly, drain conductor vias (not shown in
A third passivation may be disposed between the second metal layer 130 and a third metal layer (illustrated and described elsewhere herein). The third passivation layer may separate front end of line (FEOL) processes and back end of line (BOEL) processes. Openings through the third passivation layer may form a passivation 3 opening layer 132 to provide communication through the third passivation layer between the metal 3 layer and the metal 2 layer.
Source finger vias 502 may provide contact between the source metal 1 fingers 602 and the source ohmic fingers 202. Similarly, drain finger vias 504 may provide contact between the drain metal 1 fingers 604 and the drain ohmic fingers 204. It may be appreciated that a thin passivation layer allows for a small via and hence smaller ohmic and metal1 layers in regards to x and y dimensions. This allows the gate pitch to be as small as possible. The pitch may be equal to the width of the source/drain plus the spacing required between the source/drain ohmic region and the gate. The source/drain to gate spacing may be dependent on the breakdown properties, and so the thin passivation allows for a more narrow source/drain and hence reduces the pitch. The pitch may be reduced even more as a result of not making a connection between metal 2 and metal 1 over the active region. For example, a source/drain may be 1.4 um wide. However, if the connection were made over the active area that width would have to increase from 1.4 um to Sum. As a result, the present pitch of 3.3 um would more than double to 6.9 um. The thickness of the metal 1 may be made as thick as possible for the given pitch so as to minimize the resistance of the source/drain fingers and, hence, allow for wider FETs which in turn improves the Wg/A at the expense of switching time.
The source metal 1 conductor 606 is disposed on the first passivation layer and separated from the underlying gate metal conductor 407 by the first passivation layer. However, the source metal 1 conductor is contiguous with the source metal 1 fingers 602.
Lateral current flowing through the source metal 1 fingers (thin vertical arrows) may encounter relatively high resistance in the active area 146 because individual source fingers may be relatively thin and narrow for packing more source fingers into the active area. However, it may be appreciated that the current through individual fingers may be relatively low, and packing more source fingers into the active area provides for additional source fingers to conduct the current in parallel. Moreover, the distance that the lateral current flows in the active area 146 through the source fingers may be relatively short. In some embodiments, the distance of the lateral current flow through the source and/or drain fingers is less than about 200 microns.
Interconnections to the source metal 1 fingers 602 and ohmic fingers 202 may be provided through the source metal 1 conductor 606, which is substantially wider than the source metal 1 fingers 602. Moreover, the source metal 1 conductor 606 is disposed above the gate metal (separated from the gate metal by the first passivation layer) and outside the active area 146 and within the non-active area 142. Thus, lateral interconnect current flowing through the source metal 1 conductor 606 (thick horizontal arrows) encounters low resistance and may be substantially higher than the source fingers. However, the bulk of the current in these conductors flows vertically up into metal 2, and there is little lateral current flow. Any lateral current flow happens at the ends of the conductor. In some embodiments, the metal 1 layer 126 is fabricated using a layer of copper about 2 microns thick. Other metals and/or thickness may be used. Examples include gold, aluminum, and/or the like. For example, gold at a thickness of 1 micron may be used.
Interconnections to the gate metal fingers 403 may be provided through the gate metal 1 conductor 607, through the first passivation layer by way of the gate via 507 to the gate metal conductor 407, which is substantially wider than the gate metal fingers 403. Moreover, the gate metal 1 conductor 607 is disposed outside the active area 146 and within the non-active area 142. The second passivation layer (not illustrated) may be disposed over the metal 1 layer illustrated in
A gate via 2 interconnect 807 may provide for gate voltage to be interconnected through the second passivation layer from the gate metal 2 conductor 907 to the gate metal 1 conductor 607. Source via interconnects 806 in the second passivation layer may provide interconnection between the source metal 2 conductor 906 and the source metal 1 conductor 606, which is in turn connected to the source metal 1 fingers 602 disposed on the source ohmic fingers 202. Similarly, drain vias 808 may provide contact between the drain metal 2 conductor 908 and the drain metal 1 conductor 608, which is in turn connected to the drain metal 1 fingers 604 disposed on the drain ohmic metal fingers 204.
The gate via 2 interconnect 807 may be sized relatively small to accommodate other features, e.g., vias 1006 and/or 1008. Typical dimensions for the gate via 2 interconnect 807 may be 2-4 microns thick, by 10-20 microns wide by 20-44 microns long. The gate via 2 interconnect 807 may also serve to move heat up and out of the FEOL layers.
The source via 2 interconnect 806 functions as both a lateral and vertical interconnect. The majority of current flows vertically up into the thick metal 2 and then up into even thicker BEOL metal layers. Some might call this a via. However, it is noteworthy that the “via” extends continuously for substantially all of the source/drain metal1 conductor length. In doing so, the “via” effectively becomes a lateral interconnect, rather than a traditional vertical via and increases the thickness of the metal1 conductor for lateral current flow. The source via 2 interconnect 806 may also be sized for effective deposit of substantial amounts of metal such as copper within the interconnect, even using FEOL processes. At the ends of the conductor, there may be some lateral current flow through the metal 1 conductors and in that case the via acts as a lateral interconnect. In addition to the 2 um metal 1 layer, there is additional 3-4 um of the via plus another 4 um of the metal 2 layer for a total of 9-10 um, instead of just the 2 um in parallel with 4 um with intermittent pieces of 3-4 um as is found in typical FEOL process. The drain via 2 interconnect 808 is similarly sized and disposed on the drain metal 1 conductor 608. Thus, the source via 2 interconnect 806 may conduct substantially more current than a typical via. The source via 2 interconnect 806 may also serve to move heat up and out of the FEOL layers.
In some embodiments, a via interconnect such as described with respect to the source/drain/gate via 2 interconnects, may be described as a series of vias that are connected to form a continuous line of contiguous vias. Thus, the via interconnect may be described as a long interconnect bar, rather than many discreet vias. Whereas the conventional practice is to constrain the width of vias to comparative smaller sizes and the length to the same order of magnitude of the widths, the via interconnect may have a length that is orders of magnitude greater than the width. These longer dimensions of the source/drain via 2 interconnect, and more particularly lengths that are orders of magnitude greater than widths, contribute to conducting substantially more current and heat though the FET. Moreover, a via interconnect that forms a single long bar disposed along substantially the entire length the source/drain metal 1 conductor virtually eliminates all lateral conduction of current between discreet vias within the source/drain metal 1 conductor and within the source/drain metal 2 conductor.
It is noteworthy that the source, drain, and gate via 2 interconnects may be sized for conducting large currents and heat by virtue of being positioned almost entirely in the non-active region without impacting the gate pitch. Its sizing impact on Wg/A is second order. Furthermore, this positioning within the non-active region permits fabricating active regions of source/drain/gate fingers without positioning any vias within active region over these features. Having no vias over the metal 1 layer of the active region permits reducing the source-drain pitch by fabricating source/drain fingers having substantially smaller dimensions than would be feasible if vias were used to remove current from the source/drain metal 1 layer in the active region.
Like the metal1 source/drain conductors, the metal 2 layer serves primarily to provide a vertical interconnection from a relatively thin metal 1 layer to a substantially thicker metal 3 layer (illustrated and discussed in more detail elsewhere herein). This may serve to bridge a dimensional gap between the metal 1 and metal 3 layers. In some embodiments, the metal 2 is produced using a BEOL process, e.g., when the BEOL process can provide interconnection to fine geometries of FEOL via 2 layers. Otherwise, the metal 2 layer may be produced using FEOL process. In essence, the amount of processing done in the FEOL process may be the minimum required to organize the layout to conform to ground rules of the BEOL process. In some embodiments no actual metal layers need to be processed in the FEOL process. This may be referred to as embedded in interconnect. In some embodiments, metal 2 is fabricated using copper having a thickness of about 4 microns. The metal 2 layer includes source metal conductors 906, gate metal 2 conductors 907, and drain metal 2 conductors 908. Simply put, because metal 2 primarily provides vertical connection, it can be thinner than one might expect when used to carry large currents. Since it does not have to be thick, the result is the potential to lower FEOL costs and simplify FEOL processing.
The source metal 2 layer is disposed on the second passivation layer, which generally separates the metal 2 from the underlying metal 1 except at the vias in the second passivation layer. The source metal 2 conductor 906 may be connected through the second passivation layer by way of the source via 2 interconnect 806 in the via 2 layer 128. Similarly, the drain metal 2 conductor 908 may be connected through the second passivation layer by way of the drain via 808 in the via 2 layer 128. Also, the gate metal 2 conductor 907 may be connected through the second passivation layer by way of the gate via 807 in the via 2 layer 128. The third passivation layer (not illustrated) may be disposed over the metal 2 layer illustrated in
It is noteworthy that the second passivation layer (via 2 layer 128) isolates the entire the active region 146 from the metal 2 layer 130 and subsequent metal layers deposited directly on the die 102 using the BEOL processes. Thus, features of the metal 2 layer that extend into the active region 146 because they are larger than the non-active region, may be fabricated on the second passivation region. While the second passivation layer isolates metal 2 from the active region, passivation layer 2 and the final FEOL passivation layer together isolate the active area from BEOL metal layers. As a result, the first BEOL metal layer may be substantially removed from metal 1, reducing the parasitics. That is one reason to route the gate predominately using the first BEOL metal layer. There may be less coupling capacitance and the metal may be thicker, which may provide lower resistance and result in faster switching speeds. This may be a desirable result in a power device. Furthermore, utilizing the BEOL metal layers may result in a smaller die than if the layers were fabricated using the FEOL metal layers.
The chiplet 118 includes gate fingers, source fingers, drain fingers, an active region and non-active regions, along with FEOL and BEOL connectors to provide signals and currents to the chiplet 118. In the FEOL metal layers, lateral current flow may be generally confined to the chiplet 118. For example, lateral flow through gate, drain, and source fingers is at most from about the center of the active area to the nearest non active region, or about half the width of the chiplet 118. This is a relatively short distance, and since there are many fingers in parallel, the current in each finger may be lower while the total current flow in parallel through all the fingers may be higher. Furthermore, the resistance may also be low.
However, lateral current flow that traverses multiple chiplets may be generally confined to flow within thick metal 2 which may be widened to accommodate the lateral current flow without impacting Wg/A. Moreover, the BEOL thick metal layers may be parallel to the FEOL layers and hence the lateral current flow may take place in very low resistance interconnect composed of both the FEOL and BEOL layers. Lateral current from metal 2 is then, in turn, communicated vertically to the metal 1 layer only through via interconnects 806, 807, and 808 in the via 2 layer that are disposed over the non-active area. A person having ordinary skill in the art with the disclosure before them would understand that the die may be considered to be composed of thousands of individual small FETs at the FEOL level, that may be organized into a large upper FET and a large lower FET (or multiple large FETs, eg., 3, 4, 5, 6, 7, 8 or more large FETs) using the BEOL connections.
The FET die 102 of
Features of the metal 3 layer 1100 include a metal 3 switch node 1108 composed of the upper FET source and lower FET drain, a metal 3 node VDC 1106A composed of the upper FETs drain, a metal 3 PGND node 1106B composed of the lower FETs source, and a metal 3 upper gate 1107A, and metal 3 lower gate 1107B. The passivation 3 openings are below the metal 3 layer 1100 and between the metal 3 layer 1100 and the metal 2 layer 130, The passivation 3 openings, thus, provide communication between the metal 3 layer 1100 and metal 2 layer 130. In general the metal 3 layer 1100 has a greater thickness than the metal 2 layer. A typical thickness for the metal 3 layer 1100 is about 12 microns. A typical thickness for the metal 2 layer 130 is about 4 microns. This is because the current in the metal 2 layer flows mostly vertically so it can be made thinner, which may serve to simplify the FEOL processing and consequently lower the cost
The vias of the via 3 layer 1300, which are below the metal 4 layer 1400, are also between the metal 3 layer 1100 and the metal 4 layer 1400. The vias of the via 3 layer 1300, thus, provide vertical communication between the metal 3 layer 1100 illustrated in
The vias of the via 4 layer 1500, which are below the metal 5 layer 1600, are also between the metal 4 layer 1500 and the metal 5 layer 1600. The vias of the via 4 layer 1500, thus, provide vertical communication between the metal 4 layer 1400 illustrated in
Current from the source fingers 202 may be conducted laterally through the metal deposited in the source finger via 502 and the metal 1 finger 602 to the source metal 1 conductor 606. The source via 2 interconnect 806 conducts current (arrows) vertically from the source metal 1 conductor 606 to the source metal 2 conductor 906, where the source current is conducted vertically through the source conductor passivation 3 opening 1006 to the source metal 3 conductor 1106A/B, then through the source via 3 conductor 1306A/B to the source metal 4 conductor 1406A/B, which is connected through the source via 4 conductor 1506A/B to the source metal 5 conductor 1606A/B. A first passivation layer 305 is also illustrated, and is disposed between the substrate of the die 102 and a second passivation layer 705. The second passivation layer 705 is disposed between the first passivation layer 305 and a third passivation layer 1005. The first, second, and third passivation layers are described in more detail elsewhere herein.
Current (arrows) to or from the gate fingers 403 may be conducted laterally through the gate metal fingers 403 (disposed between the source fingers 202 and drain fingers 204) to the gate metal 407. The gate current is then conducted vertically through gate metal 407, through the gate conductor metal in the gate via 507 of the via 1 layer 124, and through the gate metal 1 conductor 607. The gate conductor 607 conducts gate current laterally to the gate via 807. For example, see
The gate via 807 in the via 2 layer 128 conducts gate current vertically from the gate metal 1 conductor 607 to the gate metal 2 conductor 907, which conducts the gate current through the passivation 3 gate vias 1007 to the gate metal 3 conductor 1107. Note, the gate via 807, gate metal 2 conductors 907, passivation 3 gate vias 1007, and gate metal 3 conductor 1107 of
Current from the drain ohmic fingers 204 may be conducted progressively through the metal deposited in the drain via 1 finger 504 to the drain metal 1 finger 604. Note that the drain metal 1 finger 604 ends without contacting the source metal 1 conductor 606. Instead, the opposite end of the drain metal 1 finger 604 is in contact with the drain metal 1 conductor 608. Thus, drain current is conducted laterally through the drain via 1 finger 504 and drain metal 1 finger 604 to the drain metal 1 conductor 608.
The drain via 1 conductor 808 then conducts drain current vertically from the drain metal 1 conductor 608 to the drain metal 2 conductor 908, which in turn conducts the drain current vertically through the drain conductor passivation 3 opening 1008 to the drain metal 3 conductor 1108, which is connected through the drain via 3 conductor 1308 to the drain metal 4 conductor 1408, which is connected through the drain via 4 conductor 1508 to the drain metal 5 conductor 1608 in a manner analogous to illustrations in
However, drain metal 1 conductor 608, drain via 1 conductor 808, drain metal 2 conductor 908, drain conductor passivation 3 opening 1008, drain metal 3 conductor 1108, drain via 3 conductor 1308, drain metal 4 conductor 1408, drain via 4 conductor 1508, and the drain metal 5 conductor 1608 are not illustrated in the cross section figures.
It is important to note that as the current travels from the fingers to the metal 5 layer, the metal thickness and cross section area increases at each level. Effectively this results in a progressively increasing cross section area in the direction of the current conduction at each layer. This increase in thickness cross section area of the metal at each layer progressively reduces the resistance and/or impedance for conducting the current and heat.
For example, the source current may be conducted laterally along the source fingers through metal in the source via 1 and source metal 1 fingers to the source metal 1 conductor 606. These features may be relatively thin, typically 2 microns. However, there may be many fingers in the active area, so each finger can be conducting relatively small currents that in parallel cumulatively constitute a relatively large current. In the process, the source current (and similarly the drain and gate currents) is conducted out of the active area that is entirely composed of ohmic fingers to the non-active area composed of connecting elements where the currents can be gathered and moved vertically out of the device.
Upon reaching the source metal 1 conductor (and similarly drain and gate metal 1 conductors), the current conduction becomes more vertical through the via 2 features to the source metal 2 conductor. The via 2 features present cross section areas in the direction of conduction that are substantially lager than the metal 1 and via 1 fingers. The via 2 features can have substantially larger cross section areas because they are disposed in the non-active region of the device.
The metal 2 conductor features are also disposed above the non-active region of the device. However, the metal 2 conductor features are also isolated from the active region and makes no direct contact with the active area. Thus, the widths of metal 2 conductor features are not constrained by dimensions of the non-active region. This allows the cross section area of features in the metal 2 conductor layer to be substantially larger than the cross section area of features in the metal 1 conductor layer and larger than the cross section area of the via 2 features. This is illustrated in
As discussed elsewhere herein, the metal 2 features primarily serve to provide vertical connection from the metal 1 features to the metal 3 features. For example, a typical thickness for the source metal 2 conductor 906 is about 4 microns. However, that is along the vertical direction of conduction. Since the cross section area of the source metal 2 conductor 906 is substantially larger than the cross section area of the source metal 1 conductor 606 (see, e.g.,
The metal 3 features are even thicker and have even larger cross section areas than the respective metal 2 features to which they are connected. For example, the source metal 3 conductors 1106A/B illustrated in
In some embodiments, a thickness for metal 3 features is about 12 microns, for metal 4 features about 18 microns, and for metal 5 about 40 microns. However, these are only exemplary dimensions; other dimensions are contemplated. The metal 3 features (metal 3 layer 1100 shown in
While the described structures illustrate an example of 2 metal FEOL layers on the GaAs die and 3 metal layers in the BEOL layers, other configurations and/or materials (e.g., Si) are contemplated. Persons having ordinary skill in the art with this disclosure before them would understand that there could be 3 metal FEOL layers and 6 metal BEOL layers. The number of layers in FEOL and BEOL depends on the application and desired results.
The larger features of the metal 3-5 layers and via 3-4 may be fabricated using Back End of Line (BEOL) technology, which is less expensive than Front End of Line (FEOL) technology. Optionally, the metal 2 layer and passivation 3 openings may be fabricated using either FEOL or BEOL technology. The FEOL and BEOL technology may be integrated by fabricating BEOL features directly on a die that has been fabricated using FEOL technology.
The above description is illustrative and not restrictive. This patent describes in detail various embodiments and implementations of the present invention and the present invention is open to additional embodiments and implementations, further modifications, and alternative constructions. There is no intention in this patent to limit the invention to the particular embodiments and implementations disclosed; on the contrary, this patent is intended to cover all modifications, equivalents and alternative embodiments and implementations that fall within the scope of the claims. Moreover, embodiments illustrated in the figures may be used in various combinations. Any limitations of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.
This application claims the priority benefit of, pending U.S. provisional patent application No. 62/609,278, filed Dec. 21, 2017, and titled, “FRONT END OF LINE AND INTEGRATED BACK END OF LINE GaAs DEVICE,” and pending U.S. provisional patent application No. 62/782,625, filed concurrently with this application on Dec. 20, 2018, and titled, “FEOL/BEOL HETEROGENEOUS INTEGRATION,” which are all incorporated by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62609278 | Dec 2017 | US | |
| 62782625 | Dec 2018 | US |
