Half-bridge circuit using flip-chip GaN power devices

Description

FIELD

The present invention relates generally to power conversion circuits and in particular to power conversion circuits utilizing one or more GaN-based semiconductor devices.

BACKGROUND

Electronic devices such as computers, servers and televisions, among others, employ one or more electrical power conversion circuits to convert one form of electrical energy to another. Some electrical power conversion circuits convert a high DC voltage to a lower DC voltage using a circuit topology called a half bridge converter. As many electronic devices are sensitive to the size and efficiency of the power conversion circuit, new half bridge converter circuits and components may be required to meet the needs of new electronic devices.

SUMMARY

In some embodiments a half bridge circuit comprising a low side circuit disposed on a first GaN device and a high side circuit disposed on a second GaN device is disclosed. The low side circuit includes a low side switch having a low side switch control gate and a low side switch driver having an output connected to the low side switch control gate. The high side circuit includes a high side switch having a high side control gate and a high side switch driver having an output connected to the high side switch control gate.

In some embodiments the half bridge circuit may further include a low side control circuit coupled to the high side and the low side switch drivers. In further embodiments a level shifter may be configured to couple one or more signals from the low side control circuit to the high side switch driver. In other embodiments the high side circuit includes a level shift receiver coupled to the level shifter, and the level shift receiver includes a signal modulator that is coupled to the high side switch driver.

In some embodiments the half bridge circuit includes a level shifter having an inverter comprising a resistor pull up and a pull down transistor. In other embodiments the half bridge circuit includes one or more pulse generators and a shoot through protection circuit configured to prevent simultaneous conduction of high side and low side switches. In further embodiments at least one of the low side switch driver and the high side switch driver have at least one delay circuit. In yet further embodiments the low side circuit includes a startup circuit. In some embodiments the high side circuit includes a high side controller coupled to the high side switch driver, and the low side circuit includes a low side controller coupled to the low side switch driver and the high side controller. In other embodiments at least one of the low side circuit and the high side circuit have an ESD clamp circuit.

In some embodiments an electronic power conversion component includes a package base, a first die secured to the package base and comprising a low side circuit, a second die secured to a package base and comprising a high side circuit and an electrically insulative mold compound encapsulating at least a portion of a top surface of the package base and the first and the second dies. In further embodiments the low side circuit may include a low side switch having a low side switch control gate and a low side switch driver having an output connected to the low side switch control gate. In yet further embodiments the high side circuit may include a high side switch having a high side control gate, and a high side switch driver having an output connected to the high side switch control gate.

In some embodiments the package base includes a leadframe. In other embodiments the component may include an insulator mounted to the leadframe, where the first die is mounted to the leadframe and the second die is mounted to the insulator. In other embodiments the package base includes a printed circuit board. In further embodiments at least one of the first and the second die comprise GaN. In yet further embodiments the component may have at least one electrical connection from the first die to the second die, formed within the component.

In some embodiments a method of operating a half bridge power conversion circuit includes operating a low side switch using a low side driver, wherein the low side switch and the low side driver are disposed on a first GaN device. The method may further include operating a high side switch using a high side driver, wherein the high side switch and the high side driver are disposed on a second GaN device. In further embodiments the method may include controlling the low side driver and the high side driver with a control circuit that transmits on and off signals to the low side and the high side drivers. In some embodiments the method may comprise transmitting control signals from a low side control circuit through a level shifter to the high side switch driver. In further embodiments the control signals may be received by a level shift receiver that modulates the control signals and transmits them to the high side switch driver.

In some embodiments a level shift circuit comprising a first GaN-based inverter circuit is disclosed. The inverter circuit may include a first input terminal, a first output terminal and a first inversion circuit coupled between the first input and the first output terminals. The inverter circuit may be configured to receive a first input logic signal at the first input terminal and in response, provide a first inverted output logic signal at the first output terminal. In other embodiments the first input and the first inverted output logic signals can be referenced to different voltage potentials.

In some embodiments the first inversion circuit is configured to be capable of operating with the first inverted output logic signal referenced to a voltage that is more than 20 volts higher than a reference voltage for the first input logic signal. In other embodiments the first inversion circuit comprises a first GaN-based enhancement-mode transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground. In further embodiments the first inversion circuit further comprises a current sink device coupled between the source and the ground.

In some embodiments, the first inversion circuit further comprises a pull up device coupled between the drain and a floating power supply. In other embodiments the first input logic signal controls on and off transitions of a high side gate. In one embodiment there is at least one logic gate configured to prevent simultaneous conduction of high and low side transistors. In other embodiments the first inverted output logic signal at the first output terminal is transmitted to a receiver circuit comprising a driver circuit configured to deliver a voltage above a floating power supply.

In some embodiments the level shift circuit includes an active pull-up device configured to shorten a time required to reset the first inverted output logic signal to a positive state when the first input logic signal changes from a high state to a low state. In some embodiments there may be a first capacitance between the first output terminal and a floating voltage and a second capacitance between the first output terminal and ground, wherein the first capacitance is greater than the second capacitance. In other embodiments an overvoltage condition on the first output terminal is prevented by a clamp. In one embodiment a floating supply voltage signal is measured, and in response, a supply voltage logic signal is generated and combined with the first inverted output logic signal. In other embodiments the supply voltage logic signal is coupled with a hysteretic inverter.

In some embodiments the level shift circuit further comprises a second GaN-based inverter circuit having a second input terminal and a second output terminal. A second inversion circuit may be coupled between the second input and the second output terminals and configured to receive a second input logic signal at the second input terminal and in response, provide a second inverted output logic signal at the second output terminal. In further embodiments the second inversion circuit comprises a second GaN-based enhancement-mode transistor having a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to ground. In yet further embodiments the first input logic signal is received from a level shift driver and the second input logic signal is received from a pulse generator. In one embodiment the second inverted output logic signal is transmitted to a circuit configured to prevent a change in the first inverted output logic signal.

In some embodiments an electronic power conversion component comprising a package base and one or more GaN-based dies secured to the package base is disclosed. The one or more GaN-based dies may include a first GaN-based inverter circuit comprising a first input terminal and a first output terminal. A first inversion circuit may be coupled between the first input and the first output terminals and configured to receive a first input logic signal at the first input terminal and in response, provide a first inverted output logic signal at the first output terminal. In further embodiments the first input and the first inverted output logic signals can be referenced to different voltage potentials.

In some embodiments a method of operating GaN-based level shift circuit is disclosed. The method may include transmitting a first input logic signal to a first input terminal and in response, a first inversion circuit providing an inverted first output logic signal on a first output terminal to control a gate of a power transistor. In one embodiment the first input logic signal and the inverted first output logic signals are referenced to different voltages.

In some embodiments a level shift circuit comprising a first inverter circuit and a second inverter circuit is disclosed. The first inverter circuit may comprise a first input terminal, a first output terminal and a first GaN-based enhancement-mode transistor. The first GaN-based enhancement-mode transistor has a gate coupled to the first input terminal, a drain coupled to the first output terminal and a source coupled to a ground. The second inverter circuit may have a second input terminal, a second output terminal and a second GaN-based enhancement-mode transistor. The second GaN-based enhancement-mode transistor has a gate coupled to the second input terminal, a drain coupled to the second output terminal and a source coupled to the ground.

In some embodiments the first and the second input terminals are referenced to a first voltage that is a ground, and the first and the second output terminals are referenced to a second voltage at a different potential than ground. In one embodiment the first inversion circuit further comprises a pull up device coupled between the drain and a floating power supply. In other embodiments a first capacitance is coupled between the first output terminal and a floating voltage and a second capacitance is coupled between the first output terminal and ground, wherein the first capacitance is greater than the second capacitance.

In some embodiments an overvoltage condition on the first output terminal is prevented by a clamp. In further embodiments the first inverter circuit input terminal is configured to receive a first pulsed input signal from a first pulse generator and the second inverter circuit input terminal is configured to receive a second pulsed input signal from a second pulse generator. In one embodiment at least one of the first pulse generator and the second pulse generators are configured to receive input pulses in a range of 2 nanoseconds to 20 microseconds and to transmit pulses of substantially constant duration within the range. In further embodiments at least one of the first pulse generator and the second pulse generators comprise at least one combinatorial logic function.

In some embodiments the input signals from the first and the second pulse generators correspond to on and off transitions of a pulse-width modulated (PWM) signal controlling a gate of a high side transistor. In further embodiments the level shift circuit further comprises a latching storage logic circuit configured to change state in response to a first pulsed input signal from the first pulse generator and to change state in response to a second pulsed input signal from the second pulse generator. In one embodiment the first and the second pulsed input signals from the first and the second pulse generators, respectively, correspond to on and off transitions of a PWM signal to control the gate of a high side transistor. In yet further embodiments at least one of the first and the second pulse generators are coupled with one or more logic gates. In other embodiments the level shift circuit is further configured to generate a logical combination of at least one PWM signal and at least one pulse generator output signal wherein the logical combination is used to prevent simultaneous conduction of a high side and a low side switch.

In some embodiments an on level shift pulse can be shortened by an off input pulse to enable an on time of less than 50 nanoseconds on a high side switch. In one embodiment an off level shift pulse can be shortened by an on input pulse to enable an off time of less than 50 nanoseconds on a high side switch. In other embodiments the first output terminal is coupled to a circuit configured to charge a state storage capacitor referenced to the second voltage. In further embodiments the second output terminal is coupled to a circuit configured to discharge a state storage capacitor that is referenced to the second voltage. In yet further embodiments an output signal from one of the first or the second output terminals prevents a dv/dt induced change in a signal from the other output terminal.

In some embodiments an electronic power conversion component includes a package base and one or more GaN-based dies secured to the package base. The one or more GaN-based dies include a first inverter circuit comprising a first input terminal and a first output terminal. A first GaN-based enhancement-mode transistor has a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground. The one or more GaN-based dies include a second inverter circuit comprising a second input terminal and a second output terminal. A second GaN-based enhancement-mode transistor has a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the ground.

In some embodiments a method of operating GaN-based level shift circuit is disclosed. The method includes generating a first pulse with a first pulse generator, the first pulse operating a first inverter circuit configured to change a state of a state storage device. The method further includes generating a second pulse with a second pulse generator, the second pulse operating a second inverter circuit configured to change a state of the state storage device.

In some embodiments a charging circuit comprising a GaN-based semiconductor circuit configured to allow unidirectional current flow from a ground referenced power supply to a floating power supply terminal is disclosed. In one embodiment the semiconductor circuit is configured to be capable of operating with the floating power supply terminal at a voltage that is 20 volts or greater than a voltage of the ground referenced power supply. In further embodiments the semiconductor circuit comprises at least one of: a schottky diode, an enhancement-mode transistor or a depletion-mode transistor. In yet further embodiments the semiconductor circuit comprises an enhancement-mode transistor that includes a gate and a source connected to a common voltage potential.

In some embodiments the drain of the enhancement-mode transistor is connected to the floating power supply terminal. In one embodiment the semiconductor circuit comprises an enhancement transistor that includes a gate that is controlled by a gate drive circuit. In other embodiments the drain of the enhancement-mode transistor is connected to the floating power supply terminal. In further embodiments the enhancement-mode transistor includes a drain that is connected to a source of a depletion-mode transistor and a drain of the depletion-mode transistor is connected to the floating power supply terminal. In yet further embodiments a gate of the depletion-mode transistor is connected to the ground referenced power supply.

In some embodiments a gate of the depletion-mode transistor is connected to ground. In one embodiment the semiconductor circuit is used in conjunction with a half bridge circuit comprising a low side GaN-based transistor having a low side transistor control gate configured to receive a low side gate signal from a ground referenced gate drive circuit, and a high side GaN-based transistor having a high side transistor control gate configured to receive a high side gate signal from a gate drive circuit that is referenced to a second floating power supply terminal. In further embodiments the second floating power supply terminal is a switch node of the half bridge circuit. In yet further embodiments a capacitor is connected between the floating power supply terminal and the second floating power supply terminal.

In some embodiments the semiconductor circuit comprises an enhancement-mode transistor including a gate that is controlled by a gate drive circuit and the gate drive circuit is configured such that it provides an output voltage that is in phase with the low side gate signal. In further embodiments a delay circuit is configured to turn on the enhancement-mode transistor after the low side GaN-based transistor turns on. In yet further embodiments a delay circuit is configured to turn off the enhancement-mode transistor before the low side GaN-based transistor turns off.

In some embodiments an electronic power conversion component includes a package base and one or more GaN-based dies secured to the package base including a charging circuit. In further embodiments the charging circuit comprises a GaN-based semiconductor circuit configured to allow unidirectional current flow from a ground referenced power supply to a floating power supply terminal. In some embodiments the semiconductor circuit comprises at least one of a: a schottky diode, an enhancement-mode transistor and a depletion-mode transistor. In further embodiments the semiconductor circuit includes an enhancement-mode transistor having a drain that is connected to a source of a depletion-mode transistor, where a drain of the depletion-mode transistor is connected to the floating power supply terminal.

In some embodiments a method of operating GaN-based charging circuit is disclosed. The method includes supplying power with a ground referenced power supply to a first terminal of a GaN-based semiconductor circuit. Current is allowed to flow through the GaN-based semiconductor circuit only in a direction from the first terminal to a second terminal, and the second terminal is a floating power supply.

In some embodiments a power supply circuit comprising a GaN-based depletion-mode transistor used as one of a voltage-limited voltage source or a voltage-limited current source is disclosed. In one embodiment the depletion-mode transistor is used in a reference circuit to set a reference voltage and includes a first drain coupled to a power source and a first source coupled to a first node. In another embodiment a first gate of the depletion-mode transistor is connected to ground. In another embodiment a first gate of the depletion-mode transistor is formed by a metal layer disposed over a passivation layer. In further embodiments the depletion-mode transistor is disposed on a GaN-based power integrated circuit device.

In some embodiments the power supply circuit further comprises a plurality of series connected circuit elements coupled between the first node and a second node, and one or more intermediate nodes disposed between each of the plurality of series connected circuit elements. In one embodiment the power supply circuit further comprises a GaN-based reference voltage transistor having a second gate connected to one of the one or more intermediate nodes, and a second source configured to deliver power to a circuit and a second drain connected to a power source. In further embodiments the GaN-based reference voltage transistor includes one or more diodes or diode-connected transistors disposed between the second gate and the second source, configured as gate overvoltage protection devices.

In some embodiments the power supply circuit may further comprise a disable circuit configured to prevent the second source from delivering power to a circuit. In one embodiment the reference voltage transistor is a GaN-based enhancement-mode transistor. In another embodiment the power supply circuit is configured to be a ground referenced power supply in a half bridge circuit. In further embodiments the second node is connected to ground. In another embodiment a capacitor is connected between the first node and the second node. In yet further embodiments at least one of the first node and the second node are connected to a capacitor. In other embodiments a diode or a diode-connected transistor is coupled between the first node and a circuit configured to deliver power.

In some embodiments the power source comprises a floating voltage. In another embodiment the reference circuit is configured to supply power only when the power source is within a predetermined range. In further embodiments the power source has a constantly varying voltage. In yet further embodiments the power source is an AC line voltage. In other embodiments the power supply circuit further comprises a third enhancement-mode transistor having a third gate, a third source and a third drain, and a fourth enhancement-mode transistor having a fourth gate, a fourth source and a fourth drain. The third and the fourth sources are coupled to a third node, the third gate and fourth gates are coupled together, the third drain is coupled to the second node and the fourth drain is coupled to a reference current sink terminal. In some embodiments the power supply circuit further comprises a comparator circuit coupled to a ground referenced power supply and the reference current sink terminal.

In some embodiments an electronic power conversion component comprising a package base having one or more GaN-based dies secured to the package base and including a power supply circuit is disclosed. In one embodiment a GaN-based depletion-mode transistor is used as one of a voltage-limited voltage source or a voltage-limited current source.

In some embodiments a method of operating GaN-based power supply circuit is disclosed. The method includes supplying power to a drain terminal of a GaN-based depletion-mode device having a first gate connected to ground and a first source connected to one or more series connected circuit elements including one or more intermediate nodes between each of the plurality of series connected circuit elements. The method further includes delivering power to one or more circuits from a second source of a GaN-based enhancement-mode device having a second gate coupled to one of the one or more intermediate nodes and a second drain connected to a power source.

In some embodiments a semiconductor device comprising a level shift transistor having a ratio of output saturation current (Idsat) to output capacitor charge (Qoss) of greater than 1 A/nc is disclosed. In one embodiment the level shift transistor is GaN-based. In another embodiment the level shift transistor has less than 25 pC of output charge (Qoss). In further embodiments the level shift transistor is operated with a pulsed input signal. In yet further embodiments a duration of the pulsed input signal is less than 100 ns. In some embodiments a channel width of the level shift transistor is less than 100 microns. In yet further embodiments a drain structure of the level shift transistor is placed less than 100 microns from a bond pad.

In some embodiments the level shift transistor includes a source ohmic contact area connected to a source terminal, and the source terminal is connected to a metal pad that is immediately adjacent to the source terminal and is more than 100 times the source ohmic contact area. In other embodiments the level shift transistor includes a drain ohmic contact area connected to a drain terminal and the drain terminal is connected to a metal pad that is immediately adjacent to the drain terminal and is more than 100 times the drain ohmic contact area. In further embodiments the level shift transistor comprises a source area and a drain area and the source area does not encircle the drain area. In yet further embodiments the level shift transistor comprises an active region having a source area at a first end and a drain area at an opposing end.

In some embodiments a level shift circuit comprising an input referenced to ground and an output referenced to a floating voltage is disclosed. The circuit is configured to be integrated on at least one GaN device. In some embodiments the level shift circuit includes a transistor having an Idsat to Qoss ratio greater than 1 A/nc. In other embodiments the level shift circuit includes a first capacitance between the output and the floating voltage, where the first capacitance is configured to prevent a change of output state when the floating voltage changes voltage potential from ground to a maximum allowed voltage. In other embodiments the level shift circuit comprises an electrically conductive circuit element coupled between a source of a level shift transistor and ground.

In some embodiments the level shift circuit comprises an electrically conductive circuit element coupled between a drain of a level shift transistor drain and a positive side of a power source that is referenced to the floating voltage. In further embodiments the level shift circuit includes a first circuit portion disposed on a first GaN device and a second circuit portion disposed on a second GaN device. In some embodiments the first circuit portion comprises the output and the second circuit portion comprises a receiver circuit, and a bond wire forms an electrical connection between the output and the receiver circuit.

In some embodiments the level shift circuit comprises at least one output terminal bond pad having a conductive shield underneath it that is referenced to the floating voltage. In other embodiments at least one level shift transistor and all ground referenced circuit elements are disposed on the first GaN device. In one embodiment the level shift circuit comprises a low side power switch disposed on the first GaN device. In further embodiments the second circuit portion comprises an electrically conductive circuit element coupled between a drain of a level shift transistor drain and a positive side of a power source that is referenced to the floating voltage. In yet further embodiments the level shift circuit comprises a high side power switch integrated on the same device.

In some embodiments a circuit including overvoltage protection is disclosed. The circuit comprises a first pin and a second pin, and an overvoltage protection circuit comprising a first enhancement-mode transistor disposed on a GaN-based substrate and coupled between the first pin and the second pin. In some embodiments the overvoltage protection circuit does not contain depletion-mode transistors. In further embodiments the overvoltage protection circuit comprises a second enhancement-mode transistor having a source coupled to a gate of a third enhancement-mode transistor, and an electrically conductive element coupled in an electrical path between the source and the second pin. The electrically conductive element includes one of a resistor, a depletion-mode transistor, a reference current sink or a reference current source.

In some embodiments the overvoltage protection circuit comprises a second enhancement-mode transistor having a source coupled to a gate of a third enhancement-mode transistor. An electrically conductive element is coupled in an electrical path between the source and the gate. The electrically conductive element comprises one of a resistor, a depletion-mode transistor, a reference current sink or a reference current source. In further embodiments the first pin is the gate of a power transistor and the second pin is the source of the power transistor. In one embodiment the overvoltage protection circuit is coupled between a power supply terminal and ground.

In some embodiments the overvoltage protection circuit is configured to remain in an off state until a voltage potential across the first and the second pins is above a predetermined voltage level. In further embodiments the first enhancement-mode transistor has a first source coupled to the first pin and a first drain coupled to the second pin. The first enhancement-mode transistor is configured to provide overvoltage protection between the first and the second pins. In one embodiment a first gate of the first enhancement-mode transistor is coupled to the first source and the first enhancement-mode transistor is configured to remain in an off state until it is subjected to an overvoltage pulse. In some embodiments one or more diodes or diode-connected transistors are connected in series and coupled to a gate of the first enhancement-mode transistor, configured to drive the first enhancement-mode transistor.

In some embodiments the first enhancement-mode transistor is configured to conduct a current greater than 500 mA when exposed to an overvoltage pulse. In one embodiment the overvoltage protection circuit comprises second and third enhancement-mode transistors. A third source of the third enhancement-mode transistor is connected to a second gate of the second enhancement-mode transistor, and a second source of the second enhancement-mode transistor is connected to a first gate of the first enhancement-mode transistor. In further embodiments a disable circuit is configured to prevent current flow between the first and the second pins for a predetermined dv/dt value occurring at the first or the second pin that is less than 1 V/ns. In yet further embodiments the disable circuit comprises a dv/dt detection filter coupled to the first gate of the first enhancement-mode transistor.

In some embodiments the dv/dt detection filter comprises at least one GaN-based logic circuit. In one embodiment the first enhancement-mode transistor is connected in series with a source of a depletion-mode transistor. A drain of the depletion-mode transistor is connected to the first pin, and the first source is connected to the second pin. In other embodiments the overvoltage protection circuit comprises a second enhancement-mode transistor connected in parallel with the first enhancement-mode transistor. The overvoltage protection circuit is configured to provide symmetric overvoltage protection for the circuit when exposed to either positive or negative overvoltage conditions. In further embodiments the overvoltage protection circuit comprises a second enhancement-mode transistor connected in series with the first enhancement-mode transistor, and the overvoltage protection circuit is configured to provide symmetric overvoltage protection for the circuit when exposed to either positive or negative overvoltage conditions.

In some embodiments an ESD protection circuit comprising a GaN-based circuit having two pins is disclosed. A first enhancement-mode transistor is coupled between the two pins and has a first gate. A dv/dt detection filter is coupled to the gate and is configured to enable current flow between the two pins when a dv/dt on at least one of the two pins is a value greater than 1 V/ns. In some embodiments the ESD protection circuit further comprises an overvoltage protection circuit that includes an enhancement-mode-transistor coupled between the two pins and configured to temporarily conduct current between the two pins while a voltage potential between the two pins is above a predetermined level.

In some embodiments an electronic power conversion component comprising a package base and one or more GaN-based dies secured to the package base is disclosed. The one or more GaN-based dies include a first circuit comprising at least one enhancement-mode transistor, and an overvoltage protection circuit coupled to the first circuit.

In some embodiments a method of operating a GaN-based circuit is disclosed. The method includes receiving a voltage potential above a predetermined value across two pins of a circuit and turning on a GaN-based enhancement-mode transistor coupled between the two pins. The enhancement-mode transistor temporarily conducts current between the two pins while the voltage potential is above the predetermined value. In some embodiments the method further comprises receiving a dv/dt signal larger than 1 V/ns on at least one of the two pins, and in response turning on a second GaN-based enhancement-mode transistor enabling current to flow between the two pins.

In some embodiments an electronic circuit including a substrate comprising GaN is disclosed. A power switch is formed on the substrate and includes a first control gate and a first source. A drive circuit is formed on the substrate and includes an output coupled to the first gate. A power supply has a maximum voltage and is coupled to the drive circuit, where the output can be driven to the maximum voltage. In further embodiments the drive circuit is coupled to at least one power supply and to one input that are both referenced to the first source. In some embodiments the drive circuit is coupled to exactly one PWM input. In other embodiments the drive circuit includes at least one enhancement-mode transistor, at least one current conducting element and does not include any depletion-mode transistors.

In some embodiments the drive circuit comprises an inverter that includes a first enhancement-mode transistor having a second gate connected to a first input signal, a second source connected to the first source, and a second drain. A second enhancement-mode transistor has a third drain connected to the power supply, a third source connected to the second drain and a third gate connected to a circuit configured to generate a voltage higher than the power supply. In one embodiment a capacitive element moves up and down in voltage synchronously with the third source and supplies power to the third gate. In some embodiments a rectifying element is configured to supply power to the capacitive element and prevent discharge of the capacitive element when a terminal of the capacitive element rises above a voltage on the power supply.

In some embodiments the second enhancement-mode transistor can be switched on in less than 100 nanoseconds. In one embodiment a third enhancement-mode transistor has a fourth gate connected the first input signal, a fourth drain connected to the third gate and a fourth source connected to the first source. In other embodiments a current limiting element is disposed in a current conduction path from the power supply to the first source. The current conduction path comprises a series connection of a rectifying element, the current limiting element and the third enhancement-mode transistor. In further embodiments a resistor is disposed between the first input signal and the control gate. In yet further embodiments the drive circuit comprises two inverters connected serially to form a non-inverting buffer circuit. In one embodiment the drive circuit comprises at least one buffer circuit. In other embodiments the drive circuit is coupled with a gate of a fourth enhancement-mode transistor having a fifth drain connected to the control gate and a fifth source connected to the first source. Further embodiments include an electrostatic discharge protection circuit.

In some embodiments an electronic component comprising a package base having at least one GaN-based die secured to the package base and including an electronic circuit is disclosed. A power switch is formed on the at least one GaN based die and includes a first control gate and a first source. A drive circuit is formed on the at least one GaN based die and includes an output coupled to the control gate. A power supply having a maximum voltage is coupled to the drive circuit, where the output can be driven to the maximum voltage. In one embodiment the drive circuit is coupled to at least one power supply and to one input that are referenced to the first source. In another embodiment the drive circuit is coupled to exactly one PWM input.

In some embodiments the drive circuit further includes at least one enhancement-mode transistor, at least one current conducting element, and does not include any depletion-mode transistors.

In some embodiments a method of operating GaN-based circuit is disclosed. The method includes receiving a signal with a drive circuit and processing the signal with the drive circuit. A signal is transmitted to a control gate of a switch and the drive circuit and the switch are disposed on a unitary GaN substrate. The drive circuit includes at least one enhancement-mode transistor, at least one current conducting element and does not include any depletion-mode transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention;

FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in FIG. 1;

FIG. 3 is a schematic of the first level shift transistor illustrated in FIG. 1;

FIG. 4 is a schematic of the level shift driver circuit illustrated in FIG. 1;

FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in FIG. 1;

FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in FIG. 5;

FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in FIG. 1;

FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in FIG. 1

FIG. 9 is a schematic of the startup circuit illustrated in FIG. 1;

FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of FIG. 9;

FIG. 11 is a schematic of the UVLO circuit illustrated in FIG. 1;

FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in FIG. 1;

FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in FIG. 12;

FIG. 14 is a schematic of the high side logic and control circuit illustrated in FIG. 1;

FIG. 15 is a schematic of the first level shift receiver circuit illustrated in FIG. 14;

FIG. 16 is a schematic of the second level shift receiver circuit illustrated in FIG. 14;

FIG. 17 is a schematic of the pull up trigger circuit illustrated in FIG. 14;

FIG. 18 is a schematic of the high side UVLO circuit illustrated in FIG. 14;

FIG. 19 is a schematic of the high side transistor driver circuit illustrated in FIG. 14;

FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in FIG. 14;

FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention;

FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in FIG. 21;

FIG. 23 is a schematic of the first level shift transistor illustrated in FIG. 22;

FIG. 24 is a schematic of the inverter/buffer circuit illustrated in FIG. 22;

FIG. 25 is a schematic of the on pulse generator circuit illustrated in FIG. 22;

FIG. 26 is a schematic of the off pulse generator circuit illustrated in FIG. 22;

FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in FIG. 22;

FIG. 28 is a schematic of the low side transistor drive circuit illustrated in FIG. 22;

FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in FIG. 21;

FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in FIG. 29;

FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in FIG. 29;

FIG. 32 is a schematic of the high side UVLO circuit illustrated in FIG. 29;

FIG. 33 is a schematic of the high side transistor driver circuit illustrated in FIG. 29;

FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention;

FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention;

FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; and

FIG. 37 is an illustration of the electronic package of FIG. 36.

DETAILED DESCRIPTION

Certain embodiments of the present invention relate to half bridge power conversion circuits that employ one or more gallium nitride (GaN) devices. While the present invention can be useful for a wide variety of half bridge circuits, some embodiments of the invention are particularly useful for half bridge circuits designed to operate at high frequencies and/or high efficiencies with integrated driver circuits, integrated level shift circuits, integrated bootstrap capacitor charging circuits, integrated startup circuits and/or hybrid solutions using GaN and silicon devices, as described in more detail below.

Half Bridge Circuit #1

Now referring to FIG. 1, in some embodiments circuit 100 may include a pair of complementary power transistors (also referred to herein as switches) that are controlled by one or more control circuits configured to regulate power delivered to a load. In some embodiments a high side power transistor is disposed on a high side device along with a portion of the control circuit and a low side power transistor is disposed on a low side device along with a portion of the control circuit, as described in more detail below.

The integrated half bridge power conversion circuit 100 illustrated in FIG. 1 includes a low side GaN device 103, a high side GaN device 105 a load 107, a bootstrap capacitor 110 and other circuit elements, as illustrated and discussed in more detail below. Some embodiments may also have an external controller (not shown in FIG. 1) providing one or more inputs to circuit 100 to regulate the operation of the circuit. Circuit 100 is for illustrative purposes only and other variants and configurations are within the scope of this disclosure.

In one embodiment, low side GaN device 103 may have a GaN-based low side circuit 104 that includes a low side power transistor 115 having a low side control gate 117. Low side circuit 104 may further include an integrated low side transistor driver 120 having an output 123 connected to low side transistor control gate 117. In another embodiment high, side GaN device 105 may have a GaN-based high side circuit 106 that includes a high side power transistor 125 having a high side control gate 127. High side circuit 106 may further include an integrated high side transistor driver 130 having an output 133 connected to high side transistor control gate 127.

A voltage source 135 (also known as a rail voltage) may be connected to a drain 137 of high side transistor 125, and the high side transistor may be used to control power input into power conversion circuit 100. High side transistor 125 may further have a source 140 that is coupled to a drain 143 of low side transistor 115, forming a switch node 145. Low side transistor 115 may have a source 147 connected to ground. In one embodiment, low side transistor 115 and high side transistor 125 may be GaN-based enhancement-mode field effect transistors. In other embodiments low side transistor 115 and high side transistor 125 may be any other type of device including, but not limited to, GaN-based depletion-mode transistors, GaN-based depletion-mode transistors connected in series with silicon based enhancement-mode field-effect transistors having the gate of the depletion-mode transistor connected to the source of the silicon-based enhancement-mode transistor, silicon carbide based transistors or silicon-based transistors.

In some embodiments high side device 105 and low side device 103 may be made from a GaN-based material. In one embodiment the GaN-based material may include a layer of GaN on a layer of silicon. In further embodiments the GaN based material may include, but not limited to, a layer of GaN on a layer of silicon carbide, sapphire or aluminum nitride. In one embodiment the GaN based layer may include, but not limited to, a composite stack of other III nitrides such as aluminum nitride and indium nitride and III nitride alloys such as AlGaN and InGaN. In further embodiments, GaN-based low side circuit 104 and GaN-based high side circuit 106 may be disposed on a monolithic GaN-based device. In other embodiments GaN-based low side circuit 104 may be disposed on a first GaN-based device and GaN-based high side circuit 106 may be disposed on a second GaN-based device. In yet further embodiments GaN-based low side circuit 104 and GaN-based high side circuit 106 may be disposed on more than two GaN-based devices. In one embodiment, GaN-based low side circuit 104 and GaN-based high side circuit 106 may contain any number of active or passive circuit elements arranged in any configuration.

Low Side Device

Low side device 103 may include numerous circuits used for the control and operation of the low side device and high side device 105. In some embodiments, low side device 103 may include logic, control and level shift circuits (low side control circuit) 150 that controls the switching of low side transistor 115 and high side transistor 125 along with other functions, as discussed in more detail below. Low side device 103 may also include a startup circuit 155, a bootstrap capacitor charging circuit 157 and a shield capacitor 160, as also discussed in more detail below.

Now referring to FIG. 2, the circuits within low side control circuit 150 are functionally illustrated. Each circuit within low side control circuit 150 is discussed below, and in some cases is shown in more detail in FIGS. 3-14. In one embodiment the primary function of low side control circuit 150 may be to receive one or more input signals, such as a PWM signal from a controller, and control the operation of low side transistor 115, and high side transistor 125.

In one embodiment, first and a second level shift transistors 203, 205, respectively, may be employed to communicate with high side logic and control circuit 153 (see FIG. 1). In some embodiments, first level shift transistor 203 may be a high voltage enhancement-mode GaN transistor. In further embodiments, first level shift transistor 203 may be similar to low side transistor 115 (see FIG. 1) and high side transistor 125, except it may be much smaller in size (e.g., first level shift transistor may be tens of microns in gate width with minimum channel length).

In other embodiments first level shift transistor 203 may experience high voltage and high current at the same time (i.e. the device may operate at the high power portion of the device Safe Operating Area) for as long as high side transistor 125 (see FIG. 1) is on. Such conditions may cause relatively high power dissipation, thus some embodiments may involve design and device reliability considerations in the design of first level shift transistor 203, as discussed in more detail below. In further embodiments, a first level shift resistor 207 may be added in series with a source 210 of first level shift transistor 203 to limit gate 213 to source 210 voltage and consequently the maximum current through the first level shift transistor. Other methods may be employed to limit the current through first level shift transistor 203, and are within the scope of this disclosure. Drain 215 of first level shift transistor 203 may be coupled to high side logic and control circuit 153 (see FIG. 1), as discussed in more detail below.

In one embodiment, first level shift transistor 203 may comprise a portion of an inverter circuit having a first input and a first output and configured to receive a first input logic signal at the first input terminal and in response, provide a first inverted output logic signal at the first output terminal, as discussed in more detail below. In further embodiments the first input and the first inverted output logic signals can be referenced to different voltage potentials. In some embodiments, first level shift resistor 207 may be capable of operating with the first inverted output logic signal referenced to a voltage that is more than 13 volts higher than a reference voltage for the first input logic signal. In other embodiments it may be capable of operating with the first inverted output logic signal referenced to a voltage that is more than 20 volts higher than a reference voltage for the first input logic signal, while in other embodiments it may be between 80-400 volts higher.

In other embodiments, first level shift resistor 207 may be replaced by any form of a current sink. For example, in one embodiment, source 210 of first level shift transistor 203 may be connected to a gate to source shorted depletion-mode device. In a further embodiment, the depletion-mode device may be fabricated by replacing the enhancement-mode gate stack with a high voltage field plate metal superimposed on top of the field dielectric layers. The thickness of the field dielectric and the work function of the metal may be used to determine the pinch-off voltage of the stack.

In other embodiments first level shift resistor 207 may be replaced by a current sink. The current sink may use a reference current (Iref) that may be generated by startup circuit 155 (illustrated in FIG. 1 and discussed in more detail below). Both the depletion-mode transistor and current sink embodiments may result in a significant device area reduction compared to the resistor embodiment (i.e., because a relatively small depletion-mode transistor would suffice and Iref is already available from startup circuit 155).

Second level shift transistor 205 may be designed similar to first level shift transistor 203 (e.g., in terms of voltage capability, current handling capability, thermal resistance, etc.). Second level shift transistor 205 may also be built with either an active current sink or a resistor, similar to first level shift transistor 203. In one embodiment the primary difference with second level shift transistor 205 may be in its operation. In some embodiments the primary purpose of second level shift transistor 205 may be to prevent false triggering of high side transistor 125 (see FIG. 1) when low side transistor 115 turns off.

In one embodiment, for example, false triggering can occur in a boost operation when low side transistor 115 turn off results in the load current flowing through high side transistor 125 while the transistor is operating in the third quadrant with its gate shorted to its source (i.e., in synchronous rectification mode). This condition may introduce a dv/dt condition at switch node (Vsw) 145 since the switch node was at a voltage close to ground when low side transistor 115 was on and then transitions to rail voltage 135 over a relatively short time period. The resultant parasitic C*dv/dt current (i.e., where C=Coss of first level shift transistor 203 plus any other capacitance to ground) can cause first level shift node 305 (see FIG. 3) to get pulled low which will then turn on high side transistor 125. In some embodiments this condition may not be desirable because there may be no dead time control, and shoot through may occur from high side transistor 125 and low side transistor 115 being in a conductive state simultaneously.

FIG. 3 illustrates one embodiment showing how first level shift transistor 203 may be electrically coupled to high side device 105. First level shift transistor 203, located on low side device 103, is illustrated along with a pull up resistor 303 that may be located on high side device 105 (see FIG. 1). In some embodiments, first level shift transistor 203 may operate as a pull down transistor in a resistor pull up inverter.

In further embodiments, when level shift driver circuit 217 (see FIG. 2) supplies a high gate signal (L1_DR) to first level shift transistor 203, a first level shift node 305 gets pulled low which is inverted by high side logic and control circuit 153 (see FIG. 1). The inverted signal appears as a high state signal that turns on high side transistor 137 (see FIG. 1) which then pulls the voltage at switch node (Vsw) 145 close to rail voltage 135.

Conversely, when level shift driver circuit 217 (see FIG. 2) supplies a low gate signal to first level shift transistor 203, a first level shift node 305 gets pulled to a high logic state which is inverted by high side logic and control circuit 153 (see FIG. 1). The inverted signal appears as a low logic state signal that turns off high side transistor 125. This scheme may result in a non-inverted gate signal to high side transistor 125. In further embodiments, first level shift transistor 203 may be designed large enough to be able to pull down on first level shift node 305, but not so large that its drain to source and drain to substrate (i.e., the semiconductor substrate) capacitances induce false triggering of high side logic and control circuit 153.

In some embodiments pull up resistor 303 may instead be an enhancement-mode transistor, a depletion-mode transistor or a reference current source element. In further embodiments pull up resistor 303 may be coupled between the drain and the positive terminal of a floating supply (e.g., a bootstrap capacitor, discussed in more detail below) that is referenced to a different voltage rail than ground. In yet further embodiments there may be a first capacitance between the first output terminal (LS NODE) 305 and switch node (Vsw) 145 (see FIG. 1) and a second capacitance between the first output terminal and ground, where the first capacitance is greater than the second capacitance. The first capacitance may be designed such that in response to a high dv/dt signal at switch node (Vsw) 145 (see FIG. 1), a large portion of the C*dv/dt current is allowed to conduct through the first capacitance ensuring that the voltage at first output terminal 305 tracks the voltage at the switch node (Vsw). In some embodiments shield capacitor 160 (see FIG. 1) may be designed to act as the first capacitor as described above. In further embodiments shield capacitor 160 (see FIG. 1) may be used to create capacitance between first output terminal 305 and switch node (Vsw) 145 (see FIG. 1) in half bridge power conversion circuit 100. In yet further embodiments, shield capacitor 160 (see FIG. 1) may also be used to minimize a capacitance between first output terminal 305 and substrate (i.e., the semiconductor substrate). More specifically, in some embodiments shield capacitor 160 may be created by adding a conductive shield layer to the device and coupling the layer to switch node (Vsw) 145. This structure may effectively create two capacitors. One capacitor is coupled between output terminal 305 and switch node (Vsw) 145, and the other is coupled between the switch node and the substrate. The capacitance between output terminal 305 and the substrate is thereby practically eliminated. In further embodiments shield capacitor 160 (see FIG. 1) may be constructed on the low side chip 103.

Logic, control and level shifting circuit 150 (see FIG. 2) may have other functions and circuits such as, but not limited to, a level shift driver circuit 217, a low side transistor drive circuit 120, a blanking pulse generator 223, a bootstrap transistor drive circuit 225 and an under voltage lock out (UVLO) circuit 227, as explained in separate figures with more detail below.

Now referring to FIG. 4, level shift driver circuit 217 is shown in greater detail. In one embodiment level shift driver circuit 217 may include a first inverter 405 and a second inverter 410 in a sequential chain. In further embodiments, since level shift driver circuit 217 may be driving a small gate width first level shift transistor 203, there may be no need for a buffer stage.

In one embodiment, level shift driver circuit 217 is driven directly by the pulse-width modulated high side signal (PWM_HS) from the controller (not shown). In some embodiments the (PWM_HS) signal may be supplied by an external control circuit. In one embodiment the external control circuit may be an external controller that is in the same package with high side device 105, low side device 103, both devices, or packaged on its own. In further embodiments, level shift driver circuit 217 may also include logic that controls when the level shift driver circuit communicates with first level shift transistor 203 (see FIG. 3). In one embodiment an optional low side under voltage lock out signal (LS_UVLO) may be generated by an under voltage lock out circuit within level shift driver circuit 217. The low side under voltage lock out circuit can be used to turn off level shift driver circuit 217 if either (Vcc) or (Vdd) for the low side (Vdd_LS) go below a certain reference voltage, or a fraction of the reference voltage.

In further embodiments level shift driver circuit 217 may generate a shoot through protection signal for the low side transistor (STP_LS) that is used to prevent shoot through arising from overlapping gate signals on low side transistor 115 and high side transistor 125. The function of the (STP_LS) signal may be to ensure that low side driver circuit 120 (see FIG. 2) only communicates with the gate terminal of the low side transistor 115 when the gate signal to high side transistor 125 is low. In other embodiments, the output of first inverter 405 may be used to generate the shoot through protection signal (STP_LS) for the low side transistor 115.

In further embodiments, logic for UVLO and shoot-through protection may implemented by adding a multiple input NAND gate to first inverter 405, where the inputs to the NAND gate are the (PWM_HS), (LS_UVLO) and (STP_HS) signals. In yet further embodiments, first inverter 405 may only respond to the (PWM_HS) signal if both (STP_HS) and (LS_UVLO) signals are high. In further embodiments, the STP_HS signal may be generated from the low side gate driver block 120, as explained in separate figures with more detail.

Now referring to FIG. 5, blanking pulse generator 223 may be used to generate a pulse signal that corresponds to the turn off transient of low side transistor 115. This pulse signal may then turn on second level shift transistor 205 for the duration of the pulse, which triggers a control circuit on high side device 105 (see FIG. 1) to prevent false pull down of first level shift node 305 voltage.

FIG. 5 illustrates a schematic of one embodiment of blanking pulse generator 223. In some embodiments a low side transistor 115 gate signal (LS_GATE) is fed as an input to blanking pulse generator 223. The (LS_GATE) signal is inverted by a first stage inverter 505, then sent through an RC pulse generator 510 to generate a positive pulse. In some embodiments an inverted signal may be needed because the pulse corresponds to the falling edge of the (LS_GATE) signal. A capacitor 515 in RC pulse generator 510 circuit may be used as a high pass filter allowing the dv/dt at its input to appear across resistor 520. Once the dv/dt vanishes at the input to the RC pulse generator 510, capacitor 515 may charge slowly through resistor 520, resulting in a slow decaying voltage waveform across the resistor. The pulse may then be sent through a second inverter 525, a third inverter 530 and a buffer 535 to generate a square wave pulse for the blanking pulse (B_PULSE) signal. The duration of the pulse may be determined by the value of capacitor 515 and resistor 520 in RC pulse generator 510. In some embodiments, capacitor 515 may be constructed using a drain to source shorted enhancement-mode GaN transistor.

Now referring to FIG. 6, example waveforms 600 within blanking pulse generator 223 are illustrated for one embodiment. Trace 605 shows a falling edge of the low side gate pulse (LS_GATE). Trace 610 shows the rising edge of first stage inverter 505 output. Trace 615 shows the output of RC pulse generator 510 and trace 620 shows the resulting blanking pulse (B_PULSE) signal that is an output of blanking pulse generator 223.

Now referring to FIG. 7, bootstrap transistor drive circuit 225 is illustrated in greater detail. Bootstrap transistor drive circuit 225 includes inverter 730, first buffer 735 and second buffer 745. Bootstrap transistor drive circuit 225 may receive the (BOOTFET_DR_IN) signal from low side driver circuit 120. The (BOOTFET_DR_IN) signal may be inverted with respect to the LS_GATE signal. Bootstrap transistor drive circuit 225 may be configured to provide a gate drive signal called (BOOTFET_DR) to a bootstrap transistor in bootstrap charging circuit 157 (see FIG. 1), discussed in more detail below. The (BOOTFET_DR) gate drive signal may be timed to turn on the bootstrap transistor when low side transistor 115 is turned on. Also, since bootstrap transistor drive circuit 225 is driven by (Vcc), the output of this circuit may have a voltage that goes from 0 volts in a low state to (Vcc)+6 volts in a high state. In one embodiment the bootstrap transistor is turned on after low side transistor 115 is turned on, and the bootstrap transistor is turned off before the low side transistor is turned off.

In some embodiments, the turn on transient of the (BOOTFET_DR) signal may be delayed by the introduction of a series delay resistor 705 to the input of second buffer 745, that may be a gate of a transistor in a final buffer stage. In further embodiments, the turn off transient of low side transistor 115 (see FIG. 1) may be delayed by the addition of a series resistor to a gate of a final pull down transistor in low side drive circuit 120. In one embodiment, one or more capacitors may be used in bootstrap transistor drive circuit 225, and support voltages of the order of (Vcc) which, for example, could be 20 volts, depending on the end user requirements and the design of the circuit. In some embodiments the one or more capacitors may be made with a field dielectric to GaN capacitor instead of a drain to source shorted enhancement-mode transistor.

Now referring to FIG. 8 a block diagram for low side transistor drive circuit 120 is illustrated. Low side transistor drive circuit 120 may have a first inverter 805, a buffer 810, a second inverter 815, a second buffer 820 and a third buffer 825. Third buffer 825 may provide the (LS_GATE) signal to low side transistor 115 (see FIG. 1). In some embodiments two inverter/buffer stages may be used because the input to the gate of low side transistor 115 (see FIG. 1) may be synchronous with (Vin). Thus, (Vin) in a high state may correspond to (Vgate) of low side transistor 115 in a high state and vice versa.

In further embodiments, certain portions of low side drive circuit 120 may have an asymmetric hysteresis. Some embodiments may include asymmetric hysteresis using a resistor divider 840 with a transistor pull down 850.

Further embodiments may have multiple input NAND gates for the (STP_LS) signal (shoot through protection on low side transistor 115). In one embodiment, low side drive circuit 120 may receive the shoot through protection signal (STP_LS) from level shift driver circuit 217. The purpose of the (STP_LS) signal may be similar to the (STP_HS) signal described previously. The (STP_LS) signal may ensure that low side transistor drive circuit 120 does not communicate with gate 117 (see FIG. 1) of low side transistor 115 when level shift driver circuit 217 output is at a high state. In other embodiments, the output of the first inverter stage 805 may be used as the (STP_HS) signal for level shift drive circuit 217 and the (BOOTFET_DR_IN) signal for bootstrap transistor drive circuit 225.

In some embodiments, low side transistor drive circuit 120 may employ multiple input NAND gates for the (LS_UVLO) signal received from UVLO circuit 227 (see FIG. 2). Further embodiments may employ a turn off delay resistor that may be in series with a gate of a final pull down transistor in final buffer stage 825. The delay resistor may be used in some embodiments to make sure the bootstrap transistor is turned off before low side transistor 115 turns off.

Now referring to FIG. 9, startup circuit 155 is illustrated in greater detail. Startup circuit 155 may be designed to have a multitude of functionalities as discussed in more detail below. Primarily, startup circuit 155 may be used to provide an internal voltage (in this case START_Vcc) and provide enough current to support the circuits that are being driven by (Vcc). This voltage may remain on to support the circuits until (Vcc) is charged up to the required voltage externally from rail voltage 135 (V+). Startup circuit 155 may also provide a reference voltage (Vref) that may be independent of the startup voltage, and a reference current sink (Iref).

In one embodiment, a depletion-mode transistor 905 may act as the primary current source in the circuit. In further embodiments depletion-mode transistor 905 may be formed by a metal layer disposed over a passivation layer. In some embodiments, depletion-mode transistor 905 may use a high voltage field plate (typically intrinsic to any high-voltage GaN technology) as the gate metal. In further embodiments a field dielectric may act as the gate insulator. The resultant gated transistor may be a depletion-mode device with a high channel pinch-off voltage (Vpinch) (i.e., pinch-off voltage is proportional to the field dielectric thickness). Depletion-mode transistor 905 may be designed to block relatively high voltages between its drain (connected to V+) and its source. Such a connection may be known as a source follower connection. Depletion-mode transistor 905 may have a gate 906 coupled to ground, a source 907 coupled to a first node 911 and a drain 909 coupled to voltage source 135.

In further embodiments a series of identical diode connected enhancement-mode low-voltage transistors 910 may be in series with depletion-mode transistor 905. Series of identical diode connected enhancement-mode low-voltage transistors 910 may be connected in series between a first node 911 and a second node 912. One or more intermediate nodes 913 may be disposed between each of series of identical diode connected enhancement-mode low-voltage transistors 910. The width to length ratio of the transistors may set the current drawn from (V+) as well as the voltage across each diode. To remove threshold voltage and process variation sensitivity, series of identical diode connected enhancement-mode low-voltage transistors 910 may be designed as large channel length devices. In some embodiments, series of identical diode connected enhancement-mode low-voltage transistors 910 may be replaced with one or more high value resistors.

In further embodiments, at the bottom end of series of identical diode connected enhancement-mode low-voltage transistors 910, a current mirror 915 may be constructed from two enhancement-mode low-voltage transistors and used to generate a reference current sink (Iref). First current mirror transistor 920 may be diode connected and second current mirror transistor 925 may have a gate connected to the gate of the first current mirror transistor. The sources of first and second current mirror transistors 920, 925, respectively may be coupled and tied to ground. A drain terminal of first current mirror transistor 920 may be coupled to second junction 912 and a source terminal of second current mirror transistor 925 may be used as a current sink terminal. This stack of current mirror 915 and series of identical diode connected enhancement-mode low-voltage transistors 910 may form what is known as a “source follower load” to depletion-mode transistor 905.

In other embodiments, when gate 906 of depletion-mode transistor 905 is tied to ground, source 907 of the depletion-mode transistor may assume a voltage close to (Vpinch) when current is supplied to the “source follower load”. At the same time the voltage drop across diode connected transistor 920 in current mirror 915 may be close to the threshold voltage of the transistor (Vth). This condition implies that the voltage drop across each of series of identical diode connected enhancement-mode low-voltage transistors 910 may be equal to (Vpinch−Vth)/n where ‘n’ is the number of diode connected enhancement-mode transistors between current mirror 915 and depletion-mode transistor 905.

For example, if the gate of a startup transistor 930 is connected to the third identical diode connected enhancement-mode low-voltage transistor from the bottom, the gate voltage of the startup transistor may be 3*(Vpinch−Vth)/n+Vth. Therefore, the startup voltage may be 3*(Vpinch−Vth)/n+Vth−Vth=3*(Vpinch-Vth)/n. As a more specific example, in one embodiment where (Vpinch)=40 volts, (Vth)=2 volts where n=6 and (Vstartup)=19 volts.

In other embodiments, startup circuit 155 may generate a reference voltage signal (Vref). In one embodiment, the circuit that generates (Vref) may be similar to the startup voltage generation circuit discussed above. A reference voltage transistor 955 may be connected between two transistors in series of identical diode connected enhancement-mode low-voltage transistors 910. In one embodiment (Vref)=(Vpinch-Vth)/n.

In further embodiments, a disable pull down transistor 935 may be connected across the gate to source of startup transistor 930. When the disable signal is high, startup transistor 930 will be disabled. A pull down resistor 940 may be connected to the gate of disable transistor 935 to prevent false turn on of the disable transistor. In other embodiments a diode clamp 945 may be connected between the gate and the source terminals of startup transistor 930 to ensure that the gate to source voltage capabilities of the startup transistor are not violated during circuit operation (i.e., configured as gate overvoltage protection devices). In some embodiments, diode clamp 945 may be made with a series of diode connected GaN-based enhancement-mode transistors 1050, as illustrated in FIG. 10.

Now referring to FIG. 11, UVLO circuit 227 is illustrated in greater detail. In some embodiments, UVLO circuit 227 may have a differential comparator 1105, a down level shifter 1110 and an inverter 1115. In further embodiments, UVLO circuit 227 may use (Vref) and (Iref) generated by startup circuit 155 (see FIG. 9) in a differential comparator/down level shifter circuit to generate the (LS_UVLO) signal that feeds into level shift driver circuit 217 (see FIG. 2) and low side transistor driver circuit 120. In some embodiments UVLO circuit 227 can also be designed to have asymmetric hysteresis. In further embodiments the output of UVLO circuit 227 may be independent of threshold voltage. This may be accomplished by choosing a differential comparator with a relatively high gain. In one embodiment the gain can be increased by increasing the value of the current source and the pull up resistors in the differential comparator. In some embodiments the limit on the current and resistor may be set by (Vref).

In other embodiments voltages (VA) and (VB), 1120 and 1125, respectively, may be proportional to (Vcc) or (Vdd_LS) and (Vref) as dictated by the resistor divider ratio on each input. When (VA) 1120>(VB) 1125 the output of the inverting terminal goes to a low state. In one specific embodiment, the low state=(Vth) since the current source creates a source follower configuration. Similarly when (VA) 1120<(VB) 1125 the output goes to a high state (Vref). In some embodiments down level shifter 1110 may be needed because the low voltage needs to be shifted down by one threshold voltage to ensure that the low input to the next stage is below (Vth). The down shifted output may be inverted by a simple resistor pull up inverter 1115. The output of inverter 1115 is the (LS_UVLO) signal.

Now referring to FIG. 12, bootstrap capacitor charging circuit 157 is illustrated in greater detail. In one embodiment, bootstrap diode and transistor circuit 157 may include a parallel connection of a high voltage diode connected enhancement-mode transistor 1205 and a high voltage bootstrap transistor 1210. In further embodiments, high voltage diode connected enhancement-mode transistor 1205 and high voltage bootstrap transistor 1210 can be designed to share the same drain finger. In some embodiments the (BOOTFET_DR) signal may be derived from bootstrap transistor drive circuit 225 (see FIG. 2). As discussed above, high voltage bootstrap transistor 1210 may be turned on coincident with the turn on of low side transistor 115 (see FIG. 1).

Now referring to FIG. 13, an alternative bootstrap diode and transistor circuit 1300 may be used in place of bootstrap diode and transistor circuit 157 discussed above in FIG. 12. In the embodiment illustrated in FIG. 13, a depletion-mode device 1305 cascoded by an enhancement-mode low voltage GaN device 1310 may be connected as illustrated in schematic 1300. In another embodiment, a gate of depletion-mode device 1305 can be connected to ground to reduce the voltage stress on cascoded enhancement-mode device 1310, depending upon the pinch-off voltage of the depletion-mode device.

High Side Device

Now referring to FIG. 14, high side logic and control circuit 153 is illustrated in greater detail. In one embodiment, high side driver 130 receives inputs from first level shift receiver 1410 and high side UVLO circuit 1415 and sends a (HS_GATE) signal to high side transistor 125 (see FIG. 1). In yet further embodiments, a pull up trigger circuit 1425 is configured to receive the (LSHIFT_1) signal and control pull up transistor 1435. In some embodiments, second level shift receiver circuit 1420 is configured to control blanking transistor 1440. Both the pull up transistor 1435 and blanking transistor 1440 may be connected in parallel with pull up resistor 1430. Each circuit within high side logic and control circuit 153 is discussed below, and in some cases is shown in more detail in FIGS. 16-20.

Now referring to FIG. 15, first level shift receiver 1410 is illustrated in greater detail. In some embodiments, first level shift receiver 1410 may convert the (L_SHIFT1) signal to an (LS_HSG) signal that can be processed by high side transistor driver 130 (see FIG. 14) to drive high side transistor 125 (see FIG. 1). In further embodiments, first level shift receiver 1410 may have three enhancement-mode transistors 1505, 1510, 1515 employed in a multiple level down shifter and a plurality of diode connected transistors 1520 acting as a diode clamp, as discussed in more detail below.

In one embodiment, first level shift receiver 1410 may down shift the (L_SHIFT1) signal by 3*Vth (e.g., each enhancement-mode transistor 1505, 1510, 1515 may have a gate to source voltage close to Vth). In some embodiments the last source follower transistor (e.g., in this case transistor 1515) may have a three diode connected transistor clamp 1520 across its gate to source. In further embodiments this arrangement may be used because its source voltage can only be as high as (Vdd_HS) (i.e., because its drain is connected to Vdd_HS) while its gate voltage can be as high as V (L_SHIFT1)−2*Vth. Thus, in some embodiments the maximum gate to source voltage on last source follower transistor 1515 may be greater than the maximum rated gate to source voltage of the device technology. The output of final source follower transistor 1515 is the input to high side transistor drive 130 (see FIG. 1), (i.e., the output is the LS_HSG signal). In further embodiments fewer or more than three source follower transistors may be used. In yet further embodiments, fewer or more than three diode connected transistors may be used in clamp 1520.

Now referring to FIG. 16, second level shift receiver 1420 is illustrated in greater detail. In one embodiment, second level shift receiver 1420 may have a down level shift circuit 1605 and an inverter circuit 1610. In some embodiments second level shift receiver 1420 may be constructed in a similar manner as first level shift receiver 1410 (see FIG. 15), except the second level shift receiver may have only one down level shifting circuit (e.g., enhancement-mode transistor 1615) and a follow on inverter circuit 1610. In one embodiment, down level shift circuit 1605 may receive the (L_SHIFT2) signal from second level shift transistor 205 (see FIG. 2). In one embodiment, inverter circuit 1610 may be driven by the (Vboot) signal, and the gate voltage of the pull up transistor of the inverter may be used as the (BLANK FET) signal driving blanking transistor 1440 (see FIG. 14). In some embodiments the voltage may go from 0 volts in a low state to (Vboot+0.5*(Vboot−Vth)) in a high state. Similar to first level shift receiver 1410, second level shift receiver 1420 may have a diode connected transistor clamp 1620 across the gate to source of source follower transistor 1615. In other embodiments, clamp 1620 may include fewer or more than three diode connected transistors.

Now referring to FIG. 17, pull up trigger circuit 1425 is illustrated in greater detail. In one embodiment, pull up trigger circuit 1425 may have a first inverter 1705, a second inverter 1710, an RC pulse generator 1715 and a gate to source clamp 1720. In some embodiments pull up trigger circuit 1425 may receive the (L_SHIFT1) signal as an input, and in response, generate a pulse as soon as the (L_SHIFT1) voltage transitions to approximately the input threshold of first inverter 1705. The generated pulse may be used as the (PULLUP_FET) signal that drives pull up transistor 1435 (see FIG. 14). Second inverter 1710 may be driven by (Vboot) instead of (Vdd_HS) because pull up transistor 1435 gate voltage may need to be larger than the (L_SHIFT1) signal voltage.

Now referring to FIG. 18, high side UVLO circuit 1415 is illustrated in greater detail. In one embodiment, high side UVLO circuit 1415 may have down level shifter 1805, a resistor pull up inverter with asymmetric hysteresis 1810 and a gate to source clamp 1815. In further embodiments, the (HS_UVLO) signal generated by high side UVLO circuit 1415 may aid in preventing circuit failure by turning off the (HS_GATE) signal generated by high side drive circuit 130 (see FIG. 14) when bootstrap capacitor 110 voltage goes below a certain threshold. In some embodiments, bootstrap capacitor 110 voltage (Vboot) (i.e., a floating power supply voltage) is measured, and in response, a logic signal is generated and combined with the output signal (LS_HSG) from first level shift receiver 1410 which is then used as the input to the high side gate drive circuit 130. More specifically, in this embodiment, for example, the UVLO circuit is designed to engage when (Vboot) reduces to less than 4*Vth above switch node (Vsw) 145 voltage. In other embodiments a different threshold level may be used.

In further embodiments, high side UVLO circuit 1415 may down shift (Vboot) in down level shifter 1805 and transfer the signal to inverter with asymmetric hysteresis 1810. The output of inverter with asymmetric hysteresis 1810 may generate the (HS_UVLO) signal which is logically combined with the output from the first level shift receiver 1410 to turn off high side transistor 125 (see FIG. 1). In some embodiments the hysteresis may be used to reduce the number of self-triggered turn on and turn off events of high side transistor 125 (see FIG. 1), that may be detrimental to the overall performance of half bridge circuit 100.

Now referring to FIG. 19, high side transistor driver 130 is illustrated in greater detail. High side transistor driver 130 may have a first inverter stage 1905 followed by a high side drive stage 1910. First inverter stage 1905 may invert the down shifted (LS_HSG) signal received from level shift 1 receiver 1410 (see FIG. 15). The downshifted signal may then be sent through high side drive stage 1910. High side drive stage 1910 may generate the (HS_GATE) signal to drive high side transistor 125 (see FIG. 1). In further embodiments first inverter stage 1905 may contain a two input NOR gate that may ensure high side transistor 125 (see FIG. 1) is turned off when the (HS_UVLO) signal is in a high state.

Now referring to FIG. 20, a reference voltage generation circuit 2000 may be used, to generate a high side reference voltage from a supply rail. Such a circuit maybe placed on the high side GaN device 105 for generating internal power supplies which are referenced to the switch node voltage 145. In some embodiments, circuit 2000 may be similar to startup circuit 155 in FIG. 9. One difference in circuit 2000 may be the addition of a source follower capacitor 2010 connected between first node 2011 and second node 2012. In some embodiments, source follower capacitor 2010 may be needed to ensure that a well regulated voltage, which does not fluctuate with dv/dt appearing at the switch node (Vsw) 145, develops between the first node 2011 and the second node 2012. In other embodiments a reference voltage capacitor 2015 may be connected between a source of reference voltage transistor 2055 and second node 2012. In some embodiments the drain of the reference voltage transistor 2055 may be connected to the (Vboot) node. In some embodiments, reference voltage capacitor 2015 may be needed to ensure that (Vref) is well regulated and does not respond to high dv/dt conditions at switch node (Vsw) 145 (see FIG. 1). In yet further embodiments, another difference in circuit 2000 may be that second node 2012 may be coupled to a constantly varying voltage, such as switch node (Vsw) 145 (see FIG. 1), rather than a ground connection through a current sink circuit 915 (see FIG. 9). In yet further embodiments (Vref) can be used as (Vdd_HS) in the half bridge circuit 100.

Another difference in circuit 2000 may be the addition of a high-voltage diode connected transistor 2025 (i.e., the gate of the transistor is coupled to the source of the transistor) coupled between depletion-mode transistor 2005 and series of identical diode connected enhancement-mode low-voltage transistors 2020. More specifically, high-voltage diode connected transistor 2025 may have source coupled to the source of depletion-mode transistor 2005, a drain coupled to first node 2011 and a gate coupled to its source. High-voltage diode connected transistor 2025 may be used to ensure that source follower capacitor 2010 does not discharge when the voltage at the top plate of the source follower capacitor rises above (V+). In further embodiments source follower capacitor 2010 may be relatively small and may be integrated on a semiconductor substrate or within an electronic package. Also shown in FIG. 21 is bootstrap capacitor 110 that may be added externally in a half bridge circuit.

In some embodiments, shield capacitor 160 (see FIG. 1) may be connected from first level shift node 305 (see FIG. 3) and second level shift node (not shown) to switch node 145 to assist in reducing the false triggering discussed above. In some embodiments, the larger the value of shield capacitor 160, the more immune the circuit will be to false triggering effects due to the parasitic capacitance to ground. However, during high side transistor 125 turn off, shield capacitor 160 may be discharged through pull up resistor 303 (see FIG. 3) connected to first level shift node 305. This may significantly slow down high side transistor 125 turn off process. In some embodiments this consideration may be used to set an upper limit on the value of shield capacitor 160. In further embodiments, an overvoltage condition on first level shift node 305 (see FIG. 3) may be prevented by the use of a clamp circuit 161 (see FIG. 1) between the first level shift node and switch node 145. In some embodiments, clamp circuit 161 maybe composed of a diode connected transistor where a drain of the transistor is connected to first level shift node 305 (see FIG. 3) and a gate and a source are connected to switch node (Vsw) 145 (see FIG. 1). In further embodiments, a second shield capacitor and a second clamp circuit may be placed between the second level shift node and switch node (Vsw) 145 (see FIG. 1).

Half Bridge Circuit #1 Operation

The following operation sequence for half-bridge circuit 100 is for example only and other sequences may be used without departing from the invention. Reference will now be made simultaneously to FIGS. 1, 2 and 14.

In one embodiment, when the (PWM_LS) signal from the controller is high, low side logic, control and level shift circuit 150 sends a high signal to low side transistor driver 120. Low side transistor driver 120 then communicates through the (LS_GATE) signal to low side transistor 115 to turn it on. This will set the switch node voltage (Vsw) 145 close to 0 volts. When low side transistor 115 turns on, it provides a path for bootstrap capacitor 110 to become charged through bootstrap charging circuit 157 which may be connected between (Vcc) and (Vboot). The charging path has a parallel combination of a high voltage bootstrap diode 1205 (see FIG. 12) and transistor 1210. The (BOOTFET_DR) signal provides a drive signal to bootstrap transistor 1210 (see FIG. 12) that provides a low resistance path for charging bootstrap capacitor 110.

Bootstrap diode 1205 (see FIG. 12) may be used to ensure that there is a path for charging bootstrap capacitor 110 during startup when there is no low side transistor 115 gate drive signal (LS_GATE). During this time the (PWM_HS) signal should be low. If the (PWM_HS) signal is inadvertently turned on (i.e., in a high state) during this time the (STP_HS) signal generated from low side transistor driver 120 will prevent high side transistor 125 from turning on. If the (PWM_LS) signal is turned on while the (PWM_HS) signal is on, the (STP_LS) signal generated from level shift driver circuit 217 will prevent low side transistor 115 from turning on. Also, in some embodiments the (LS_UVLO) signal may prevent low side transistor 115 and high side transistor 125 from turning on when either (Vcc) or (Vdd_LS) goes below a preset threshold voltage level.

In further embodiments, when the (PWM_LS) signal is low, low side gate signal (LS_GATE) to low side transistor 115 is also low. During the dead time between the (PWM_LS) signal low state to the (PWM_HS) high state transition, an inductive load will force either high side transistor 125 or low side transistor 115 to turn on in the synchronous rectifier mode, depending on direction of power flow. If high side transistor 125 turns on during the dead time (e.g., during boost mode operation), switch node (Vsw) 145 voltage may rise close to (V+) 135 (rail voltage).

In some embodiments, a dv/dt condition on switch node 145 (Vsw) may tend to pull first level shift node (LSHIFT_1) 305 (see FIG. 3) to a low state relative to switch node (Vsw) 145, due to capacitive coupling to ground. This may turn on high side gate drive circuit 130 causing unintended triggering of high side transistor 125. In one embodiment, this may result in no dead time which may harm half bridge circuit 100 with a shoot through condition. In further embodiments, to prevent this condition from occurring, blanking pulse generator 223 may sense the turn off transient of low side transistor 115 and send a pulse to turn on second level shift transistor 205. This may pull the (L_SHIFT2) signal voltage to a low state which then communicates with second level shift receiver 1420 to generate a blanking pulse signal (B_PULSE) to drive blanking transistor 1440. Blanking transistor 1440 may then act as a pull up to prevent first level shift node (LSHIFT_1) 305 (see FIG. 3) from going to a low state relative to switch node (Vsw) 145.

In further embodiments, after the dead time, when the (PWM_HS) signal goes to a high state, level shift driver circuit 217 may send a high signal to the gate of first level shift transistor 203 (via the L1_DR signal from level shift driver circuit 217). The high signal will pull first level shift node (LSHIFT_1) 305 (see FIG. 3) low relative to switch node (Vsw) 145 which will result in a high signal at the input of high side transistor 125, turning on high side transistor 125. Switch node voltage (Vsw) 145 will remain close to (V+) 135. In one embodiment, during this time, bootstrap capacitor 110 may discharge through first level shift transistor 203 (which is in an on state during this time).

If high side transistor 125 stays on for a relatively long time (i.e., a large duty cycle) bootstrap capacitor 110 voltage will go down to a low enough voltage that it will prevent high side transistor 125 from turning off when the (PWM_HS) signal goes low. In some embodiments this may occur because the maximum voltage the (L_SHIFT1) signal can reach is (Vboot) which may be too low to turn off high side transistor 125. In some embodiments, this situation may be prevented by high side UVLO circuit 1415 that forcibly turns off high side transistor 125 by sending a high input to high side gate drive circuit 130 when (Vboot) goes below a certain level.

In yet further embodiments, when the (PWM_HS) signal goes low, first level shift transistor 203 will also turn off (via the L1_DR signal from the level shift driver circuit 217). This will pull first level shift node (LSHIFT_1) 305 (see FIG. 3) to a high state. However, in some embodiments this process may be relatively slow because the high value pull up resistor 303 (see FIG. 3) (used to reduce power consumption in some embodiments) needs to charge all the capacitances attached to first level shift node (L_SHIFT1) 305 (see FIG. 3) including the output capacitance (Coss) of first level shift transistor 213 and shield capacitor 160. This may increase the turn off delay of high side transistor 125. In order to reduce high side transistor 125 turn off delay, pull up trigger circuit 1425 may be used to sense when first level shift node (L_SHIFT1) 305 (see FIG. 3) goes above (Vth). This condition may generate a (PULLUP_FET) signal that is applied to pull up transistor 1435 which, acting in parallel with pull up resistor 1430, may considerably speed up the pull up of first level shift node (L_SHIFT1) 305 (see FIG. 3) voltage, hastening the turn off process.

Half Bridge Circuit #2

Now referring to FIG. 21, a second embodiment of a half bridge circuit 2100 is disclosed. Half bridge circuit 2100 may have the same block diagram as circuit 100 illustrated in FIG. 1, however the level shift transistors in circuit 2100 may operate with pulsed inputs, rather than a continuous signal, as described in more detail below. In some embodiments, pulsed inputs may result in lower power dissipation, reduced stress on the level shift transistors and reduced switching time, as discussed in more detail below.

Continuing to refer to FIG. 21, one embodiment includes an integrated half bridge power conversion circuit 2100 employing a low side GaN device 2103, a high side GaN device 2105, a load 2107, a bootstrap capacitor 2110 and other circuit elements, as discussed in more detail below. Some embodiments may also have an external controller (not shown in FIG. 21) providing one or more inputs to circuit 2100 to regulate the operation of the circuit. Circuit 2100 is for illustrative purposes only and other variants and configurations are within the scope of this disclosure.

As further illustrated in FIG. 21, in one embodiment, integrated half bridge power conversion circuit 2100 may include a low side circuit disposed on low side GaN device 2103 that includes a low side transistor 2115 having a low side control gate 2117. The low side circuit may further include an integrated low side transistor driver 2120 having an output 2123 connected to a low side transistor control gate 2117. In another embodiment there may be a high side circuit disposed on high side GaN device 2105 that includes a high side transistor 2125 having a high side control gate 2127. The high side circuit may further include an integrated high side transistor driver 2130 having an output 2133 connected to high side transistor control gate 2127.

High side transistor 2125 may be used to control the power input into power conversion circuit 2100 and have a voltage source (V+) 2135 (sometimes called a rail voltage) connected to a drain 2137 of the high side transistor. High side transistor 2125 may further have a source 2140 that is coupled to a drain 2143 of low side transistor 2115, forming a switch node (Vsw) 2145. Low side transistor 2115 may have a source 2147 connected to ground. In one embodiment, low side transistor 2115 and high side transistor 2125 may be enhancement-mode field-effect transistors. In other embodiments low side transistor 2115 and high side transistor 2125 may be any other type of device including, but not limited to, GaN-based depletion-mode transistors, GaN-based depletion-mode transistors connected in series with silicon based enhancement-mode field-effect transistors having the gate of the depletion-mode transistor connected to the source of the silicon-based enhancement-mode transistor, silicon carbide based transistors or silicon-based transistors.

In some embodiments high side device 2105 and low side device 2103 may be made from a GaN-based material. In one embodiment the GaN-based material may include a layer of GaN on a layer of silicon. In further embodiments the GaN based material may include, but not limited to, a layer of GaN on a layer of silicon carbide, sapphire or aluminum nitride. In one embodiment the GaN based layer may include, but not limited to, a composite stack of other III nitrides such as aluminum nitride and indium nitride and III nitride alloys such as AlGaN and InGaN

Low Side Device

Low side device 2103 may have numerous circuits used for the control and operation of the low side device and high side device 2105. In some embodiments, low side device 2103 may include a low side logic, control and level shift circuit (low side control circuit) 2150 that controls the switching of low side transistor 2115 and high side transistor 2125 along with other functions, as discussed in more detail below. Low side device 2103 may also include a startup circuit 2155, a bootstrap capacitor charging circuit 2157 and a shield capacitor 2160, as also discussed in more detail below.

Now referring to FIG. 22, the circuits within low side control circuit 2150 are functionally illustrated. Each circuit within low side control circuit 2150 is discussed below, and in some cases is shown in more detail in FIGS. 23-28. In one embodiment the primary function of low side control circuit 2150 may be to receive one or more input signals, such as a PWM signal from a controller, and control the operation of low side transistor 2115, and high side transistor 2125.

First level shift transistor 2203, may be an “on” pulse level shift transistor, while second level shift transistor 2215 may be an “off” pulse level shift transistor. In one embodiment, a pulse width modulated high side (PWM_HS) signal from a controller (not shown) may be processed by inverter/buffer 2250 and sent on to an on pulse generator 2260 and an off pulse generator 2270. On pulse generator 2260 may generate a pulse that corresponds to a low state to high state transient of the (PWM_HS) signal, thus turning on first level shift transistor 2203 during the duration of the pulse. Off pulse generator 2270 may similarly generate a pulse that corresponds to the high state to low state transition of the (PWM_HS) signal, thus turning on second level shift transistor 2205 for the duration of the off pulse.

First and second level shift transistors 2203, 2205, respectively, may operate as pull down transistors in resistor pull up inverter circuits. More specifically, turning on may mean the respective level shift node voltages get pulled low relative to switch node (Vsw) 2145 voltage, and turning off may result in the respective level shift nodes assuming the (Vboot) voltage. Since first and second level shift transistors 2203, 2215, respectively, are “on” only for the duration of the pulse, the power dissipation and stress level on these two devices may be less than half bridge circuit 100 illustrated in FIG. 1.

First and second resistors 2207, 2208, respectively, may be added in series with the sources of first and second level shift transistors 2203, 2215, respectively to limit the gate to source voltage and consequently the maximum current through the transistors. First and second resistors 2207, 2208, respectively, could be smaller than the source follower resistors in half bridge circuit 100 illustrated in FIG. 1, which may help make the pull down action of first and second level shift transistors 2203, 2215 faster, reducing the propagation delays to high side transistor 2125.

In further embodiments, first and second resistors 2207, 2208, respectively, could be replaced by any form of a current sink. One embodiment may connect the source of first and second level shift transistors 2203, 2205, respectively to a gate to source shorted depletion-mode device. One embodiment of a depletion-mode transistor formed in a high-voltage GaN technology may be to replace the enhancement-mode gate stack with one of the high-voltage field plate metals superimposed on top of the field dielectric layers. The thickness of the field dielectric and the work function of the metal may control the pinch-off voltage of the stack.

In further embodiments, first and second resistors 2207, 2208, respectively may be replaced by a current sink. In one embodiment a reference current (Iref) that is generated by startup circuit 2155 (see FIG. 21) may be used. Both the depletion-mode transistor and current sink embodiments may result in a significant die area reduction compared to the resistor option (i.e., because a small depletion transistor would suffice and Iref is already available).

Bootstrap transistor drive circuit 2225 may be similar to bootstrap transistor drive circuit 225 illustrated in FIG. 2 above. Bootstrap transistor drive circuit 2225 may receive input from low side drive circuit 2220 (see FIG. 22) and provide a gate drive signal called (BOOTFET_DR) to the bootstrap transistor in bootstrap capacitor charging circuit 2157 (see FIG. 21), as discussed in more detail above.

Now referring to FIG. 23, first level shift transistor 2203 is illustrated along with a pull up resistor 2303 that may be located in high side device 2105. In some embodiments, first level shift transistor 2203 may operate as a pull down transistor in a resistor pull up inverter similar to first level shift transistor 203 illustrated in FIG. 3. As discussed above, pull up resistor 2303 may be disposed in high side device 2105 (see FIG. 21). Second level shift transistor 2215 may have a similar configuration. In some embodiments there may be a first capacitance between the first output terminal (LS NODE) 2305 and switch node (Vsw) 2145 (see FIG. 21), and a second capacitance between a first output terminal 2305 and ground, where the first capacitance is greater than the second capacitance. The first capacitance may be designed such that in response to a high dv/dt signal at the switch node (Vsw) 2145 (see FIG. 21), a large portion of the C*dv/dt current is allowed to conduct through the first capacitance ensuring that the voltage at first output terminal 2305 tracks the voltage at the switch node (Vsw). A shield capacitor 2160 (see FIG. 21) may be configured to act as the first capacitor as described above. In further embodiments shield capacitor 2160 (see FIG. 21) may be used to create capacitance between first output terminal 2305 and switch node (Vsw) 2145 (see FIG. 21) in the half bridge power conversion circuit 2100. Shield capacitor 2160 may also be used to minimize the capacitance between first output terminal 2305 and a substrate of the semiconductor device. In further embodiments shield capacitor 2160 may be constructed on low side GaN device 2103.

Now referring to FIG. 24, inverter/buffer circuit 2250 is illustrated in greater detail. In one embodiment inverter/buffer circuit 2250 may have a first inverter stage 2405 and a first buffer stage 2410. In further embodiments, inverter/buffer circuit 2250 may be driven directly by the (PWM_HS) signal from the controller (not shown). The output of first inverter stage 2405 may be the input signal (PULSE_ON) to on pulse generator 2260 (see FIG. 22) while the output of first buffer stage 2410 may be an input signal (PULSE OFF) to off pulse generator 2270.

In some embodiments, an optional (LS_UVLO) signal may be generated by sending a signal generated by UVLO circuit 2227 (see FIG. 22) in to a NAND gate disposed in first inverter stage 2405. This circuit may be used to turn off the level shift operation if either (Vcc) or (Vdd_LS) go below a certain reference voltage (or a fraction of the reference voltage). In further embodiments, inverter/buffer circuit 2250 may also generate a shoot through protection signal (STP_LS1) for low side transistor 2115 (see FIG. 21) that may be applied to low side transistor gate drive circuit 2120. This may turn off low side transistor gate drive circuit 2120 (see FIG. 21) when the (PWM_HS) signal is high, preventing shoot through.

Now referring to FIG. 25, on pulse generator 2260 is illustrated in greater detail. In one embodiment on pulse generator 2260 may have a first inverter stage 2505, a first buffer stage 2510, an RC pulse generator 2515, a second inverter stage 2520 a third inverter stage 2525 and a third buffer stage 2530. In further embodiments the (PULSE_ON) signal input from inverter/buffer circuit 2250 (see FIG. 22) may be first inverted and then transformed into an on pulse by RC pulse generator 2515 and a square wave generator. The result of this operation is the gate drive signal (LI_DR) that is transmitted to first level shift transistor 2203 (see FIG. 22).

In further embodiments, on pulse generator 2260 may comprise one or more logic functions, such as for example, a binary or combinatorial function. In one embodiment, on pulse generator 2260 may have a multiple input NOR gate for the (STP_HS) signal. The (STP_HS) signal may have the same polarity as the (LS_GATE) signal. Therefore, if the (STP_HS) signal is high (corresponding to LS_GATE signal being high) the on pulse may not be generated because first inverter circuit 2505 in FIG. 25 will be pulled low which will deactivate pulse generator 2515.

In further embodiments, RC pulse generator 2515 may include a clamp diode (not shown). The clamp diode may be added to ensure that RC pulse generator 2515 works for very small duty cycles for the (PWM_LS) signal. In some embodiments, on pulse generator 2260 may be configured to receive input pulses in a range of 2 nanoseconds to 20 microseconds and to transmit pulses of substantially constant duration within the range. In one embodiment the clamp diode may turn on and short out a resistor in RC pulse generator 2515 (providing a very small capacitor discharge time) if the voltage across the clamp diode becomes larger than (Vth). This may significantly improve the maximum duty cycle of operation (with respect to the PWM_HS signal) of pulse generator circuit 2260.

Now referring to FIG. 26, off pulse generator 2270 is illustrated in greater detail. In one embodiment off pulse generator 2270 may have an RC pulse generator 2603, a first inverter stage 2605, a second inverter stage 2610 and a first buffer stage 2615. In further embodiments, off pulse generator 2270 may receive an input signal (PULSE OFF) from inverter/buffer circuit 2250 (see FIG. 22) that may be subsequently communicated to RC pulse generator 2603.

In further embodiments the pulse from RC pulse generator 2603 is sent through first inverter stage 2605, second inverter stage 2610 and buffer stage 2615. The pulse may then be sent as the (L2_DR) signal to second level shift transistor 2215 (see FIG. 22). A clamp diode may also be included in off pulse generator 2270. In some embodiments, the operating principle may be similar to the operating principle discussed above with regard to on pulse generator 2260 (see FIG. 25). Such operating principles may ensure that off pulse generator 2270 operates for very low on times of high side transistor 2125 (see FIG. 21) (i.e. the circuit will operate for relatively small duty cycles). In some embodiments, off pulse generator 2270 may be configured to receive input pulses in a range of 2 nanoseconds to 20 microseconds and to transmit pulses of substantially constant duration within the range. In further embodiments an off level shift pulse can be shortened by an on input pulse to enable an off time of less than 50 nanoseconds on high side transistor 2125.

In some embodiments, RC pulse generator 2603 may include a capacitor connected with a resistor divider network. The output from the resistor may be a signal (INV) that is sent to an inverter 2275 (see FIG. 22) that generates a shoot through protection signal (STP_LS2) transmitted to low side driver circuit 2220. In further embodiments, off pulse generator 2270 may comprise one or more logic functions, such as for example, a binary or combinatorial function. In one embodiment the (STP_LS2) signal is sent to a NAND logic circuit within low side driver circuit 2220, similar to the (STP_LS1) signal. In some embodiments, these signals may be used to ensure that during the duration of the off pulse signal (PULSE OFF), low side transistor 2115 (see FIG. 21) does not turn on (i.e., because high side transistor 2125 turns off during the off pulse). In some embodiments this methodology may be useful to compensate for a turn off propagation delay (i.e., the PULSE OFF signal may enable shoot through protection), ensuring that low side transistor 2115 will only turn on after high side transistor 2125 gate completely turns off.

In further embodiments, a blanking pulse can be level shifted to high side device 2105 using second level shift transistor 2215. To accomplish this, a blanking pulse may be sent into a NOR input into first inverter stage 2605. The blanking pulse may be used to inhibit false triggering due to high dv/dt conditions at switch node Vsw 2145 (see FIG. 20). In some embodiments no blanking pulse may be used to filter dv/dt induced or other unwanted level shift output pulses.

Now referring to FIG. 27, blanking pulse generator 2223 is illustrated in greater detail. In one embodiment, blanking pulse generator 2223 may be a more simple design than used in half bridge circuit 100 illustrated in FIG. 1 because the square wave pulse generator is already part of off pulse generator 2270. In one embodiment the (LS_GATE) signal is fed as the input to blanking pulse generator 2223 from low side gate drive circuit 2220 (see FIG. 22). This signal may be inverted and then sent through an RC pulse generator to generate a positive going pulse. In some embodiments, an inverted signal may be used because the pulse needs to correspond to the falling edge of the (LS_GATE) signal. The output of this may be used as the blanking pulse input (B_PULSE) to off pulse generator 2270.

Now referring to FIG. 28, low side transistor drive circuit 2220 is illustrated in greater detail. In one embodiment low side transistor drive circuit 2220 may have a first inverter stage 2805, a first buffer stage 2810, a second inverter stage 2815, a second buffer stage 2820 and a third buffer stage 2825. In some embodiments two inverter/buffer stages may be used because the input to the gate of low side transistor 2115 is synchronous with the (PWM_LS) signal. Thus, in some embodiments a (PWM_LS) high state may correspond to a (LS_GATE) high state and vice versa.

In further embodiments, low side transistor drive circuit 2220 may also include an asymmetric hysteresis using a resistor divider with a transistor pull down similar to the scheme described in 120 (see FIG. 8). In one embodiment low side transistor drive circuit 2220 includes multiple input NAND gates for the (STP_LS1) and (STP_LS2) (shoot through prevention on low side transistor 2115) signals. The (STP_LS1) and (STP_LS2) signals may ensure that low side transistor drive circuit 2220 (see FIG. 22) does not communicate with low side transistor 2115 (see FIG. 21) when high side transistor 2125 is on. This technique may be used to avoid the possibility of shoot-through. Other embodiments may include NAND gates (similar to the ones employed above in FIG. 28) for the (LS_UVLO) signal. One embodiment may include a turn off delay resistor in series with the gate of the final pull down transistor. This may be used to ensure the bootstrap transistor is turned off before low side transistor 2115 turns off.

In further embodiments, low side device 2103 (see FIG. 21) may also include a startup circuit 2155, bootstrap capacitor charging circuit 2157, a shield capacitor 2160, and a UVLO circuit 2227 that may be similar to startup circuit 155, bootstrap capacitor charging circuit 157, shield capacitor 160 and UVLO circuit 227, respectively, as discussed above.

High Side Device

Now referring to FIG. 29, high side logic and control circuit 2153 and how it interacts with high side transistor driver 2130 is illustrated in greater detail. In some embodiments, high side logic and control circuit 2153 may operate in similar ways as high side logic and control circuit 153, discussed above in FIG. 15. In further embodiments, high side logic and control circuit 2153 may operate in different ways, as discussed in more detail below.

In one embodiment, level shift 1 receiver circuit 2910 receives an (L_SHIFT1) signal from first level shift transistor 2203 (see FIG. 22) that receives an on pulse at the low state to high state transition of the (PWM_HS) signal, as discussed above. In response, level shift 1 receiver circuit 2910 drives a gate of pull up transistor 2960 (e.g., in some embodiments a low-voltage enhancement-mode GaN transistor). In further embodiments, pull up transistor 2960 may then pull up a state storing capacitor 2955 voltage to a value close to (Vdd_HS) with respect to switch node (Vsw) 2145 voltage. The voltage on a state storing capacitor 2955 may then be transferred to high side transistor driver 2130 and on to the gate of high side transistor gate 2127 (see FIG. 21) to turn on high side transistor 2125. In some embodiments state storing capacitor 2955 may be a latching storage logic circuit configured to change state in response to a first pulsed input signal and to change state in response to a second pulsed input signal. In further embodiments, state storing capacitor 2955 may be replaced by any type of a latching circuit such as, but not limited to an RS flip-flop.

In further embodiments, during this time, level shift 2 receiver circuit 2920 may maintain pull down transistor 2965 (e.g., in some embodiments a low-voltage enhancement-mode GaN transistor) in an off state. This may cut off any discharge path for state storing capacitor 2955. Thus, in some embodiments, state storing capacitor 2955 may have a relatively small charging time constant and a relatively large discharge time constant.

Similarly, level shift 2 receiver 2920 may receive an (L_SHIFT2) signal from second level shift transistor 2215 (see FIG. 22) that receives an off pulse at the high state to low state transition of the (PWM_HS) signal, as discussed above. In response, level shift 2 receiver circuit 2920 drives a gate of pull down transistor 2965 (e.g., in some embodiments a low-voltage enhancement-mode GaN transistor). In further embodiments, pull down transistor 2965 may then pull down (i.e., discharge) state storing capacitor 2955 voltage to a value close to switch node (Vsw) 2145, that may consequently turn off high side transistor 2125 through high side transistor driver 2130.

Continuing to refer to FIG. 29, first and second shield capacitors 2970, 2975, respectively, may be connected from (L_SHIFT1) and (L_SHIFT2) nodes to help prevent false triggering during high dv/dt conditions at switch node (Vsw) 2145 (see FIG. 21). In further embodiments there may also be a clamp diode between the (L_SHIFT1) and (L_SHIFT2) nodes and the switch node (Vsw) 2145 (see FIG. 21). This may ensure that the potential difference between switch node (Vsw) 2145 (see FIG. 21) and the (L_SHIFT1) and (L_SHIFT2) nodes never goes above (Vth). This may be used to create a relatively fast turn on and turn off for high side transistor 2125 (see FIG. 21).

Now referring to FIG. 30, level shift 1 receiver 2910 is illustrated in greater detail. In one embodiment level shift 1 receiver 2910 may include a down level shifter 3005, a first inverter 3010, a second inverter 3015, a first buffer 3020, a third inverter 3025, a second buffer 3030 and a third buffer 3135. In some embodiments, level shift 1 receiver 2910 down shifts (i.e., modulates) the (L_SHIFT1) signal by a voltage of 3*Vth (e.g., using three enhancement-mode transistors where each may have a gate to source voltage close to Vth). In other embodiments a fewer or more downshift transistors may be used.

In further embodiments, the last source follower transistor may have a three diode connected transistor clamp across its gate to its source. In some embodiments this configuration may be used because its source voltage can only be as high as (Vdd_HS) (i.e., because its drain is connected to Vdd_HS) while its gate voltage can be as high as V (L_SHIFT1)−2*Vth. Thus, in some embodiments the maximum gate to source voltage on the final source follower transistor can be greater than the maximum rated gate to source voltage in the technology.

In further embodiments, first inverter 3010 may also have a NOR Gate for the high side under voltage lock out using the (UV_LS1) signal generated by high side UVLO circuit 2915. In one embodiment, an output of level shift 1 receiver 2910 (see FIG. 29) may be a (PU_FET) signal that is communicated to a gate of pull up transistor 2960 (see FIG. 29). This signal may have a voltage that goes from 0 volts in a low state to (Vdd_HS)+(Vdd_HS−Vth) in a high state. This voltage may remain on for the duration of the on pulse.

Now referring to FIG. 31, level shift 2 receiver 2920 is illustrated in greater detail. In one embodiment level shift 2 receiver 2920 may be similar to level shift 1 receiver 2910 discussed above. In further embodiments level shift 2 receiver 2920 may include a blanking pulse generator 3105, a down level shifter 3110, a first inverter 3115, a second inverter 3120, a first buffer 3125, an third inverter 3130, a second buffer 3135 and a third buffer 3140. In one embodiment, blanking pulse generator 3105 may be used in addition to a 3*Vth down level shifter 3110 and multiple inverter/buffer stages.

In other embodiments different configurations may be used. In some embodiments, this particular configuration may be useful when level shift 2 receiver 2920 doubles as a high side transistor 2125 (see FIG. 21) turn off as well as a blanking transistor 2940 (see FIG. 29) drive for better dv/dt immunity. In some embodiments, blanking pulse generator 3105 may be identical to level shift 2 receiver 1520 illustrated in FIG. 17. In one embodiment level shift 2 receiver 2920 (see FIG. 29) may receive (L_SHIFT2) and (UV_LS2) signals and in response, transmit a (PD_FET) signal to pull down transistor 2965. In further embodiments, first inverter 3115 may have a two input NAND gate for the (UV_LS2) signal from high side UVLO circuit 2915 (see FIG. 29).

Now referring to FIG. 32, high side UVLO circuit 2915 is illustrated in greater detail. In one embodiment high side UVLO circuit 2915 may include a down level shifter 3205 and a resistor pull up inverter stage 3210. In some embodiments, high side UVLO circuit 2915 may be configured to prevent circuit failure by turning off the (HS_GATE) signal to high side transistor 2125 (see FIG. 21) when bootstrap capacitor 2110 voltage goes below a certain threshold. In one example embodiment high side UVLO circuit 2915 is designed to engage when (Vboot) reduces to a value less than 4*Vth below switch node (Vsw) 2145 voltage. In another embodiment the output of down level shifter 3205 may be a (UV_LS2) signal transmitted to second level shift receiver 2920 and the output of resistor pull up inverter stage 3210 may be an (UV_LS1) signal that is transmitted to first level shift receiver 2910.

As discussed below, in some embodiments high side UVLO circuit 2915 may be different from high side UVLO circuit 1415 for half bridge circuit 100 discussed above in FIGS. 14 and 18, respectively. In one embodiment, the (Vboot) signal may be down shifted by 3*Vth and transferred to resistor pull up inverter stage 3210. In further embodiments, since level shift 2 receiver circuit 2920 (see FIG. 29) controls the turn off process based on high side transistor 2125 (see FIG. 21), directly applying a 3*Vth down shifted output to the NAND gate at the input of level shift 2 receiver circuit 2920 will engage the under voltage lock out.

However, in some embodiments, because the bootstrap voltage may be too low this may also keep pull up transistor 2960 (see FIG. 29) on. In some embodiments, this may result in a conflict. While level shift 2 receiver circuit 2920 (see FIG. 29) tries to keep high side transistor 2125 (see FIG. 21) off, level shift 1 receiver circuit 2910 may try to turn the high side transistor on. In order to avoid this situation, some embodiments may invert the output of the 3*Vth down shifted signal from high side UVLO circuit 2915 (see FIG. 29) and send it to a NOR input on level shift 1 receiver circuit 2910. This may ensure that level shift 1 receiver circuit 2910 does not interfere with the UVLO induced turn off process.

Now referring to FIG. 33, high side transistor driver 2130 is illustrated in greater detail. In one embodiment high side transistor driver 2130 may include a first inverter 3305, a first buffer 3310, a second inverter 3315, a second buffer 3320 and a third buffer 3325. In some embodiments high side transistor driver 2130 may be a more basic design than high side transistor driver 130 employed in half bridge circuit 100 illustrated in FIG. 1. In one embodiment, high side transistor driver 2130 receives an (S CAP) signal from state storage capacitor 2955 (see FIG. 29) and delivers a corresponding drive (HS_GATE) signal to high side transistor 2125 (see FIG. 21). More specifically, when the (S CAP) signal is in a high state, the (HS_GATE) signal is in a high state and vice versa.

Half Bridge Circuit #2 Operation

The following operation sequence for half-bridge circuit 2100 (see FIG. 21) is for example only and other sequences may be used without departing from the invention. Reference will now be made simultaneously to FIGS. 21, 22 and 29.

In one embodiment, when the (PWM_LS) signal is in a high state, low side logic, control and level shift circuit 2150 may send a high signal to low side transistor driver 2120 which then communicates that signal to low side transistor 2115 to turn it on. This may set switch node (Vsw) 2145 voltage close to 0 volts. In further embodiments, when low side transistor 2115 turns on it may provide a path for bootstrap capacitor 2110 to charge. The charging path may have a parallel combination of a high-voltage bootstrap diode and transistor.

In some embodiments, bootstrap transistor drive circuit 2225 may provide a drive signal (BOOTFET_DR) to the bootstrap transistor that provides a low resistance path for charging bootstrap capacitor 2110. In one embodiment, the bootstrap diode may ensure that there is a path for charging bootstrap capacitor 2110 during startup when there is no low side gate drive signal (LS_GATE). During this time the (PWM_HS) signal should be in a low state. If the (PWM_HS) signal is inadvertently turned on during this time, the (STP_HS) signal generated from low side driver circuit 2220 may prevent high side transistor 2125 from turning on. If the (PWM_LS) signal is turned on while the (PWM_HS) signal is on, then the (STP_LS1) and (STP_LS2) signals generated from inverter/buffer 2250 and inverter 2275, respectively will prevent low side transistor 2115 from turning on. In addition, in some embodiments the (LS_UVLO) signal may prevent low side gate 2117 and high side gate 2127 from turning on when either (Vcc) or (Vdd_LS) go below a predetermined voltage level.

Conversely, in some embodiments when the (PWM_LS) signal is in a low state, the (LS_GATE) signal to low side transistor 2115 may also be in a low state. In some embodiments, during the dead time between the (PWM_LS) low signal and the (PWM_HS) high signal transition, the inductive load may force either high side transistor 2125 or low side transistor 2115 to turn on in the synchronous rectifier mode, depending on the direction of power flow. If high side transistor 2125 turns on during the dead time (e.g., in a boost mode), switch node (Vsw) 2145 voltage may rise close to (V+) 2135 (i.e., the rail voltage). This dv/dt condition on switch node (Vsw) 2145 may tend to pull the (L_SHIFT1) node to a low state relative to the switch node (i.e., because of capacitive coupling to ground) which may turn on high side transistor driver 2130 causing unintended conduction of high side transistor 2125. This condition may negate the dead time, causing shoot through.

In some embodiments this condition may be prevented by using blanking pulse generator 2223 to sense the turn off transient of low side transistor 2115 and send a pulse to turn on second level shift transistor 2205. This may pull the (L_SHIFT2) signal to a low state which may then communicate with level shift 2 receiver circuit 2920 to generate a blanking pulse to drive blanking transistor 2940. In one embodiment, blanking transistor 2940 may act as a pull up to prevent the (L_SHIFT1) signal from going to a low state relative to switch node (Vsw) 2145.

In further embodiments, after the dead time when the (PWM_HS) signal transitions from a low state to a high state, an on pulse may be generated by on pulse generator 2260. This may pull the (L_SHIFT1) node voltage low for a brief period of time. In further embodiments this signal may be inverted by level shift 1 receiver circuit 2910 and a brief high signal will be sent to pull up transistor 2960 that will charge state storage capacitor 2955 to a high state. This may result in a corresponding high signal at the input of high side transistor driver 2130 which will turn on high side transistor 2125. Switch node (Vsw) 2145 voltage may remain close to (V+) 2135 (i.e., the rail voltage). State storing capacitor 2955 voltage may remain at a high state during this time because there is no discharge path.

In yet further embodiments, during the on pulse, bootstrap capacitor 2110 may discharge through first level shift transistor 2203. However, since the time period is relatively short, bootstrap capacitor 2110 may not discharge as much as it would if first level shift transistor 2203 was on during the entire duration of the (PWM_HS) signal (as was the case in half bridge circuit 100 in FIG. 1). More specifically, in some embodiments this may result in the switching frequency at which the UVLO engages to be a relatively lower value than in half bridge circuit 100 in FIG. 1.

In some embodiments, when the (PWM_HS) signal transitions from a high state to a low state, an off pulse may be generated by off pulse generator 2270. This may pull the (L_SHIFT2) node voltage low for a brief period of time. This signal may be inverted by level shift 2 receiver circuit 2920 and a brief high state signal may be sent to pull down transistor 2965 that will discharge state storing capacitor 2955 to a low state. This will result in a low signal at the input of high side transistor driver 2130 that will turn off high side transistor 2125. In further embodiments, state storing capacitor 2955 voltage may remain at a low state during this time because it has no discharge path.

In one embodiment, since the turn off process in circuit 2100 does not involve charging level shift node capacitors through a high value pull up resistor, the turn off times may be relatively shorter than in half bridge circuit 100 in FIG. 1. In further embodiments, high side transistor 2125 turn on and turn off processes may be controlled by the turn on of substantially similar level shift transistors 2203, 2205, therefore the turn on and turn off propagation delays may be substantially similar. This may result in embodiments that have no need for a pull up trigger circuit and/or a pull up transistor as were both used in half bridge circuit 100 in FIG. 1.

ESD Circuits

Now referring to FIG. 34, in some embodiments, one or more pins (i.e., connections from a semiconductor device within an electronic package to an external terminal on the electronic package) may employ an electro-static discharge (ESD) clamp circuit to protect the circuit. The following embodiments illustrate ESD clamp circuits that may be used on one or more pins in one or more embodiments disclosed herein, as well as other embodiments that may require ESD protection. In further embodiments, the ESD clamp circuits disclosed herein may be employed on GaN-based devices.

One embodiment of an electro-static discharge (ESD) clamp circuit 3400 is illustrated. ESD clamp circuit 3400 may have a configuration employing one or more source follower stages 3405 made from enhancement-mode transistors. Each source follower stage 3405 may have a gate 3406 connected to a source 3407 of an adjacent source follower stage. In the embodiment illustrated in FIG. 34, four source follower stages 3405 are employed, however in other embodiments fewer or more may be used. Resistors 3410 are coupled to sources 3407 of source follower stages 3405.

An ESD transistor 3415 is coupled to one or more source follower stages 3405 and may be configured to conduct a current greater than 500 mA when exposed to an overvoltage pulse, as discussed below. Resistors 3410 are disposed between source 3420 of ESD transistor 3415 and each source 3407 of source follower stages 3405. Drains 3408 of source follower stages 3405 are connected to drain 3425 of ESD transistor 3415. Source 3407 of the last source follower stage is coupled to gate 3430 of ESD transistor 3415.

In one embodiment, a turn on voltage of ESD clamp circuit 3400 can be set by the total number of source follower stages 3405. However, since the last source follower stage is a transistor with a certain drain 3408 to source 3407 voltage and gate 3406 to source voltage the current through the final resistor 3410 may be relatively large and may result in a larger gate 3430 to source 3420 voltage across ESD transistor 3415. This condition may result in a relatively large ESD current capability and in some embodiments an improved leakage performance compared to other ESD circuit configurations.

In further embodiments, ESD clamp circuit 3400 may have a plurality of degrees of freedom with regard to transistor sizes and resistor values. In some embodiments ESD clamp circuit 3400 may be able to be made smaller than other ESD circuit configurations. In other embodiments, the performance of ESD clamp circuit 3400 may be improved by incrementally increasing the size of source follower stages 3405 as they get closer to ESD transistor 3415. In further embodiments, resistors 3410 can be replaced by depletion-mode transistors, reference current sinks or reference current sources, for example.

Now referring to FIG. 35 an embodiment similar to ESD clamp circuit 3400 in FIG. 34 is illustrated, however ESD clamp circuit 3500 may have resistors in a different configuration, as discussed in more detail below. ESD clamp circuit 3500 may have a configuration employing one or more source follower stages 3505 made from one or more enhancement-mode transistors. Each source follower stage 3505 may have a gate 3506 connected to a source 3507 of an adjacent source follower stage. In the embodiment illustrated in FIG. 35, four source follower stages 3505 are employed, however in other embodiments fewer or more may be used. Resistors 3510 are coupled between sources 3507 of adjacent source follower stages 3505. An ESD transistor 3515 is coupled to source follower stages 3505 with resistor 3510 disposed between source 3520 of ESD transistor 3515 and source 3507 of a source follower stage 3505. Drains 3508 of source follower stages 3505 may be coupled together and to drain 3525 of ESD transistor 3515.

Electronic Packaging

Now referring to FIGS. 36 and 37, in some embodiments, one or more semiconductor devices may be disposed in one or more electronic packages. Myriad packaging configurations and types of electronic packages are available and are within the scope of this disclosure. FIG. 36 illustrates one example of what is known as a quad-flat no-lead electronic package with two semiconductor devices within it.

Electronic package 3600 may have a package base 3610 that has one or more die pads 3615 surrounded by one or more terminals 3620. In some embodiments package base 3610 may comprise a leadframe while in other embodiments it may comprise an organic printed circuit board, a ceramic circuit or another material.

In the embodiment depicted in FIG. 36, a first device 3620 is mounted to a first die pad 3615 and a second device 3625 is mounted to a second die pad 3627. In another embodiment one or more of first and second devices 3620, 3625, respectively may be mounted on an insulator (not shown) that is mounted to package base 3610. In one embodiment the insulator may be a ceramic or other non-electrically conductive material. First and second devices 3620, 3625, respectively are electrically coupled to terminals 3640 with wire bonds 3630 or any other type of electrical interconnect such as, for example, flip-chip bumps or columns that may be used in a flip-chip application. Wirebonds 3630 may extend between device bond pads 3635 to terminals 3640, and in some cases to die pads 3615, 3627 and in other cases to device bond pads 3635 on an adjacent device.

Now referring to FIG. 37, an isometric view of electronic package 3600 is shown. Terminals 3640 and die attach pads 3615 and 3627 may be disposed on an external surface and configured to attach to a printed circuit board or other device. In further embodiments, terminals 3640 and die attach pads 3615 and 3627 may only be accessible within the inside of electronic package 3600 and other connections may be disposed on the outside of the electronic package. More specifically, some embodiments may have internal electrical routing and there may not be a one to one correlation between internal and external connections.

In further embodiments first and second devices 3620, 3625, respectively (see FIG. 36) and a top surface of package base 3610 may be encapsulated by a non-electrically conductive material, such as for example, a molding compound. Myriad other electronic packages may be used such as, but not limited to, SOIC's, DIPS, MCM's and others. Further, in some embodiments each device may be in a separate electronic package while other embodiments may have two or more electronic devices within a single package. Other embodiments may have one or more passive devices within one or more electronic packages.

In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the invention, and what is intended by the applicants to be the scope of the invention, is the literal and equivalent scope of the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction.

Claims

1. A circuit, comprising: a low-side circuit disposed on a first monolithic flip-chip semiconductor device, the first flip-chip semiconductor device formed from at least one layer of gallium-nitride disposed on at least one layer of silicon, wherein the low-side circuit comprises: a low-side switch comprising a low-side switch control gate, a low-side source, and a low-side drain; anda low-side switch driver, arranged to control a conductivity state of the low-side switch according to a first input signal; anda high-side circuit disposed on a separate second monolithic flip-chip semiconductor device, the second flip-chip semiconductor device formed from at least one layer of gallium-nitride disposed on at least one layer of silicon, wherein the high-side circuit comprises: a high-side switch comprising a high-side switch control gate, a high-side source, and a high-side drain; anda high side switch driver arranged to control a conductivity state of the high-side switch according to a second input signal;wherein the low-side drain is electrically connected to the high-side source such that the low-side circuit and the high-side circuit form a half-bridge circuit.
2. The circuit of claim 1 wherein the at least one layer of gallium-nitride is a composite stack of III-nitrides.
3. The circuit of claim 1 wherein the at least one layer of gallium-nitride includes a layer of aluminum gallium nitride.
4. The circuit of claim 1 wherein each of the first and the second flip-chip semiconductor devices include flip-chip bumps that are electrical connections.
5. The circuit of claim 1 wherein the first flip-chip semiconductor device and the second flip-chip semiconductor device are disposed on a monolithic semiconductor substrate formed from at least one layer of gallium-nitride disposed on at least one layer of silicon.
6. The circuit of claim 1 wherein the first flip-chip semiconductor device includes at least a portion of a level shifting circuit.
7. The circuit of claim 1 wherein the second flip-chip semiconductor device includes at least a portion of a level shifting circuit.
8. A circuit, comprising: a low-side circuit disposed on a first monolithic flip-chip semiconductor device, the first flip-chip semiconductor device formed on a substrate including gallium-nitride, wherein the low-side circuit comprises: a low-side enhancement-mode transistor comprising a low-side control gate, a low-side source, and a low-side drain, the low-side control gate arranged to control a conductivity state of the low-side enhancement-mode transistor according to a first input signal, wherein the first input signal is received from a low-side driver circuit; anda high-side circuit disposed on a separate second monolithic flip-chip semiconductor device, the second flip-chip semiconductor device formed on a substrate including gallium-nitride, wherein the high-side circuit comprises: a high-side enhancement-mode transistor comprising a high-side control gate, a high-side source, and a high-side drain, the high-side control gate arranged to control a conductivity state of the high-side enhancement-mode transistor according to a second input signal, wherein the second input signal is received from a high-side driver circuit;wherein the low-side drain is electrically connected to the high-side source forming a switch-node of a half-bridge circuit.
9. The circuit of claim 8 wherein the gallium-nitride comprises a composite stack of III-nitrides.
10. The circuit of claim 8 wherein the gallium-nitride includes a layer of aluminum gallium nitride.
11. The circuit of claim 8 wherein each of the first and the second flip-chip semiconductor devices include flip-chip bumps that are electrical interconnects.
12. The circuit of claim 8 wherein the first flip-chip semiconductor device and the second flip-chip semiconductor device are disposed on a common gallium-nitride layer that forms a portion of a monolithic semiconductor substrate.
13. The circuit of claim 8 wherein the first flip-chip semiconductor device includes at least a portion of a level shifting circuit.
14. The circuit of claim 8 wherein the low-side driver circuit is disposed on the first flip-chip semiconductor device.
15. The circuit of claim 8 wherein the high-side driver circuit is disposed on the second flip-chip semiconductor device.
16. A circuit, comprising: a low-side circuit disposed on a first monolithic semiconductor device having a plurality of first flip-chip interconnects, the first semiconductor device formed on a substrate including gallium-nitride and silicon, wherein the low-side circuit comprises: a low-side transistor comprising a low-side control gate, a low-side source, and a low-side drain, the low-side control gate arranged to control a conductivity state of the low-side transistor according to a first input signal, wherein the first input signal is received from a low-side driver circuit; anda high-side circuit disposed on a separate second monolithic semiconductor device having a plurality of second flip-chip interconnects, the second semiconductor device formed on a substrate including gallium-nitride and silicon, wherein the high-side circuit comprises: a high-side transistor comprising a high-side control gate, a high-side source, and a high-side drain, the high-side control gate arranged to control a conductivity state of the high-side transistor according to a second input signal, wherein the second input signal is received from a high-side driver circuit;wherein the low-side drain is electrically connected to the high-side source forming a half-bridge circuit.
17. The circuit of claim 16 wherein the gallium-nitride comprises a composite stack of III-nitrides.
18. The circuit of claim 16 wherein the first and the second semiconductor devices are disposed on a common gallium-nitride layer that forms a portion of a monolithic semiconductor substrate.
19. The circuit of claim 16 wherein the low-side driver circuit is disposed on the first semiconductor device.
20. The circuit of claim 16 wherein the high-side driver circuit is disposed on the second semiconductor device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to and is a continuation of U.S. patent application Ser. No. 17/811,797, for PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES, filed on Jul. 11, 2022, which is a continuation of U.S. patent application Ser. No. 16/699,081, for PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES, filed on Nov. 28, 2019, now U.S. Pat. No. 11,404,884, issued on Aug. 2, 2022, which is a divisional of U.S. patent application Ser. No. 16/151,695, for “PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES” filed on Oct. 4, 2018, now U.S. Pat. No. 10,530,169, issued on Jan. 7, 2020, which is a divisional of U.S. patent application Ser. No. 15/219,248, for “PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES” filed on Jul. 25, 2016, now U.S. Pat. No. 10,135,275, issued on Nov. 20, 2018, which is a continuation of U.S. patent application Ser. No. 14/667,523, for “PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES” filed on Mar. 24, 2015, now U.S. Pat. No. 9,401,612, issued on Jul. 26, 2016, which claims priority to U.S. provisional patent application No. 62/127,725, for “HALF BRIDGE POWER CONVERSION CIRCUITS USING GAN AND SILICON DEVICES” filed on Mar. 3, 2015, and also claims priority to U.S. provisional patent application No. 62/051,160, for “HYBRID HALF-BRIDGE DRIVER USING GAN AND SILICON DEVICES” filed on Sep. 16, 2014. All of the aforementioned disclosures are hereby incorporated by reference in their entirety for all purposes.

US Referenced Citations (242)

Number	Name	Date	Kind
4698530	Thomson	Oct 1987	A
5079744	Tobita et al.	Jan 1992	A
5138200	Barsanti et al.	Aug 1992	A
5274274	Leman et al.	Dec 1993	A
5502412	Choi et al.	Mar 1996	A
5545955	Wood	Aug 1996	A
5808879	Liu et al.	Sep 1998	A
5828262	Rees	Oct 1998	A
6166971	Tamura et al.	Dec 2000	A
6211706	Choi et al.	Apr 2001	B1
6229342	Noble et al.	May 2001	B1
6304094	Gilliam	Oct 2001	B2
6307399	Lien et al.	Oct 2001	B1
6317000	Ivanov et al.	Nov 2001	B1
6353345	Yushan et al.	Mar 2002	B1
6365930	Schillaci et al.	Apr 2002	B1
6486714	Ushida et al.	Nov 2002	B2
6590914	Tanase et al.	Jul 2003	B1
6593622	Kinzer et al.	Jul 2003	B2
6605963	Kitamoto et al.	Aug 2003	B2
6614633	Kohno	Sep 2003	B1
6636024	Zametzky	Oct 2003	B2
7002398	Disney	Feb 2006	B2
7068486	Feldtkeller	Jun 2006	B2
7227763	Noh et al.	Jun 2007	B1
7254000	Smith et al.	Aug 2007	B1
7323912	Nielsen	Jan 2008	B2
7385375	Rozman	Jun 2008	B2
7436160	Rusu et al.	Oct 2008	B2
7619303	Bayan	Nov 2009	B2
7705476	Bayan et al.	Apr 2010	B2
7724046	Wendt et al.	May 2010	B2
7808222	Ueunten	Oct 2010	B2
7863877	Briere	Jan 2011	B2
7881029	Li et al.	Feb 2011	B1
7884583	Lenz et al.	Feb 2011	B2
7928950	Osame et al.	Apr 2011	B2
8044699	Kelly	Oct 2011	B1
8093373	Van Alstine et al.	Jan 2012	B2
8134400	Yamamoto	Mar 2012	B2
8138598	Shiraishi et al.	Mar 2012	B2
8144441	Ping et al.	Mar 2012	B2
8203380	Hashimoto et al.	Jun 2012	B2
8324934	Truong et al.	Dec 2012	B1
8574437	Bergstrom et al.	Nov 2013	B2
8593211	Forghani-Zadeh et al.	Nov 2013	B2
8638577	Shiraishi et al.	Jan 2014	B2
8659275	Bahramian	Feb 2014	B2
8742490	Disney	Jun 2014	B2
8754509	Grey	Jun 2014	B2
8823012	Lidow et al.	Sep 2014	B2
8970262	Weis et al.	Mar 2015	B2
9064722	Bedell et al.	Jun 2015	B2
9155980	Glad et al.	Oct 2015	B2
9225163	Cao et al.	Dec 2015	B2
9259729	Bergstrom et al.	Feb 2016	B2
9264022	Kihara	Feb 2016	B2
9276413	Zhang	Mar 2016	B1
9278297	Bergstrom et al.	Mar 2016	B2
9374858	Ni	Jun 2016	B2
9401612	Kinzer et al.	Jul 2016	B2
9413166	Rupp et al.	Aug 2016	B2
9525410	Kim et al.	Dec 2016	B2
9537338	Kinzer et al.	Jan 2017	B2
9570927	Kinzer et al.	Feb 2017	B2
9571093	Kinzer et al.	Feb 2017	B2
9577530	Ribarich et al.	Feb 2017	B1
9613891	Kinzer	Apr 2017	B2
9685869	Kinzer et al.	Jun 2017	B1
9712058	Newlin	Jul 2017	B1
9716395	Kinzer et al.	Jul 2017	B2
9722609	Kinzer et al.	Aug 2017	B2
9831867	Kinzer et al.	Nov 2017	B1
9859732	Kinzer et al.	Jan 2018	B2
9929652	Ribarich et al.	Mar 2018	B1
9960620	Kinzer et al.	May 2018	B2
9960764	Kinzer et al.	May 2018	B2
10084448	Godycki	Sep 2018	B2
10135275	Kinzer et al.	Nov 2018	B2
10170922	Kinzer et al.	Jan 2019	B1
10269687	Kinzer	Apr 2019	B2
10277048	Kinzer et al.	Apr 2019	B2
10305472	Kinzer et al.	May 2019	B1
10333327	Kinzer et al.	Jun 2019	B2
10396579	Kinzer et al.	Aug 2019	B2
10530169	Kinzer et al.	Jan 2020	B2
10536140	Ribarich et al.	Jan 2020	B1
10897142	Kinzer et al.	Jan 2021	B2
10910843	Kinzer et al.	Feb 2021	B2
10944270	Kinzer et al.	Mar 2021	B1
11404884	Kinzer et al.	Aug 2022	B2
11545838	Kinzer et al.	Jan 2023	B2
11605955	Kinzer et al.	Mar 2023	B2
20030067339	Yamamoto	Apr 2003	A1
20040182915	Bachman et al.	Sep 2004	A1
20050134533	Sasada et al.	Jun 2005	A1
20050151236	Oliver et al.	Jul 2005	A1
20050219017	Shirakawa	Oct 2005	A1
20050280141	Zhang	Dec 2005	A1
20060034107	West	Feb 2006	A1
20060256586	Ohshima et al.	Nov 2006	A1
20060256589	Choi	Nov 2006	A1
20060261862	Baszler et al.	Nov 2006	A1
20070063678	Yoshikawa	Mar 2007	A1
20070170465	Kwon et al.	Jul 2007	A1
20070285066	Lipcsei et al.	Dec 2007	A1
20080012542	Liu et al.	Jan 2008	A1
20080035959	Jiang	Feb 2008	A1
20080054979	Nagumo	Mar 2008	A1
20080062595	Ping et al.	Mar 2008	A1
20080136390	Briere	Jun 2008	A1
20080284482	Ishikawa	Nov 2008	A1
20090052216	Iwabuchi et al.	Feb 2009	A1
20090180304	Bahramian	Jul 2009	A1
20090256617	Ochi	Oct 2009	A1
20090284288	Zhang et al.	Nov 2009	A1
20100019279	Chen et al.	Jan 2010	A1
20100025730	Heikman et al.	Feb 2010	A1
20100060320	Lee	Mar 2010	A1
20100140660	Wu et al.	Jun 2010	A1
20100253296	Huang et al.	Oct 2010	A1
20100258842	Lidow et al.	Oct 2010	A1
20100264975	Scott	Oct 2010	A1
20100315163	Takagi et al.	Dec 2010	A1
20100315748	Kwong et al.	Dec 2010	A1
20110025397	Wang et al.	Feb 2011	A1
20110049526	Chu et al.	Mar 2011	A1
20110157949	Bahramian	Jun 2011	A1
20110204928	Umezaki et al.	Aug 2011	A1
20110212585	Huang et al.	Sep 2011	A1
20110215746	Ikoshi et al.	Sep 2011	A1
20110216563	Ribarich	Sep 2011	A1
20110284862	Zhang	Nov 2011	A1
20110292632	Wen et al.	Dec 2011	A1
20110316494	Kitamura et al.	Dec 2011	A1
20120126406	Dix	May 2012	A1
20120126765	Stone et al.	May 2012	A1
20120175631	Lidow et al.	Jul 2012	A1
20120220089	Imada et al.	Aug 2012	A1
20120274366	Briere	Nov 2012	A1
20120293231	Nishijima	Nov 2012	A1
20120319758	Kobayashi et al.	Dec 2012	A1
20130009674	Reese et al.	Jan 2013	A1
20130051113	Kwon	Feb 2013	A1
20130056744	Mishra et al.	Mar 2013	A1
20130063123	Liang	Mar 2013	A1
20130063195	Youssef	Mar 2013	A1
20130074907	Saunders	Mar 2013	A1
20130076322	Tateno et al.	Mar 2013	A1
20130099768	Yonezawa et al.	Apr 2013	A1
20130119393	Zhu et al.	May 2013	A1
20130146891	Xin et al.	Jun 2013	A1
20130162923	Umezaki	Jun 2013	A1
20130193485	Akiyama et al.	Aug 2013	A1
20130194003	Takayama et al.	Aug 2013	A1
20130200938	Yao et al.	Aug 2013	A1
20130240893	Bedell et al.	Sep 2013	A1
20130241520	Kim et al.	Sep 2013	A1
20130241621	Forghani-Zadeh et al.	Sep 2013	A1
20130248931	Saito et al.	Sep 2013	A1
20130249001	Willmeroth et al.	Sep 2013	A1
20130249017	Kwon	Sep 2013	A1
20130249602	Mauder et al.	Sep 2013	A1
20130265029	Akiyama	Oct 2013	A1
20130285470	Koyama et al.	Oct 2013	A1
20130343143	Jung	Dec 2013	A1
20140001479	Kudymov	Jan 2014	A1
20140015586	Hirler et al.	Jan 2014	A1
20140048810	Umezaki et al.	Feb 2014	A1
20140070627	Briere et al.	Mar 2014	A1
20140070786	Guerra et al.	Mar 2014	A1
20140091311	Jeon et al.	Apr 2014	A1
20140092637	Minoura et al.	Apr 2014	A1
20140092638	Nishimori et al.	Apr 2014	A1
20140167069	Vielemeyer et al.	Jun 2014	A1
20140175454	Roberts et al.	Jun 2014	A1
20140191281	Yamaji	Jul 2014	A1
20140225162	Briere	Aug 2014	A1
20140266389	Sadwick et al.	Sep 2014	A1
20140300413	Høyerby et al.	Oct 2014	A1
20140337603	Yamazaki et al.	Nov 2014	A1
20140346522	Disney et al.	Nov 2014	A1
20140347116	Kihara et al.	Nov 2014	A1
20140347905	Takizawa	Nov 2014	A1
20140353673	Ito et al.	Dec 2014	A1
20140361343	Sriram	Dec 2014	A1
20140375372	Ikeda	Dec 2014	A1
20150034957	Chiu et al.	Feb 2015	A1
20150042918	Kimura et al.	Feb 2015	A1
20150091539	Norling	Apr 2015	A1
20150130428	Lee et al.	May 2015	A1
20150137134	Shah et al.	May 2015	A1
20150137135	Green et al.	May 2015	A1
20150160678	Kadowaki et al.	Jun 2015	A1
20150162424	Briere	Jun 2015	A1
20150162832	Briere	Jun 2015	A1
20150188448	Perreault et al.	Jul 2015	A1
20150255547	Yuan et al.	Sep 2015	A1
20150256157	Kozuma	Sep 2015	A1
20150263001	Saito et al.	Sep 2015	A1
20150263620	Huang	Sep 2015	A1
20150311196	Hirler et al.	Oct 2015	A1
20150357422	Liao	Dec 2015	A1
20150358003	Kihara	Dec 2015	A1
20160013179	Miura	Jan 2016	A1
20160056282	Yamaji	Feb 2016	A1
20160065086	Zojer et al.	Mar 2016	A1
20160079785	Kinzer et al.	Mar 2016	A1
20160079844	Kinzer et al.	Mar 2016	A1
20160079853	Kinzer et al.	Mar 2016	A1
20160079854	Kinzer et al.	Mar 2016	A1
20160079964	Kinzer et al.	Mar 2016	A1
20160079975	Kinzer et al.	Mar 2016	A1
20160079978	Kinzer et al.	Mar 2016	A1
20160079979	Kinzer et al.	Mar 2016	A1
20160086881	Standing	Mar 2016	A1
20160086938	Kinzer	Mar 2016	A1
20160118894	Zhang et al.	Apr 2016	A1
20160141352	Sung	May 2016	A1
20160173096	Inoue et al.	Jun 2016	A1
20160173097	Inoue et al.	Jun 2016	A1
20160240471	Klowak et al.	Aug 2016	A1
20160247748	Kinzer	Aug 2016	A1
20160277008	Green et al.	Sep 2016	A1
20160277012	Abesingha et al.	Sep 2016	A1
20160307826	McKnight-MacNeil et al.	Oct 2016	A1
20160315033	Otremba et al.	Oct 2016	A1
20160322116	Jang et al.	Nov 2016	A1
20160336926	Kinzer et al.	Nov 2016	A1
20160372920	Kinzer et al.	Dec 2016	A1
20170025267	Chu et al.	Jan 2017	A1
20170093283	Leoncini et al.	Mar 2017	A1
20170155391	Kinzer et al.	Jun 2017	A1
20170162483	Kinzer	Jun 2017	A1
20170163258	Kinzer et al.	Jun 2017	A1
20170324263	Kinzer et al.	Nov 2017	A1
20180013422	Leong et al.	Jan 2018	A1
20180102661	Kinzer et al.	Apr 2018	A1
20180159529	Reusch et al.	Jun 2018	A1
20180205373	Hokazono et al.	Jul 2018	A1
20200044648	Sharma et al.	Feb 2020	A1
20200153338	Ribarich et al.	May 2020	A1

Foreign Referenced Citations (38)

Number	Date	Country
101572490	Nov 2009	CN
101621871	Jan 2010	CN
101572490	May 2012	CN
103872037	Jun 2014	CN
107005163	Aug 2017	CN
107005163	Sep 2018	CN
1120835	Aug 2001	EP
2763320	Aug 2014	EP
2244400	Nov 1991	GB
2000260451	Sep 2000	JP
2001308462	Nov 2001	JP
2013106027	May 2013	JP
I231094	Apr 2005	TW
I297503	Jun 2008	TW
I362749	Apr 2012	TW
201240294	Oct 2012	TW
I383587	Jan 2013	TW
201312909	Mar 2013	TW
201315150	Apr 2013	TW
201401775	Jan 2014	TW
201404038	Jan 2014	TW
201416818	May 2014	TW
201618276	May 2016	TW
201622327	Jun 2016	TW
201624669	Jul 2016	TW
201624924	Jul 2016	TW
201629665	Aug 2016	TW
201804277	Feb 2018	TW
I626822	Jun 2018	TW
I628780	Jul 2018	TW
I649969	Feb 2019	TW
I677779	Nov 2019	TW
I687050	Mar 2020	TW
2014171190	Oct 2014	WO
2016044474	Mar 2016	WO
2016044479	Mar 2016	WO
2016044480	Mar 2016	WO
2016044481	Mar 2016	WO

Non-Patent Literature Citations (125)

Entry
“100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs”, Texas Instruments, LM5113 5A, Available online at: http://www.ti.com/product/ lm5113, Apr. 2013, pp. 1-26.
“85V Half-Bridge MOSFET Drivers with Adaptive Dead Time and Shoot-Through Protection”, Micrel, Inc., Available online at: http://www.micrel.com/ index.php/products/power-management-ics/mosfet-drevers /half-bridge/article/7.html, Nov. 11, 2013, pp. 1-25.
“DA8801 Integrated 650V GaN Half Bridge Power IC”, Dialog Semiconductor, Available online at: http://www.dialogsemiconductor.com/products/da8801, Jan. 3, 2017, 6 pages.
“Dialog Semiconductor Enters Gallium Nitride (GaN) Market with First Integrated Devices Targeting Fast Charging Power Adapters (News with Additional Features)”, Business Wire, A Berkshire Hathaway Company, Available Online at http://www.businesswire.com/news/home/20160824006260/en/Dialog-Semiconductor-Ente, Aug. 25, 2016, 3 pages.
U.S. Appl. No. 14/667,319 , “Advisory Action”, dated Apr. 20, 2016, 4 pages.
U.S. Appl. No. 14/667,319 , “Advisory Action”, dated Jan. 9, 2017, 4 pages.
U.S. Appl. No. 14/667,319 , “Final Office Action”, dated Feb. 16, 2016, 9 pages.
U.S. Appl. No. 14/667,319 , “Final Office Action”, dated Sep. 15, 2016, 9 pages.
U.S. Appl. No. 14/667,319 , “First Action Interview Office Action Summary”, dated Dec. 14, 2015, 6 pages.
U.S. Appl. No. 14/667,319 , “First Action Interview Pilot Program Pre-Interview Commu”, dated Nov. 20, 2015, 4 pages.
U.S. Appl. No. 14/667,319 , “Non-Final Office Action”, dated Apr. 14, 2017, 10 pages.
U.S. Appl. No. 14/667,319 , “Non-Final Office Action”, dated Jul. 5, 2016, 8 pages.
U.S. Appl. No. 14/667,319 , “Notice of Allowance”, dated Aug. 25, 2017, 9 pages.
U.S. Appl. No. 14/667,319 , “Restriction Requirement”, dated Aug. 13, 2015, 6 pages.
U.S. Appl. No. 14/667,319 , “Supplemental Notice of Allowance”, dated Nov. 16, 2017, 6 pages.
U.S. Appl. No. 14/667,329 , “Advisory Action”, dated Apr. 14, 2016, 2 pages.
U.S. Appl. No. 14/667,329 , “Final Office Action”, dated Feb. 18, 2016, 11 pages.
U.S. Appl. No. 14/667,329 , “Final Office Action”, dated Sep. 28, 2016, 6 pages.
U.S. Appl. No. 14/667,329 , “Non-Final Office Action”, dated Aug. 17, 2016, 13 pages.
U.S. Appl. No. 14/667,329 , “Non-Final Office Action”, dated Jan. 5, 2016, 10 pages.
U.S. Appl. No. 14/667,329 , “Non-Final Office Action”, dated May 25, 2016, 11 pages.
U.S. Appl. No. 14/667,329 , “Notice of Allowance”, dated Nov. 1, 2016, 8 pages.
U.S. Appl. No. 14/667,515 , “Non-Final Office Action”, dated Jun. 29, 2017, 9 pages.
U.S. Appl. No. 14/667,515 , “Notice of Allowance”, dated Jan. 10, 2018, 9 pages.
U.S. Appl. No. 14/667,523 , “Corrected Notice of Allowability”, dated Jun. 22, 2016, 2 pages.
U.S. Appl. No. 14/667,523 , “Final Office Action”, dated Feb. 9, 2016, 7 pages.
U.S. Appl. No. 14/667,523 , “Non-Final Office Action”, dated Jul. 30, 2015, 20 pages.
U.S. Appl. No. 14/667,523 , “Notice of Allowance”, dated Mar. 10, 2016, 8 pages.
U.S. Appl. No. 14/667,531 , “Advisory Action”, dated Jul. 14, 2016, 3 pages.
U.S. Appl. No. 14/667,531 , “Final Office Action”, dated Jun. 9, 2016, 22 pages.
U.S. Appl. No. 14/667,531 , “Final Office Action”, dated Nov. 29, 2016, 32 pages.
U.S. Appl. No. 14/667,531 , “Non-Final Office Action”, dated Apr. 1, 2016, 18 pages.
U.S. Appl. No. 14/667,531 , “Non-Final Office Action”, dated Sep. 1, 2016, 30 pages.
U.S. Appl. No. 14/667,531 , “Notice of Allowance”, dated Apr. 7, 2017, 3 pages.
U.S. Appl. No. 14/667,531 , “Notice of Allowance”, dated Jan. 23, 2017, 10 pages.
U.S. Appl. No. 14/728,874 , “Non-Final Office Action”, dated Aug. 26, 2016, 12 pages.
U.S. Appl. No. 14/728,874 , “Notice of Allowance”, dated Nov. 16, 2016, 8 pages.
U.S. Appl. No. 14/737,259 , “First Action Interview Pilot Program Pre-Interview Communication”, dated Mar. 14, 2017, 4 pages.
U.S. Appl. No. 14/737,259 , “Notice of Allowance”, dated Apr. 17, 2017, 16 pages.
U.S. Appl. No. 14/743,815 , “Non Final Office Action”, dated Feb. 7, 2017, 18 pages.
U.S. Appl. No. 14/857,497 , “Non-Final Office Action”, dated Feb. 9, 2017, 30 pages.
U.S. Appl. No. 14/857,497 , “Restriction Requirement”, dated Sep. 28, 2016, 6 pages.
U.S. Appl. No. 14/877,574 , “Notice of Allowance”, dated Dec. 14, 2016, 13 pages.
U.S. Appl. No. 14/968,688 , “Notice of Allowance”, dated Jan. 18, 2017, 11 pages.
U.S. Appl. No. 14/968,688 , “Restriction Requirement”, dated Sep. 23, 2016, 6 pages.
U.S. Appl. No. 15/219,248 , “Corrected Notice of Allowability”, dated Oct. 17, 2018, 2 pages.
U.S. Appl. No. 15/219,248 , “Corrected Notice of Allowability”, dated Sep. 26, 2018, 2 pages.
U.S. Appl. No. 15/219,248 , “Non-Final Office Action”, dated Jan. 25, 2018, 9 pages.
U.S. Appl. No. 15/219,248 , “Notice of Allowance”, dated Aug. 15, 2018, 8 pages.
U.S. Appl. No. 15/219,248 , “Restriction Requirement”, dated Nov. 1, 2017, 6 pages.
U.S. Appl. No. 15/360,123, “Corrected Notice of Allowability”, dated May 22, 2017, 6 pages.
U.S. Appl. No. 15/360,123, “Notice of Allowance”, dated Feb. 7, 2017, 13 pages.
U.S. Appl. No. 15/431,632, “Notice of Allowance”, dated Apr. 7, 2017, 7 pages.
U.S. Appl. No. 15/431,641, “Non-Final Office Action”, dated Aug. 30, 2017, 26 pages.
U.S. Appl. No. 15/431,641, “Notice of Allowance”, dated Nov. 20, 2017, 12 pages.
U.S. Appl. No. 15/431,641, “Supplemental Notice of Allowance”, dated Apr. 5, 2018, 2 pages.
U.S. Appl. No. 15/431,641, “Supplemental Notice of Allowance”, dated Dec. 4, 2017, 2 pages.
U.S. Appl. No. 15/431,641, “Supplemental Notice of Allowance”, dated Feb. 23, 2018, 2 pages.
U.S. Appl. No. 15/431,641, “Supplemental Notice of Allowance”, dated Jan. 11, 2018, 2 pages.
U.S. Appl. No. 15/434,956, “Non-Final Office Action”, dated Sep. 20, 2018, 9 pages.
U.S. Appl. No. 15/434,956, “Notice of Allowance”, dated Jan. 17, 2019, 9 pages.
U.S. Appl. No. 15/434,956, “Restriction Requirement”, dated May 17, 2018, 6 pages.
U.S. Appl. No. 15/439,785, “Notice of Allowance”, dated Oct. 12, 2017, 9 pages.
U.S. Appl. No. 15/439,785, “Restriction Requirement”, dated Jul. 31, 2017, 9 pages.
U.S. Appl. No. 15/658,242, “Non-Final Office Action”, dated Oct. 4, 2018, 13 pages.
U.S. Appl. No. 15/658,242, “Notice of Allowance”, dated Apr. 17, 2019, 8 pages.
U.S. Appl. No. 15/838,026, “First Action Interview Office Action Summary”, dated Jun. 4, 2018, 6 pages.
U.S. Appl. No. 15/838,026, “First Action Interview Pilot Program Pre-Interview Communication”, dated Mar. 30, 2018, 4 pages.
U.S. Appl. No. 15/838,026, “Notice of Allowance”, dated Nov. 28, 2018, 9 pages.
U.S. Appl. No. 15/903,398, “First Action Interview Pilot Program Pre-Interview Communication”, dated Jun. 4, 2018, 5 pages.
U.S. Appl. No. 15/903,398, “Notice of Allowance”, dated Aug. 15, 2018, 19 pages.
U.S. Appl. No. 15/961,723, “Non-Final Office Action”, dated Oct. 4, 2018, 10 pages.
U.S. Appl. No. 15/961,723, “Notice of Allowance”, dated Apr. 3, 2019, 10 pages.
U.S. Appl. No. 15/961,723, “Notice of Allowance”, dated Feb. 14, 2019, 8 pages.
U.S. Appl. No. 15/961,781, “Non-Final Office Action”, dated Oct. 1, 2018, 39 pages.
U.S. Appl. No. 15/961,781, “Notice of Allowance”, dated Jan. 25, 2019, 9 pages.
U.S. Appl. No. 15/961,781, “Supplemental Notice of Allowability”, dated Apr. 12, 2019, 3 pages.
U.S. Appl. No. 16/151,695, “Non-Final Office Action”, dated Jul. 25, 2019, 7 pages.
U.S. Appl. No. 16/151,695, “Notice of Allowance”, dated Aug. 22, 2019, 9 pages.
U.S. Appl. No. 16/212,370, “Corrected Notice of Allowability”, dated Jan. 14, 2021, 2 pages.
U.S. Appl. No. 16/212,370, “Final Office Action”, dated Jun. 18, 2020, 12 pages.
U.S. Appl. No. 16/212,370, “Non-Final Office Action”, dated Jan. 7, 2020, 12 pages.
U.S. Appl. No. 16/212,370, “Notice of Allowance”, dated Nov. 12, 2020, 8 pages.
U.S. Appl. No. 16/447,922, “Notice of Allowance”, dated Sep. 18, 2020, 9 pages.
U.S. Appl. No. 16/550,272, “Corrected Notice of Allowability”, Nov. 4, 2020, 2 pages.
U.S. Appl. No. 16/550,272, “Ex-parte Quayle Action”, Jul. 20, 2020, 7 pages.
U.S. Appl. No. 16/550,272, “First Action Interview Pilot Program Pre-Interview Communication”, dated Apr. 17, 2020, 3 pages.
U.S. Appl. No. 16/550,272, “Notice of Allowance”, dated Sep. 29, 2020, 8 pages.
U.S. Appl. No. 16/699,081, “First Action Interview Office Action Summary”, dated Jan. 20, 2022, 4 pages.
U.S. Appl. No. 16/699,081, “First Action Interview Pilot Program Pre-Interview Communication”, dated Oct. 26, 2021, 4 pages.
U.S. Appl. No. 16/699,081, “Notice of Allowance”, dated Mar. 31, 2022, 8 pages.
U.S. Appl. No. 17/811,797, “Final Office Action”, dated May 25, 2023, 13 pages.
U.S. Appl. No. 17/811,797, “Non-Final Office Action”, dated Feb. 2, 2023, 17 pages.
U.S. Appl. No. 17/820,538, “Advisory Action”, dated May 19, 2023, 3 pages.
U.S. Appl. No. 17/820,538, “Final Office Action”, dated Mar. 9, 2023, 15 pages.
U.S. Appl. No. 17/820,538, “Non-Final Office Action”, dated Dec. 2, 2022, 11 pages.
U.S. Appl. No. 17/820,538, “Non-Final Office Action”, dated Jun. 15, 2023, 11 pages.
U.S. Appl. No. 17/820,829, “Notice of Allowance”, dated Nov. 10, 2022, 10 pages.
U.S. Appl. No. 17/820,834, “Notice of Allowance”, dated Jan. 23, 2023, 8 pages.
U.S. Appl. No. 17/820,834, “Notice of Allowance”, dated Dec. 13, 2022, 9 pages.
U.S. Appl. No. 18/064,209, “Non-Final Office Action”, dated Apr. 13, 2023, 16 pages.
CN201580049750.0, “Notice of Decision to Grant”, dated Jun. 6, 2018, 2 pages.
CN201580049750.0, “Office Action”, dated Dec. 18, 2017, 9 pages.
PCT/US2015/050510, “International Preliminary Report on Patentability”, dated Mar. 30, 2017, 6 pages.
PCT/US2015/050510, “International Search Report and Written Opinion”, dated Jan. 14, 2016, 7 pages.
PCT/US2015/050516, “International Preliminary Report on Patentability”, dated Mar. 30, 2017, 10 pages.
PCT/US2015/050516, “International Search Report and Written”, dated Dec. 28, 2015, 11 pages.
PCT/US2015/050517, “International Preliminary Report on Patentability”, dated Mar. 30, 2017, 8 pages.
PCT/US2015/050517, “International Search Report and Written Opinion”, dated Dec. 24, 2015, 9 pages.
PCT/US2015/050519, “International Preliminary Report on Patentability”, dated Mar. 30, 2017, 9 pages.
PCT/US2015/050519, “International Search Report and Written Opinion”, dated Dec. 23, 2015, 10 pages.
Tw104130652, “Notice of Decision to Grant”, dated Feb. 22, 2018, 3 pages.
Tw104130652, “Office Action”, dated Oct. 30, 2017, 3 pages.
Tw104130660, “Notice of Decision to Grant”, dated Oct. 5, 2017, 6 pages.
Tw104130694, “Notice of Decision to Grant”, dated Oct. 30, 2018, 3 pages.
Tw104130694, “Office Action”, dated Apr. 18, 2018, 7 pages.
Tw104130695, “Notice of Decision to Grant”, dated Mar. 2, 2018, 3 pages.
Tw104130695, “Office Action”, dated Dec. 6, 2017, 3 pages.
Tw106138274, “Notice of Decision to Grant”, dated Jul. 22, 2019, 4 pages.
Tw106138274, “Office Action”, dated Oct. 3, 2018, 5 pages.
Tw107143302, “Notice of Decision to Grant”, dated Jul. 26, 2019, 3 pages.
Tw107143302, “Office Action”, dated Mar. 25, 2019, 3 pages.
Tw108130019, “Notice of Decision to Grant”, dated Oct. 8, 2020, 3 pages.
Tw108130019, “Office Action”, dated Jan. 14, 2020, 11 pages.
Tw108130889, “Notice of Decision to Grant”, dated Oct. 28, 2019, 5 pages.

Related Publications (1)

	Number	Date	Country
	20220393479 A1	Dec 2022	US

Provisional Applications (2)

	Number	Date	Country
	62127725	Mar 2015	US
	62051160	Sep 2014	US

Divisions (2)

	Number	Date	Country
Parent	16151695	Oct 2018	US
Child	16699081		US
Parent	15219248	Jul 2016	US
Child	16151695		US

Continuations (3)

	Number	Date	Country
Parent	17811797	Jul 2022	US
Child	17819608		US
Parent	16699081	Nov 2019	US
Child	17811797		US
Parent	14667523	Mar 2015	US
Child	15219248		US

Half-bridge circuit using flip-chip GaN power devices

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