BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a sectional view showing in enlargement a bonding area between a semiconductor chip and a heat spreader of a semiconductor package according to a first embodiment;
FIG. 2 is a sectional view showing in enlargement the bonding area between the semiconductor chip and the heat spreader of the semiconductor package according to a second embodiment;
FIG. 3 is a sectional view showing in enlargement the bonding area between the semiconductor chip and the heat spreader of the semiconductor package according to a third embodiment;
FIG. 4 is a sectional view showing in enlargement the bonding area between the semiconductor chip and the heat spreader of the semiconductor package according to a fourth embodiment;
FIG. 5 is a view illustrating a semiconductor package in section according to the prior art;
FIG. 6 is a sectional view showing a state where the semiconductor package according to the prior art is heated;
FIG. 7 is a sectional view showing in enlargement the bonding area between the semiconductor chip and the heat spreader of the semiconductor package according to the prior art;
FIG. 8 is a view showing an analysis model used for analyzing in simulation a thermal stress occurred in the semiconductor package;
FIG. 9 is a table showing conditions in a simulation analysis model manufacturing step;
FIG. 10 is a table showing conditions of the respective simulation analysis models;
FIG. 11 is an equipressure contour representing a stress distribution of a tensile stress in a Z-axis direction, which occurs in a heat conductive bonding material;
FIG. 12 is a graph showing a stress distribution map that is plotted along an axis of Y═X;
FIG. 13 is a graph showing the stress distribution map that is plotted along an axis of Y=0;
FIG. 14 is a graph showing the maximum stress occurred in each analysis model; and
FIG. 15 is a table showing a result of a reliability test of an actual semiconductor package according to the first embodiment.