BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a sectional view showing a main portion of an embodiment of an interposer according to this invention;
FIG. 2 is a sectional view showing a main portion of another interposer according to this invention;
FIG. 3 is a sectional view showing an actual arrangement of the interposer; and
FIG. 4 is a sectional view showing an actual arrangement of the another interposer.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of novel interposers and electronic devices using the interposers according to the present invention will be explained below in detail with reference to the accompanying drawings. It should be understood that the embodiments are only exemplified and the present invention is not limited thereto. Also, note that, in the drawings, the same components are denoted by the same reference numerals to omit duplicate explanation.
[Interposer]
FIG. 1 is a sectional view showing an embodiment of a main portion of an interposer 10 according to this invention. The main portion of the interposer 10 includes through-hole conductors 20-1, 20-2, 20-3 formed on a silicon substrate 12, lower electrodes 18 formed on a surface of the silicon substrate 12, a dielectric layer 16 formed on the lower electrodes 18, and upper electrodes 14 formed on the dielectric layer 16.
When the surface of the silicon substrate 12 is properly polished, it has such a property that the surface is very flat and smooth. Alternatively a glass substrate and a polyimide substrate may be used in place of the silicon substrate when they satisfy the level of a surface flatness required in this embodiment.
The through-hole conductors 20-1 of the through-hole conductors 20 formed on the silicon substrate 12 are conductors for signal supply and transmit a signal between a semiconductor chip (not shown) and a package substrate (not shown) as described later. The through-hole conductors 20-2 are conductors for power supply, and the land portions of the through-hole conductors 20-2 extend to form, for example, the lower broad electrodes 18. The through-hole conductors 20-3 are conductors for ground (GND), and the land portions of the through-hole conductors 20-3 extend to form, for example, the upper broad electrodes 14.
Alternatively, the upper electrodes 14 may be formed as the land portions of the through-hole conductors 20-2 for power supply, while the lower electrodes 18 may be formed as the land portions of the through-hole conductors 20-3 for GND.
The upper and lower electrodes 14, 18 each are formed of an appropriate metal. In this embodiment the upper electrodes 14 are formed of, for example, nickel (Ni), and the lower electrodes 18 are formed of, for examples, platinum (Pt), for convenience of production. However, they may be formed of other metals.
The dielectric layer 16 is preferably composed of a high dielectric substance, for example, barium titanate (BaTiO3) having ferroelectricity.
Here, the upper electrodes 14 (the land portions of the through-hole conductors 20-3 for GND), the dielectric layer 16, and the lower electrodes 18 (or the land portions of the through-hole conductors 20-2 for power supply) form capacitors 15.
As described later, the interposer 10 shown in FIG. 1 is interposed between a semiconductor chip (not shown) and a package substrate (also referred to as a “mounting substrate”) (not shown). The interposer 10 is located very near to the semiconductor chip and functions as a decoupling capacitor between a power supply and the ground to absorb noise.
A features of the interposer 10 shown in FIG. 1 are that only the through-hole conductors 20 and the dielectric layer 16 are formed on the silicon substrate 12 and that the land portions of the through-hole conductors 20 form the upper or lower electrodes 14, 18. In other words, a wiring pattern that occupies the surface area of the silicon substrate 12 does not exist in the interposer 10 shown in FIG. 1. Accordingly, the electrodes 14, 18 of the capacitors can be spread out on the surface of the silicon substrate 12 to have a large area.
Further, since the silicon substrate 12 used for the interposer 10 shown in FIG. 1 has a very flat and smooth surface, the dielectric layer 16 can be formed very thin since the gap between the upper electrode 14 and the lower electrode 18 can be formed very narrow.
Further, a barium titanate (BaTIO3) layer being of ferroelectricity can be employed as the dielectric layer 16 used for the interposer 10 shown in FIG. 1.
The interposer 10 shown in FIG. 1 can form a capacitor (condenser) having a very large capacity by employing at least one of above described factors.
FIG. 2 is a sectional view showing another embodiment of main portion of an interposer according to this invention. On the main portion of the interposer shown in FIG. 1, the capacitors 15 are formed in that the through-hole conductors 20-2 for power supply and the through-hole conductors 20-3 for ground are disposed on a central portion of the surface of the silicon substrate 12 and that these through-hole conductors 20-2, 20-3 are surrounded by the through-hole conductors 20-1 for signal supply disposed on a peripheral region of the surface of the silicon substrate 12. In contrast, the main portion of the interposer shown in FIG. 2 is different from that shown in FIG. 1 in that the through-hole conductors 20-2 for power supply and the through-hole conductors 20-3 for ground are disposed on the peripheral region of the surface of the silicon substrate 12 and the through-hole conductors 20-1 for signal are disposed to a central portion surrounded by these through-hole conductors 20-2, 20-3.
As shown in FIG. 2, the land portions of the through-hole conductors 20-2 for power supply extend to form the broad upper electrodes 14 and are insulated from the lower electrodes 18 by gap 16. The through-hole conductors 20-1 for signal are insulated from the upper electrodes 14 by clearances 24 and are insulated from the lower electrodes 18 by the clearances 26. The land portions of the through-hole conductors 20-3 extend to form the lower electrodes 18.
Alternatively, the through-hole conductors 20-1, the through-hole conductors 20-2, and the through-hole conductors 20-3 may be disposed in mixture.
FIG. 3 is a sectional view showing an actual arrangement of the interposer 10. The interposer 10 is interposed between an IC chip (IC) 40 and a package substrate (PK) 42 and is connected to the IC chip 40 through solder bumps 26 and to the package substrate 42 through solder bumps 30, respectively, by soldering.
In addition to the upper electrodes 14, the dielectric layer 16, the lower electrodes 18, the silicon substrate 12, and the through-hole conductors 20 explained in relation to FIGS. 1 and 2, the interposer 10 shown in FIG. 3 includes an insulating resin layer 21 formed on the upper electrodes 14, nickel (Ni) lands 24-1 connected to the through-hole conductor through openings of the insulating resin layer 21, gold (Au) plated layers 24-2 overlaying the nickel lands 24-1, the solder bumps 26 formed on the gold plated layers 24-2, a solder resist layer 28 formed on the lower surface of the silicon substrate 12, and the solder bumps 30 formed on land portions of the through-hole conductors 20 through openings of the solder resist layer 28.
The interposer 10 shown in FIG. 3 possesses the same function and features as those of the interposer explained in relation to FIGS. 1 and 2. That is, the interposer 10 is located very near to the semiconductor chip 40 so that it absorbs noise by functioning as a decoupling capacitor between a power supply and the ground. The feature of the interposer 10 resides in the facts that: (1) since these exists no a wiring pattern that occupies the surface of the silicon substrate 12, the electrodes 14, 18 for capacitor (condenser) having large areas can be formed; (2) since the surface of the silicon substrate 12 is very flat and smooth, the gap between the upper electrodes 14 and the lower electrodes 18 can be narrowed; and (3) since ferroelectric dielectric substance can be employed for the dielectric layer 16, the capacitor (condenser) having the greatly large capacity can be formed.
FIG. 4 is a sectional view showing an actual arrangement of another interposer 10. The arrangement of the interposer 10 shown in FIG. 4 is different from that of FIG. 3 in that wiring layers 23-1, 23-2 are added.
In addition to the upper electrodes 14, the dielectric layer 16, the lower electrodes 18, the silicon substrate 12, the through-hole conductors 20, the solder bumps 26, the solder resist layer 28, and the solder bumps 30 explained in relation to FIG. 3, the interposer 10 shown in FIG. 4 includes a lower interlayer insulating resin layer 21-1 on which the land portions of the through-hole conductor or the wiring patterns 23-1 are formed, and an upper interlayer insulating resin layer 21-2 on which the land portion of the through hole conductor portions or the wiring patterns 23-2 are formed.
However, the wiring patterns 23-1, 23-2 are formed on the layers different from those of the capacitors 15 (i.e. on the interlayer insulating resin layers 21-1, 21-2). That is, since no wiring pattern exists in the capacitors 15 formed by the upper electrodes 14, the dielectric layer 16, and the lower electrodes 18, capacitor electrodes having a large area can be still formed.
Accordingly, the interposer 10 shown in FIG. 4 possesses the same function and features as those of the interposer explained in relation to FIGS. 1 and 3. That is, the function of the interposer 10 shown in FIG. 4 is such that it is located very near to the semiconductor chip 40 to function as a decoupling capacitor between a power supply and the ground to absorb noise. The features of the interposer 10 are as follows: Since no wiring pattern exists in the portions of the capacitors 15, the electrodes for capacitors having a large area can be formed. Since the surface of the silicon substrate 12 is very flat and smooth, the space between the upper electrodes 14 and the lower electrodes 18 can be made very narrow. Since a ferroelectric substance can be utilized for the dielectric layer 16, the capacitor (condenser) having the greatly large capacity can be formed.
(Manufacturing Method)
Although a method of manufacturing the interposers 10 shown in FIGS. 2 and 3 is not shown, they can be manufactured as described, for example, below. First, the silicon substrate 12 is prepared, the lower electrodes 18 are then formed by patterning on the silicon substrate 12, the dielectric layer 16 is then formed on the lower electrode by sputtering and the like while controlling its thickness, and further the upper electrodes 14 are formed on the dielectric layer by patterning. When desired, the lower and upper interlayer insulating resin layers 21-1, 21-2 may be formed to form wiring layers. They are formed by a known buildup method. Further, openings are formed from the back surface of the silicon substrate 12, and the through-hole conductors 20 are formed. When desired, solder resists 28, 38 may be formed by, for example, a screen printing.
[Electronic Device Using Interposer]
The interposer 10 shown in FIG. 2 is interposed between the IC chip 40 and the package substrate 42, and is connected to the both to form electronic device 70 that is composed of a combination of the semiconductor chip, the interposer, and the package substrate.
After the interposer 10 is manufactured, the electronic device 70 is formed by subjecting the solder bumps 26, 30 to reflow and connecting the interposer 10 to the semiconductor chip 40 and the package substrate 42, respectively, by soldering. The interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as the decoupling capacitor having a large capacity.
The interposer 10 shown in FIG. 3 is interposed between the IC chip 40 and the package substrate 42 to be connected to each other, and forms electronic device 70 that is composed of a combination of the semiconductor chip, the interposer, and the package substrate. After the interposer 10 is manufactured, the electronic device 70 is formed by reflowing the solder bumps 26, 30 to connect the interposer 10 to the IC chip 40 and the package substrate 42, respectively, by soldering. The interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as a decoupling capacitor having a large capacity. Further, the interposer 10 shown in FIG. 4 also provides the wiring layers 23-1, 23-2 between the IC chip 40 and the package substrate 42.
Features, Advantages, and the Like of the Embodiments
The interposers 10 according to the embodiments possess the following features and advantages.
(1) Because of no wiring pattern that occupies the surface of the silicon substrate 12, the electrodes for capacitor having a large area can be formed.
(2) Since the silicon substrate 12 has very flat and smooth surface, the dielectric layer 16 can be formed very thin, whereby the space between the upper electrodes 14 and the lower electrodes 18 can be formed very narrow.
(3) A ferroelectric material, for example, barium titanate (BaTiO3), can be used for the dielectric layer 16 of the interposer 10.
(4) The interposer 10 can provide capacitors (condenser) having a very large capacity by employing at least one of the above factors.
The electronic devices according to the embodiments has the following features and advantages.
(1) Noise can be absorbed by providing a decoupling capacitor having large capacity that is connected between the power supply and the ground at a position very near the semiconductor chip 40 in the devices composing the combination of the semiconductor chip 40, the interposer 10, and the package substrate 42.
(2) The wiring layers 23-1, 23-2 can be also provided by using the interposer 10 explained in relation to FIG. 4 while providing the decoupling capacitor having the large capacity at the position very near the semiconductor chip 40.
[Others]
The embodiments of the interposers and the electronic devices making use of the interposers according to the present invention have been explained above. It should be noted that they are only examples, and the present invention is not limited thereto.
The technical scope of the present invention should be determined according to the description of the accompanying claims.
Patent Application
20080017407
