Patent Application
20240282709
Embodiments of the present disclosure generally relate to semiconductor manufacturing processes, more particularly, to processes to produce layered semiconductor substrates.
Ruthenium (Ru) metal is useful in various layered substrate devices, such as DRAM devices. The inventors have observed, however, that Ru processing techniques can undesirably lead to several integration issues, such as high line edge roughness (LER) and/or bitline rounding. Accordingly, the inventors have provided improved methods for producing Ru films on devices.
Methods for producing a layered substate are provided herein. In embodiments, a method to produce a layered substrate, comprises depositing a ruthenium layer having a first average grain size on a substrate; annealing the substrate at a temperature and for a period of time sufficient to produce an annealed ruthenium layer having a second average grain size which is greater than the first average grain size; removing a portion of the annealed ruthenium layer by chemical mechanical planarization to form a planarized ruthenium layer, to produce the layered substrate.
In other embodiments, a layered substrate comprises a base substrate; a diffusion barrier layer disposed over the base substrate; and a ruthenium layer having a root mean square roughness of less than or equal to about 1 nm disposed over the diffusion barrier layer, wherein a ratio of an average grain size of the ruthenium layer in nanometers divided by a thickness of the ruthenium layer in nanometers, is greater than or equal to about 20.
Other and further embodiments of the present disclosure are described below.
Embodiments of the present disclosure, briefly summarized above and discussed in greater detail below, can be understood by reference to the illustrative embodiments of the disclosure depicted in the appended drawings. However, the appended drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of scope, for the disclosure may admit to other equally effective embodiments.
FIG. 2A1 depicts a block diagram of a partially completed or intermediate layered substrate according to embodiments disclosed herein.
FIG. 2A2 depicts a block diagram of a partially completed or intermediate layered substrate after annealing according to embodiments disclosed herein.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
In embodiments, a method to produce a layered substrate comprises depositing a ruthenium layer having a first average grain size on a substrate; annealing the substrate at a temperature and for a period of time sufficient to produce an annealed ruthenium layer having a second average grain size which is greater than the first average grain size; removing a portion of the annealed ruthenium layer by chemical mechanical planarization to form a planarized ruthenium layer, to produce the layered substrate.
In embodiments, the method further comprises depositing a capping layer comprising silicon nitride (SiN) over the planarized ruthenium layer. In embodiments, the ruthenium layer is deposited by physical vapor deposition.
In embodiments, the ruthenium layer is deposited over a diffusion barrier layer comprising at least one of titanium nitride TiaNx, tantalum nitride, TaaNx, zirconium nitride ZraNx, wherein each a is independently from 1 to 3 and x is from 1 to 5 to result in a neutral compound; or titanium zirconium nitride TicZraNx, wherein c+d equals an integer from 1 to 3 and x is from 1 to 5 to result in a neutral compound. In embodiments, the ruthenium layer is deposited over a molybdenum metal layer.
In embodiments of the method, a thickness of the planarized ruthenium layer is greater than or equal to about 50% of the ruthenium layer prior to the chemical mechanical planarization.
In embodiments, the annealing the substrate is at a temperature of greater than or equal to about 800° C. In embodiments, a ratio of the second average grain size of the planarized ruthenium layer in nanometers divided by a thickness of the planarized ruthenium layer in nanometers is greater than or equal to about 20. In embodiments, a maximum grain size of the planarized ruthenium layer is greater than or equal to about 200 nm. In embodiments, a root mean square roughness of the planarized ruthenium layer is less than or equal to about 1 nm.
In embodiments, a root mean square roughness of the planarized ruthenium layer is less than or equal to about 90% of a root mean square roughness of the ruthenium layer prior to planarization. In embodiments, a surface resistivity of the planarized ruthenium layer is less than or equal to about 90% of a surface resistivity of the ruthenium layer prior to annealing.
In embodiments, a layered substrate comprises a base substrate; a diffusion barrier layer disposed over the base substrate; and a ruthenium layer having a root mean square roughness of less than or equal to about 1 nm disposed over the diffusion barrier layer, wherein a ratio of an average grain size of the ruthenium layer in nanometers divided by a thickness of the ruthenium layer in nanometers, is greater than or equal to about 20.
In embodiments, the ruthenium layer has a maximum grain size of greater than or equal to about 200 nm. In embodiments, the layered substrate further comprises a capping layer disposed over the ruthenium layer. In embodiments, the capping layer comprises silicon nitride (SiN). In embodiments, the layered substrate further comprises a molybdenum layer disposed between the diffusion barrier layer and the ruthenium layer. In embodiments, the diffusion barrier layer comprises one or more of titanium nitride TiaNx, tantalum nitride, TaaNx, zirconium nitride ZraNx, wherein each a is independently from 1 to 3 and x is from 1 to 5 to result in a neutral compound; or titanium zirconium nitride TicZraNx, wherein c+d equals an integer from 1 to 3 and x is from 1 to 5 to result in a neutral compound.
In embodiments, the base substrate is Si. In embodiments, the base substrate comprises SiO2.
As used herein, the terms “on”, “over”, “above,” “below,” and “between” as used herein refer to a relative position of one layer with respect to other layers. As such, one layer deposited or disposed on, over, above or below another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a layer disposed in contact with another layer refers to the two layers being in direct contact with each other.
As shown in
Although
As shown in
In embodiments, a diffusion barrier layer 204 is disposed over the base substrate, which in embodiments may be disposed in contact with the base substrate 202. In embodiments, the diffusion barrier layer 204 may further enhance the adherence of a metal layer disposed upon the diffusion barrier layer 204.
In embodiments, the diffusion barrier layer 204 comprises a nitride, which in embodiments is one or more of titanium nitride TiaNx, tantalum nitride, TaaNx, zirconium nitride ZraNx, wherein each a is independently from 1 to 3 and x is from 1 to 5 to result in a neutral compound; or titanium zirconium nitride TicZraNx, wherein c+d equals an integer from 1 to 3 and x is from 1 to 5 to result in a neutral compound.
In embodiments the nitride layer is deposited using reactive physical vapor deposition, e.g., by sputtering a titanium or tantalum target in a nitrogen/argon plasma. The diffusion barrier layer is configured to limit the diffusion of the underlayer and/or the ruthenium layer into the semiconductor substrate and the dielectric layer, thereby dramatically increasing the reliability of the connection. In embodiments, the diffusion barrier layer has a thickness greater than or equal to about 5 Å, or greater than or equal to about 50 Å, or greater than or equal to about 100 Å, or greater than or equal to about 150 Å, and less than or equal to about 1000 Å, or less than or equal to about 500 Å, or less than or equal to about 200 Å.
In some embodiments, the diffusion barrier layer further comprises an amount of the base substrate, e.g., the diffusion barrier layer is doped with the material utilized in the base substrate in an amount effective to increase or facilitate adhesion between the diffusion barrier layer and the base substrate. In some embodiments, diffusion barrier layer further comprises less than or equal to about 1 weight percent of the material present in the base substrate material, or less than or equal to about 0.1 weight percent of the base substrate material, or less than or equal to about 0.01 weight percent of the base substrate material, based on the total amount of diffusion barrier layer present.
In embodiments, as shown in
As shown in FIG. 2A1, in embodiments, an intermediate layered substrate 200a is formed into the layered substrate 200 (see
The deposited ruthenium layer 210, when deposited, e.g., via physical vapor deposition, has a first average grain size, which is determined on the surface 218 of the intermediate layered substrate 200a, of the deposited ruthenium layer 210 before annealing. The first average grain size is enlarged to a second average grain size during annealing to form the annealed ruthenium layer 211 shown in FIG. 2A2. The annealed intermediate layered substrate 200b is then subjected to chemical mechanical planarization to form the planarized ruthenium layer 208, having a second average grain size which is determined on an upper surface 220 of the planarized ruthenium layer 208 of the layered substrate 200 (see
The inventors have observed that larger grain size in the ruthenium layer after annealing has benefits which include reduced surface resistivity and enhanced stability. However, the inventors have observed that the grain size formed by annealing of the ruthenium layer also depends on the thickness of the ruthenium layer. The larger grain sizes are only formed during the annealing process in ruthenium layers which are thicker than desired for various end uses. Ruthenium grain growth during the annealing has also been observed to cause other integration issues, such as increased roughness, bitline rounding, and the like.
The inventors have observed that after the deposited ruthenium layer 210 is deposited at a first thickness 206, and then subject to annealing to form the annealed ruthenium layer 211 to increase the grain size of the deposited ruthenium layer 210 from of first average grain size to a second average grain size, the annealing results in the annealed ruthenium layer 211 having a surface roughness which may be problematic. The addition of a CMP procedure to the annealed ruthenium layer 211 to form the planarized ruthenium layer 208 having a reduced final thickness 212, significantly reduces the roughness of the planarized ruthenium layer 208 and improves the surface resistivity of the planarized ruthenium layer 208, relative to the deposited ruthenium layer 210 prior to annealing.
In embodiments, the deposited ruthenium layer 210 is deposited at a thickness of greater than or equal to about 10 nm, or greater than or equal to about 15 nm, or greater than or equal to about 20 nm, or greater than or equal to about 25 nm, or greater than or equal to about 30 nm. The deposited ruthenium layer 210 is then annealed as described herein to form the annealed ruthenium layer 211, which is then subjected to CMP such that an amount of the annealed ruthenium layer 211 is removed, i.e., a removed thickness 214, to produce the planarized ruthenium layer 208 having a final thickness 212 after planarization.
In embodiments, the final thickness 212 of the planarized ruthenium layer 208 is greater than or equal to about 50%, or greater than or equal to about 60%, or greater than or equal to about 70%, or greater than or equal to about 80%, or greater than or equal to about 90% of the first thickness 206 of the deposited ruthenium layer 210 (after annealing), prior to the chemical mechanical planarization.
In embodiments, a ratio of the second average grain size of the planarized ruthenium layer in nanometers, determined on the planarized upper surface 220 of the planarized ruthenium layer 208, divided by the final thickness 212 of the planarized ruthenium layer 208 in nanometers, is greater than or equal to about 20, or greater than or equal to about 30, or greater than or equal to about 40, or greater than or equal to about 50. In contrast, a ratio of the first average grain size of the deposited ruthenium layer 210 in nanometers, determined on the surface 218 of the deposited ruthenium layer 210, divided by the first thickness 206 of the deposited ruthenium layer 210 in nanometers, is less than or equal to about 10, or less than or equal to about 8, or less than or equal to about 5.
In embodiments, a maximum grain size of the planarized ruthenium layer 208 is greater than or equal to about 200 nm, or greater than or equal to about 225 nm, or greater than or equal to about 250 nm, or greater than or equal to about 300 nm, or greater than or equal to about 350 nm, or greater than or equal to about 400 nm, or greater than or equal to about 550 nm. In embodiments, a root mean square roughness of the upper surface 220 of the planarized ruthenium layer 208 is less than or equal to about 1 nm, or less than or equal to about 0.8 nm, or less than or equal to about 0.5 nm. In embodiments, a root mean square roughness of the upper surface 220 of the planarized ruthenium layer 208 is less than or equal to about 90%, or less than or equal to about 80%, or less than or equal to about 70%, or less than or equal to about 60% of a root mean square roughness of the annealed ruthenium layer 211 prior to the chemical mechanical planarization.
In embodiments, a surface resistivity of the planarized ruthenium layer 208 is less than or equal to about 99%, or less than or equal to about 95%, or less than or equal to about 90%, or less than or equal to about 80% of a surface resistivity of the deposited ruthenium layer 210, when determined at the same thickness of both the deposited ruthenium layer and the planarized ruthenium layer.
Accordingly, the layered substrate according to embodiments disclosed herein has the benefits of the larger grain size only achievable using thicker ruthenium layers, with a thinner ruthenium layer having a reduced roughness obtained by the CMP procedure.
In embodiments, the process to produce the layered substrate may be performed in a substrate processing chamber which can be any PVD, CVD, ALD or other deposition chamber configured to deposit the diffusion barrier layer, the ruthenium layer, the molybdenum layer when present, and/or the capping layer. In embodiments, the annealing may take place in the same deposition chamber, or in another processing chamber.
The removal of a portion of the annealed ruthenium layer by chemical mechanical planarization to form a planarized ruthenium layer may be conducted using any assembly or system suitable for CMP to produce the layered substrate according to embodiments disclosed herein.
The methods described herein may be performed in individual process chambers that may be provided in a standalone configuration or as part of one or more cluster tools.
In accordance with embodiments of the disclosure, at least the following embodiments are contemplated.
The disclosure may be practiced using other semiconductor substrate processing systems wherein the processing parameters may be adjusted to achieve acceptable characteristics by those skilled in the art by utilizing the teachings disclosed herein without departing from the spirit of the disclosure. While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.
