MEMORY DEVICE

Abstract

A memory device includes a substrate, a three-dimensional (3D) NAND memory cell array on the substrate, and a peripheral circuit including a transistor on the substrate. The substrate includes p-type impurities and n-type impurities, a concentration of the n-type impurities in the substrate is lower than a concentration of the p-type impurities in the substrate, and the concentration of the n-type impurities in the substrate is about 2×1014 atoms/cm3 to about 1.5×1015 atoms/cm3 while the concentration of the p-type impurities in the substrate is about 9×1014 atoms/cm3 to about 2×1015 atoms/cm3.

Description

Claims

1. A memory device comprising: a substrate;a three-dimensional (3D) NAND memory cell array on the substrate; anda peripheral circuit comprising a transistor on the substrate,wherein the substrate comprises p-type impurities and n-type impurities,wherein a concentration of the n-type impurities in the substrate is lower than a concentration of the p-type impurities in the substrate, andwherein the concentration of the n-type impurities in the substrate is about 2×1014 atoms/cm3 to about 1.5×1015 atoms/cm3, and the concentration of the p-type impurities in the substrate is about 9×1014 atoms/cm3 to about 2×1015 atoms/cm3.

2. The memory device of claim 1, wherein a resistivity of the substrate is about 14 ohms centimeter (Ω·cm) to about 17 Ω·cm.

3. The memory device of claim 1, wherein a breakdown voltage of the transistor is about 19 volts (V) to about 24 V.

4. The memory device of claim 1, wherein a standby current of the memory device is less than or equal to 40 microamperes (µA).

5. The memory device of claim 1, wherein a leakage current of the transistor during an erase operation of the memory device is about 20.8 microamperes (µA) to about 22.5 µA.

6. The memory device of claim 1, wherein the 3D NAND memory cell array comprises: a stack structure comprising a plurality of gate layers alternately stacked with a plurality of interlayer insulating layers on the substrate; anda plurality of channel structures, wherein ones of the plurality of channel structures penetrate the stack structure in a vertical direction that is perpendicular to the substrate.

7. A memory device comprising: a first substrate;a peripheral circuit comprising a transistor on the first substrate;an insulating layer on the first substrate and on the peripheral circuit;a second substrate on the insulating layer; anda three-dimensional (3D) NAND memory cell array on the second substrate,wherein the first substrate comprises p-type impurities and n-type impurities,wherein a concentration of the n-type impurities in the first substrate is lower than a concentration of the p-type impurities in the first substrate, andwherein the concentration of the n-type impurities in the first substrate is about 2×1014 atoms/cm3 to about 1.5×1015 atoms/cm3, and the concentration of the p-type impurities in the first substrate is about 9×1014 atoms/cm3 to about 2×1015 atoms/cm3.

8. The memory device of claim 7, wherein a concentration of the n-type impurities in the second substrate is lower than the concentration of the n-type impurities in the first substrate.

9. The memory device of claim 7, wherein a resistivity of the first substrate is about 14 ohms centimeter (Ω·cm) to about 17 Ω·cm.

10. The memory device of claim 7, wherein a breakdown voltage of the transistor is about 19 volts (V) to about 24 V.

11. The memory device of claim 7, wherein a standby current of the memory device is less than or equal to 40 microamperes (µA).

12. The memory device of claim 7, wherein a leakage current of the transistor during an erase operation of the memory device is about 20.8 microamperes (µA) to about 22.5 µA.

13. The memory device of claim 7, wherein the 3D NAND memory cell array comprises: a stack structure comprising a plurality of gate layers alternately stacked with a plurality of interlayer insulating layers on the second substrate; anda plurality of channel structures, wherein ones of the plurality of channel structures penetrate the stack structure in a vertical direction perpendicular to the substrate.

14. A memory device comprising a first structure and a second structure on the first structure, wherein the first structure comprises: a first substrate;a three-dimensional (3D) NAND memory cell array on the first substrate;a first insulating layer on the first substrate and on the 3D NAND memory cell array; anda plurality of first bonding pads on the first insulating layer and electrically connected to the 3D NAND memory cell array, andwherein the second structure comprises: a second substrate;a peripheral circuit comprising a transistor on the second substrate;a second insulating layer on the second substrate and the peripheral circuit; anda plurality of second bonding pads on the second insulating layer and electrically connected to the peripheral circuit,wherein the plurality of first bonding pads are respectively in contact with the plurality of second bonding pads,wherein the second substrate comprises p-type impurities and n-type impurities,wherein a concentration of the n-type impurities in the second substrate is lower than a concentration of the p-type impurities in the second substrate, andwherein the concentration of the n-type impurities in the second substrate is about 2×1014 atoms/cm3 to about 1.5×1015 atoms/cm3, and the concentration of the p-type impurities in the second substrate is about 9×1014 atoms/cm3 to about 2×1015 atoms/cm3.

15. The memory device of claim 14, wherein a concentration of the n-type impurities in the first substrate is lower than the concentration of the n-type impurities in the second substrate.

16. The memory device of claim 14, wherein a resistivity of the second substrate is about 14 ohms centimeter (Ω·cm) to about 17 Ω·cm.

17. The memory device of claim 14, wherein a breakdown voltage of the transistor is about 19 volts (V) to about 24 V.

18. The memory device of claim 14, wherein a standby current of the memory device is less than or equal to 40 microamperes (µA).

19. The memory device of claim 14, wherein a leakage current of the transistor during an erase operation of the memory device is about 20.8 microamperes (µA) to about 22.5 µA.

20. The memory device of claim 14, wherein the 3D NAND memory cell array comprises: a stack structure comprising a plurality of gate layers alternately stacked with a plurality of interlayer insulating layers on the second substrate; anda plurality of channel structures, wherein ones of the plurality of channel structures penetrate the stack structure in a vertical direction that is perpendicular to the second substrate.