CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2021-141393, filed Aug. 31, 2021, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for manufacturing a wiring substrate.
Description of Background Art
Japanese Patent Application Laid-Open Publication No. 2001-298257 describes a method for manufacturing a printed wiring board in which a hole-filling paste is filled and cured in through holes of a substrate having the through holes. The entire contents of this publication are incorporated herein by reference.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a method for manufacturing a wiring substrate includes preparing a substrate including an insulating layer and metal foils laminated on sides of the insulating layer, respectively, forming a through hole in the substrate such that the through hole penetrates through the insulating layer and metal foils of the substrate, forming a first plating film on the substrate such that the first plating film is formed on the entire surface of each of the metal foils and an inner wall of the through hole, laminating one or more resin sheets on the first plating film such that the resin sheet or sheets cover the first plating film formed on the entire surface of a respective one of the metal foils, pressing the resin sheet or sheets such that resin is extruded from the resin sheet or sheets into the through hole and fills a space surrounded by the first plating film inside the through hole in the substrate, removing the resin sheet or sheets from the first plating film formed on the respective one of the metal foils, and forming a second plating film on the substrate such that the second plating film covers a surface of the resin in the through hole.
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. 1 is a cross-sectional view illustrating an example of a wiring substrate according to an embodiment of the present invention;
FIG. 2 is an enlarged view of a portion (II) of FIG. 1;
FIG. 3A is a cross-sectional view illustrating an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3B is a cross-sectional view illustrating an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3C is a cross-sectional view illustrating an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3D is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3E is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3F is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3G is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3H is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3I is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3J is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3K is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3L is a cross-sectional view illustrating a portion of an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention;
FIG. 3M is a cross-sectional view illustrating an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention; and
FIG. 3N is a cross-sectional view illustrating an example of a wiring substrate being manufactured using a manufacturing method according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
A method for manufacturing a wiring substrate according to an embodiment of the present invention is described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a wiring substrate 100, which is an example of a wiring substrate manufactured using the method for manufacturing a wiring substrate of the embodiment, and FIG. 2 is an enlarged view of a portion (II) of FIG. 1. FIGS. 3A-3N illustrate an example of a method for manufacturing the wiring substrate 100. The wiring substrate 100 is merely an example of a wiring substrate that may be manufactured using a method for manufacturing a wiring substrate according to an embodiment of the present invention. A laminated structure and the number of conductor layers and the number of insulating layers of a wiring substrate manufactured using the method for manufacturing a wiring substrate of the present embodiment are not limited to a laminated structure of the wiring substrate 100 of FIG. 1, and the number of conductor layers and the number of insulating layers included in the wiring substrate 100.
As illustrated in FIGS. 1 and 2, the wiring substrate 100 includes an insulating layer 2 and two conductor layers (conductor layer 11 and conductor layer 12) that are respectively formed on both sides of the insulating layer 2. A core substrate 1 of the wiring substrate 100 is formed by the insulating layer 2, the conductor layer 11, and the conductor layer 12. The insulating layer 2 has a first surface (2a) and a second surface (2b) on the opposite side with respect to the first surface (2a), and further has through holes 20 that each penetrate the insulating layer 2 in a thickness direction between the first surface (2a) and second surface (2b). The conductor layer 11 is formed on the first surface (2a) of the insulating layer 2, and the conductor layer 12 is formed on the second surface (2b) of the insulating layer 2. On the first surface (2a) of the insulating layer 2 and on the conductor layer 11, two insulating layers 21 and two conductor layers 13 are alternately laminated, and on the second surface (2b) of the insulating layer 2 and on the conductor layer 12, two insulating layers 22 and two conductor layers 14 are alternately laminated. The two pairs of insulating layers 21 and conductor layers 13 and the two pairs of insulating layers 22 and conductor layers 14 respectively form build-up parts of the wiring substrate 100 on the first surface (2a) side and the second surface (2b) side of the insulating layer 2.
In the description of the embodiment, a side farther from the insulating layer 2 in a thickness direction of the wiring substrate 100 is also referred to as an “outer side,” an “upper side,” or simply “upper,” and a side closer to the insulating layer 2 is also referred to as an “inner side,” a “lower side,” or simply “lower.” Further, for the conductor layers and the insulating layers, a surface facing the opposite side with respect to the insulating layer 2 is also referred to as an “upper surface,” and a surface facing the insulating layer 2 side is also referred to as a “lower surface.”
A solder resist 5 is formed on the outer conductor layer 13 and insulating layer 21 of the two pairs of conductor layers 13 and insulating layers 21. Similarly, a solder resist 5 is formed on the outer conductor layer 14 and insulating layer 22 of the two pairs of conductor layers 14 and insulating layers 22. Each of the solder resists 5 is provided with openings that each expose a part of the conductor layer 13 or a part of the conductor layer 14. Each of the solder resists 5 is formed of, for example, a photosensitive epoxy resin or polyimide resin, or the like.
In each of the insulating layers 21 and the insulating layers 22, via conductors (2d) penetrating the each insulating layer are formed. The via conductors (2d) penetrating the insulating layers 21 connect the conductor layers 13 to each other or the conductor layer 13 and the conductor layer 11. The via conductors (2d) penetrating the insulating layers 22 connect the conductor layers 14 to each other or the conductor layer 14 and the conductor layer 12.
The wiring substrate 100 further includes through-hole conductors 3 that physically and electrically connect the conductor layer 11 and the conductor layer 12 to each other. The through-hole conductors 3 are formed in the through holes 20 of the insulating layer 2. The wiring substrate 100 of FIG. 1 includes multiple through-hole conductors 3. The via conductors (2d) are laminated directly above some of the through-hole conductors 3. Penetrating conductors penetrating from one surface to the other surface of the wiring substrate 100 are formed by the through-hole conductors 3 and the multiple via conductors (2d) laminated overlapping the through-hole conductors 3 in a plan view. The term “plan view” means viewing the wiring substrate of the embodiment along the thickness direction thereof.
The through-hole conductors 3 cover inner walls of the through holes 20 along the inner walls, and have a predetermined thickness on the inner walls of the through holes 20 without completely filling the through holes 20. That is, the through-hole conductors 3 have hollow spaces 30 penetrating the through-hole conductors 3 in the thickness direction of the insulating layer 2, and as a whole have tubular shapes along the inner walls of the through holes 20. The hollow spaces 30 are also regions in the through holes 20 that are not occupied by a film body (first plating film 31) that forms the through-hole conductors 3.
The wiring substrate 100 further includes a resin 4 filling the hollow spaces 30. The hollow spaces 30 are preferably substantially completely filled with the resin 4. The hollow spaces 30 are filled with the resin 4 and, as will be described later, a surface (4c) of the resin 4 is flat. Therefore, as in the example of FIGS. 1 and 2, the via conductors (2d) are stably formed directly above the through holes 20. Further, it may be possible that, as compared to a case where the entire interiors of the through holes 20 are filled with the through-hole conductors 3, the interiors of the through holes 20 are filled in a short time. Further, it may be possible that, by selecting a resin having a thermal expansion coefficient close to that of the insulating layer 2 as the resin 4, a thermal stress generated in the insulating layer 2 is reduced. However, the resin 4 is not particularly limited in material as long as the resin 4 fills the hollow spaces 30. The resin 4 may be non-conductive or conductive. The resin 4 may be, for example, an insulating resin such as an epoxy resin, an acrylic resin, or a phenol resin, a conductive paste or conductive ink containing conductive particles such as silver particles, an epoxy resin and the like, or a magnetic resin containing an epoxy resin and magnetic particles. The magnetic particles may be iron oxide filler such as FeO, Fe2O3, and Fe3O4.
The insulating layer 2 and the insulating layers (21, 22) are formed of any insulating resin. An example of the insulating resin is a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin (BT resin), or a phenol resin. In the example of FIG. 1, the insulating layer 2 contains a core material (reinforcing material) (2c) formed of a glass fiber, an aramid fiber, or the like. Each of the insulating layers may further contain inorganic filler (not illustrated in the drawings) formed of fine particles of silica (SiO2), alumina, mullite, or the like.
The conductor layers (11-14), as well as the through-hole conductors 3 and the via conductors (2d), may be formed using any metal such as copper or nickel. Each of the conductor layers (13, 14) and the via conductor (2d) has a two-layer structure in the example of FIG. 1 but may have a single-layer structure or a laminated structure with any number of layers. Each of the conductor layers (13, 14) and the via conductors (2d) of FIG. 1 includes, for example, a metal film formed by electroless plating or sputtering or the like and a plating film formed by electrolytic plating using the metal film as a power feeding layer. Each of the via conductors (2d) is integrally formed with one of the conductor layers 13 and the conductor layers 14.
In the example of FIGS. 1 and 2, the through-hole conductors 3 are formed by the first plating film 31 on the inner walls of the through holes 20 so as to cover the inner walls. That is, the first plating film 31 is formed in a tubular shape with the thickness direction of the insulating layer 2 as an axial direction thereof. The first plating film 31 is, for example, a plating film formed of an electroless plating film and electrolytic plating film, the electroless plating film being formed on the inner walls of the through holes 20, and the electrolytic plating film being formed using the electroless plating film as a power feeding layer and being formed on an inner side of the electroless plating film in the through holes 20 so as to cover the electroless plating film. However, the through-hole conductors 3 may be formed of a plating film with any number of layers equal to or larger than one. In FIGS. 1 and 2, the first plating film 31 is illustrated as a single-layer plating film.
In the present embodiment, each of the conductor layer 11 and the conductor layer 12 has a laminated structure with three or less layers. In the wiring substrate 100 of FIGS. 1 and 2, the lamination structure of each of the conductor layer 11 and the conductor layer 12 is a three-layer structure. As illustrated in the enlarged view of FIG. 2, this three-layer structure includes a metal foil (10c), a metal film (second plating film) (10b), and a metal film (10a). These metal foil (10c), metal film (10b), and metal film (10a) are laminated on each of the first surface (2a) and the second surface (2b) of the insulating layer 2 in the order of the metal foil (10c), the metal film (10b), and the metal film (10a). However, instead of a three-layer structure, each of the conductor layer 11 and the conductor layer 12 may have, for example, a two-layer structure formed of a metal foil (10c) and a thick metal film (10b) formed on the metal foil (10c).
The metal foil (10c) may be formed of any metal, and is, for example, a foil body such as a copper foil or a nickel foil. The metal foil (10c) is, for example, a copper foil bonded to the insulating layer 2 by thermocompression. The metal film (10b) is formed, for example, using any metal such as copper or nickel. The metal film (10b) is, for example, an electroless plating film formed by electroless plating. It is also possible that the metal film (10b) is a metal film formed by sputtering. The metal film (10a) is formed, for example, using any metal such as copper or nickel. The metal film (10a) is, for example, an electrolytic plating film formed by electrolytic plating using the metal film (10b) and the metal foil (10c) as power feeding layers.
Each of the conductor layers (11-14) may include any conductor patterns. In the example of FIG. 1, the conductor layer 11 and the conductor layer 12 include conductor pads (1a) and multiple wiring patterns (1b). The conductor pads (1a) are provided at positions overlapping the through-hole conductors 3 in a plan view. That is, the conductor pads (1a) function as so-called through-hole pads of the through-hole conductors 3. The conductor pads (1a) are also provided at positions overlapping the through holes 20 and the hollow spaces 30 in a plan view. The conductor pads (1a) close the through holes 20 and the hollow spaces 30. Therefore, the conductor pads (1a) are also so-called cover pads of the through-hole conductors 3. The through holes 20 and the hollow spaces 30 are sandwiched between the conductor pads (1a) of the conductor layer 11 and the conductor pads (1a) of the conductor layer 12. Since the conductor pads (1a), which are cover pads, are provided, the via conductors (2d) is provided directly above the through-hole conductors 3. It is thought that miniaturization of the wiring substrate is realized. It is thought that the via conductors (2d) and the through-hole conductors 3 are stably and firmly electrically connected.
With reference to FIG. 2, as described above, the conductor pad (1a) is formed of three layers including the metal foil (10c), the metal film (10b) and the metal film (10a), and the through hole 20 and the hollow space 30 are closed on both the first surface (2a) side and the second surface (2b) side of the insulating layer 2. Therefore, the conductor pad (1a) included in each of the conductor layer 11 and the conductor layer 12 is in direct contact with the through-hole conductor 3. In the example of FIG. 2, the through-hole conductor 3 is connected to the metal film (10b) such that an end surface (3c) of the through-hole conductor 3 is in contact with a surface (10b1) of the metal film (10b) on the opposite side with respect to the metal film (10a).
The through-hole conductor 3 and the conductor pad (1a) are not integrally formed. There is an interface between the through-hole conductor 3 and the conductor pad (1a). The first plating film 31 that forms the through-hole conductor 3 is not integrally formed with any one of the metal film (10a), the metal film (10b) and the metal foil (10c). Since the first plating film 31 is formed before the metal film (10b) as to be described later, there is an interface between the first plating film 31 and the metal film (10b).
The through-hole conductor 3 (first plating film 31) formed in a tubular shape penetrates not only the insulating layer 2 but also the metal foil (10c). As illustrated in FIG. 2, the end surface (3c) of the first plating film 31 in a tubular shape and the surface (4c) of the resin 4 filling the hollow space 30 are in contact with the surface (10b1) of the metal film (10b). In the present embodiment, the surface (4c) of the resin 4 is formed substantially parallel to the first surface (2a) and the second surface (2b) of the insulating layer 2. The end surface (3c) of the first plating film 31 in a tubular shape and the surface (4c) of the resin 4 are formed substantially flush with each other. An interface between a through-hole surface, which is formed by the end surface (3c) of the through-hole conductor 3 and the surface (4c) of the resin 4, and the conductor pad (1a) is highly flat. In the present embodiment, since the through-hole surface is maintained highly flat, the via conductor (2d) is laminated on the through hole via the conductor pad (1a). It is thought that a mounting density of the wiring substrates is increased.
In the present embodiment, further, the through-hole surface, which is formed of the end surface (3c) of the through-hole conductor 3 and the surface (4c) of the resin 4, is formed at a substantially constant height from the first surface (2a) of the insulating layer 2. There is no recess on the through-hole surface. As illustrated in FIG. 2, the through-hole surface is formed substantially flush with a surface (10c1) of the metal foil (10c) facing the metal film (10b). The metal film (10b) and the metal film (10a) are formed on the through-hole surface and the surface (10c1) of the metal foil (10c). Therefore, the metal film (10b) and the metal film (10a) are also formed with a high flatness and at a substantially constant height from the first surface (2a) of the insulating layer 2. It is thought that, since occurrence of a recess in the conductor pad (1a) is suppressed, bonding between the conductor pad (1a) and the via conductor (2d) formed thereon is stabilized. Bonding reliability between the through hole and a conductor circuit formed thereon is improved, and a wiring substrate 100 with a high connection reliability is obtained.
The end surface (3c) of the through-hole conductor 3, the surface (4c) of the resin 4, and the surface (10c1) of the metal foil (10c) are formed substantially flush with each other. However, in order to further improve the flatness of the surfaces, a surface formed of the end surface (3c), the surface (4c), and the surface (10c1) may be a processed surface that has been subjected to processing. For example, mechanical processing such as cutting or polishing may be performed with respect to the surface. Therefore, the end surface (3c), the surface (4c), and the surface (10c1) may be polished surfaces that have been subjected to a polishing treatment.
Using the wiring substrate 100 illustrated in FIGS. 1 and 2 as an example, a method for manufacturing the wiring substrate of the embodiment is described with reference to FIGS. 3A-3N. Structural elements formed in the manufacturing method to be described below may be formed using the materials exemplified as the materials of the corresponding structural elements in the description of the wiring substrate 100 in FIG. 1, unless otherwise specified.
As illustrated in FIG. 3A, a substrate (starting substrate) including an insulating layer 2 and a metal foil (10c) laminated on both sides of the insulating layer 2 is prepared. The insulating layer 2 is formed of, for example, any insulating resin such as epoxy resin, a BT resin, or a phenol resin. The insulating layer 2 contains a core material (2c). However, it is also possible that the insulating layer 2 does not contain the core material (2c). The metal foil (10c) is formed of, for example, any metal such as copper or nickel. The metal foil (10c) is bonded to both sides of the insulating layer 2 using any method such as thermocompression bonding. For example, a double-sided copper-clad laminated plate may be prepared as the starting substrate.
As illustrated in FIG. 3B, through holes 20 penetrating the insulating layer 2 and the metal foil (10c) are formed. The through holes 20 may be formed, for example, by irradiating laser such as CO2 laser from the first surface (2a) side and/or the second surface (2b) side of the insulating layer 2. It is also possible that the through holes 20 are formed by drilling. The through holes 20 may be formed using any formation method.
As illustrated in FIG. 3C, a first plating film 31 is formed on an entire surface (10c1) of the metal foil (10c) on the opposite side with respect to the insulating layer 2, on exposed end surfaces of the metal foil (10c) facing the through holes 20, and on inner walls of the through holes 20. The first plating film 31 is formed of, for example, an electroless plating film and an electrolytic plating film. After the electroless plating film formed of any metal such as copper or nickel is formed by electroless plating, the electrolytic plating film is formed on the electroless plating film by electrolytic plating using the electroless plating film as a power feeding layer. It is also possible that, instead of the electroless plating film, a metal film such as a sputtering film formed by sputtering is formed. It is also possible that the first plating film 31 is formed of a single-layer plating film. A first plating film 31 having a desired thickness is formed. By forming the first plating film 31 on the end surfaces of the metal foil (10c) exposed in the through holes 20 and on the inner walls of the through holes 20, through-hole conductors 3 having hollow spaces 30 at centers thereof are formed by the first plating film 31 in the through holes 20. The metal foil (10c) and the first plating film 31 are sequentially laminated on each of the first surface (2a) and the second surface (2b) of the insulating layer 2.
Subsequently, a release film 8 is provided on the first plating film 31 on the surface on each of the first surface (2a) side and the second surface (2b) side of the insulating layer 2. The release film 8 is laminated on entire surfaces on both the upper side and the lower side of the wiring substrate illustrated in FIG. 3C in a process of being manufactured so as to cover the entire upper and lower surfaces. Therefore, the release film 8 also covers the hollow spaces 30. The release film 8 is not laminated inside the hollow spaces 30. A portion of the wiring substrate in a process of being manufactured in this state is illustrated in FIG. 3D. FIG. 3D is an enlarged view of only a portion corresponding to a portion (IIID) of the wiring substrate illustrated in FIG. 3C. FIGS. 3E-3L to be referenced below are also enlarged views of only the portion corresponding to the portion (IIID) of FIG. 3C in the respective processes.
As illustrated in FIG. 3D, the release film 8 is applied to the surface of the first plating film 31 on the first surface (2a) side and the second surface (2b) side of the insulating layer 2. In the manufacturing processes to be described below with reference to FIGS. 3E-3K, the same processing processes may be performed on both the first surface (2a) side and the second surface (2b) side of the insulating layer 2. Therefore, in the following description related to FIGS. 3D-3K, description related to the first surface (2a) side is mainly presented, and description related to the second surface (2b) side may be omitted. Further, in FIGS. 3D-3K, the reference numeral symbols on the second surface (2b) side are omitted.
The release film 8 covers the upper surface of the first plating film 31 and covers the hollow spaces 30. The release film 8 is provided using at least a material that does not firmly bond to but adheres to the first plating film 31. Therefore, the release film 8 and the first plating film 31 are easily separated from each other with a relatively weak force. For example, the release film 8 may include, for example, an adhesive layer and a bonding layer laminated on the adhesive layer. As described above, the adhesive layer is formed of a material that does not firmly bond to but sufficiently adheres to the first plating film 31.
For example, an acrylic resin may be used for the adhesive layer. On the other hand, the bonding layer is formed of a material that exhibits sufficient adhesion to a resin sheet 9 (see FIG. 3F) to be described later. For example, a polyimide resin may be used for the bonding layer. When the release film 8 has such a two-layer structure, the release film 8 may be placed on the first plating film 31 such that the adhesive layer side faces the first plating film 31. However, it is also possible that the release film 8 is formed of a single layer without including the bonding layer. It is sufficient as long as the release film 8 has adhesion to the first plating film 31.
Then, as illustrated in FIG. 3E, an opening (8a) is formed in the release film 8. The opening (8a) is formed with an area larger than an area of the hollow space 30 at a position overlapping the hollow space 30 in a plan view. Therefore, the opening (8a) exposes the hollow space 30 and also exposes the upper surface of the first plating film 31 at a peripheral edge part of the hollow space 30. The opening (8a) may be formed by laser processing. Laser is radiated from the first surface (2a) side of the insulating layer 2 toward the first plating film 31 at the peripheral edge part of the hollow space 30. A portion of the upper surface of the first plating film 31 and the hollow space 30 are exposed.
Next, as illustrated in FIG. 3F, a resin sheet 9 is laminated on the release film 8 in which the opening (8a) is formed and on the entire surfaces on the first surface (2a) side and the second surface (2b) side of the insulating layer 2. That is, the resin sheet 9 covers the upper surface of the release film 8, and covers the first plating film 31 and the hollow space 30 exposed from the opening (8a). The resin sheet 9 is formed of a resin material that will become a resin 4 that fills the hollow space 30 after a process to be described later (see FIG. 3G). Examples of such a resin material include insulating resins such as an epoxy resin, an acrylic resin, and a phenol resin, and a magnetic resin containing an epoxy resin and magnetic particles. The magnetic particles may be iron oxide filler such as FeO, Fe2O3, and Fe3O4. For example, the resin sheet 9 is a semi-cured insulating resin sheet containing such an insulating resin material.
As illustrated in FIG. 3G, by pressing the resin sheet 9 from both the first surface (2a) side and the second surface (2b) side of the insulating layer 2, the hollow space 30 is filled with the resin 4 exuded from the resin sheet 9. The pressing may be performed, for example, with heating, using a vacuum press device 50. Vacuum press conditions, that is, a temperature rising rate, a pressure, a pressure application timing, and the like, may be appropriately adjusted according to a material of the resin sheet 9 to be used. After filling the hollow space 30 with the resin 4, the resin 4 in the hollow space 30 and the resin sheet 9 on the release film 8 and on the first plating film 31 are solidified. The hollow space 30 is filled with a solidified resin material, that is, the resin 4.
By filling the hollow space 30 with a resin material using a vacuum press, even in cases such as when through holes are formed with a fine pitch, when a through hole aspect ratio (a ratio of a thickness of a core substrate to a diameter of a through hole) is large, and when through-holes with different diameters coexist, the through holes is uniformly filled with the resin material. Further, by performing the filling using a vacuum press, a volatile component that may be generated along with resin curing of the filling resin material or air that may be contained in the resin material is discharged by constant vacuuming. Therefore, there is less risk that a defect may occur such as that a void is generated in the resin 4 after filling and solidification.
Next, as illustrated in FIG. 3H, an opening (9a) is provided in the solidified resin sheet 9. The opening (9a) is formed by irradiating laser from the first surface (2a) side of the insulating layer 2 toward the first plating film 31 at the peripheral edge part of the hollow space 30. In the example of FIG. 3H, the opening (9a) is formed at a position that substantially overlaps the opening (8a) formed in the release film 8 in a plan view. However, the opening (9a) may be formed so as to expose an inner wall of the opening (8a). The solidified resin sheet 9 laminated on the first plating film 31 at the peripheral edge part of the hollow space 30 is removed from the first plating film 31 by laser irradiation. Due to the formation of the opening (9a), a portion of the upper surface of the first plating film 31 that was once exposed in the process illustrated in FIG. 3E is exposed again.
The present process of providing the opening (9a) in the resin sheet 9 further includes removing a portion of the solidified resin sheet 9 protruding from the hollow space 30 in a convex shape. Further, in the present embodiment, the removal includes removing a surface-side portion of the resin 4 filled in the hollow space 30. That is, in the present embodiment, a height of the resin 4, which is a length of the resin 4 in the hollow space 30 in the thickness direction of the insulating layer 2, is lower than a height of the upper surface of the first plating film 31 exposed by the formation of the opening (9a). Preferably, the removal of the surface-side portion of the resin 4 is performed until the surface (4c) of the resin 4 is substantially flush with the surface (10c1) of the metal foil (10c) facing the first plating film 31.
As illustrated in FIG. 3I, the release film 8 is removed from the upper surface of the first plating film 31 together with the resin sheet 9 laminated on the release film 8. For example, the resin sheet 9 and the release film 8 may be removed by sucking a surface of a portion of the resin sheet 9 laminated on the release film 8 with a tool or the like and pulling it up to the opposite side with respect to the insulating layer 2. Since the release film 8 adheres but does not firmly bonds to the upper surface of the first plating film 31, the release film 8 and the resin sheet 9 may be simultaneously peeled off without leaving the release film 8 or residues of the release film 8 or the like on the upper surface of the first plating film 31. The entire upper surface of the first plating film 31 is exposed.
Subsequently, as illustrated in FIG. 3J, the first plating film 31 on the surface on each of the first surface (2a) side and the second surface (2b) side of the insulating layer 2 is removed. The removal is preferably performed by etching. Through the present process, the first plating film 31 formed at a position above the height of the surface (10c1) of the metal foil (10c) laminated on the insulating layer 2 is removed over the entire surface. The surface (10c1) of the metal foil (10c) laminated on the insulating layer 2 is exposed, and the height of the end surface (3c) of the through-hole conductor 3 and the height of the surface (10c1) of the metal foil (10c) are substantially flush with each other.
By forming the opening (9a) in the resin sheet 9 illustrated in FIG. 3H, the height of the surface (4c) of the resin 4 inside the hollow space 30 exposed from the opening (9a) is substantially equal to the height of the surface (10c1) of the metal foil (10c). Therefore, as illustrated in FIG. 3J, the surface (10c1) of the metal foil (10c) on the insulating layer 2, the end surface (3c) of the through-hole conductor 3, and the surface (4c) of the resin 4 in the hollow space 30 are formed substantially flush with each other.
Optionally, after the removal of the first plating film 31 on the surfaces, the entire surfaces on both sides of the wiring substrate in a process of being manufactured may be polished. That is, the surface (10c1) of the metal foil (10c), the end surface (3c) of the through-hole conductor 3, and the surface (4c) of the resin 4 in the hollow space 30 form the surface of the wiring substrate in a process of being manufactured in which the first plating film 31 on the surfaces has been removed and are formed substantially flush with each other. The surface formed of the surface (10c1), the end surface (3c), and the surface (4c) are polished. The heights of the surface (10c1) of the metal foil (10c), the end surface (3c) of the through-hole conductor 3, and the surface (4c) of the resin 4 in the hollow space 30 are further satisfactorily aligned substantially flush with each other. It is thought that the flatness of the surface of the wiring substrate in a process of being manufactured including the through-hole conductor 3 filled with the resin 4 is further improved.
Examples of methods for the polishing include, but are not limited to, chemical mechanical polishing (CMP), belt sander polishing, buff polishing, and the like.
As illustrated in FIG. 3K, a metal film (second plating film) (10b) is formed on the entire surface formed of the surface (10c1) of the metal foil (10c), the end surface (3c) of the through-hole conductor 3, and the surface (4c) of the resin 4 in the hollow space 30, which is the surface of the wiring substrate in a process of being manufactured in which the first plating film 31 on the surfaces has been removed. The metal film (10b) is an electroless plating film formed of any metal such as copper or nickel. It is also possible that the metal film (10b) is a sputtering film formed by sputtering. As described above, the surface (10c1) of the metal foil (10c), the end surface (3c) of the through-hole conductor 3, and the surface (4c) of the resin 4 in the hollow space 30 are formed substantially flush with each other. Therefore, the metal film (10b) also is formed with good flatness, parallel to the surface of the insulating layer 2, and with a uniform thickness.
As illustrated in FIGS. 3L and 3M, conductor layers (a conductor layer 11 and a conductor layer 12), which each include the metal foil (10c), the metal film (10b) (second plating film) and a metal film (10a) and each have predetermined patterns, are respectively formed on the surfaces on the first surface (2a) side and the second surface (2b) side of the insulating layer 2. FIG. 3M illustrates the entire wiring substrate in a process of being manufactured after the formation of the conductor layer 11 and the conductor layer 12. For example, the metal film (10a) is formed by electrolytic plating using the metal film (10b) as a power feeding layer. As a result, the conductor layer 11 and the conductor layer 12 each having a three-layer structure are formed. After that, a core substrate 1 having predetermined conductor patterns is obtained by patterning the conductor layer 11 and the conductor layer 12 using a subtractive method. Since the metal film (10b) is formed with good flatness, the metal film (10a) on the metal film (10b) is also flatly and stably formed. A conductor pad (1a) with excellent flatness is formed on the through-hole conductor 3. It is also possible that the conductor layer 11 and the conductor layer 12 are formed using a semi-additive method. In this case, a plating resist (not illustrated in the drawings) having openings at predetermined locations is formed on the metal film (10b), and an electrolytic plating film (the metal film (10a)) is formed in the openings. The conductor layer 11 and the conductor layer 12 each including the metal film (10a) are formed. After that, the plating resist is removed, and unwanted portions of the metal foil (10c) and the metal film (10b) are removed by etching.
When the conductor layer 11 and the conductor layer 12 are formed to include fine wiring patterns, before forming the metal film (10b) in the process illustrated in FIG. 3K, a thickness of the metal foil (10c) may be reduced by polishing, half-etching, or the like. It is possible to shorten a processing time for removing unwanted portions of the metal foil (10c) and the metal film (10b) by etching in order to separate the conductor patterns in each of the conductor layers. It may be possible that excessive etching in width directions of the wiring patterns is suppressed and wiring patterns with fine widths are obtained.
It is also possible that each of the conductor layer 11 and the conductor layer 12 does not have a three-layer structure. For example, conductor patterns may be formed by forming a thick metal film (10b) and etching unwanted portions, without forming the metal film (10a).
When the wiring substrate 100 of FIG. 1 is manufactured, as illustrated in FIG. 3N, an insulating layer 21 and a conductor layer 13 are formed on the first surface (2a) side of the insulating layer 2, and an insulating layer 22 and a conductor layer 14 are formed on the second surface (2b) side of the insulating layer 2. In the formation of the insulating layer 21 and the insulating layer 22, on the first surface (2a) of the insulating layer 2 and on the conductor layer 11, and on the second surface (2b) of the insulating layer 2 and on the conductor layer 12, for example, a film-like epoxy resin is laminated and is heated and pressed. As a result, the insulating layer 21 and the insulating layer 22 are formed. Through holes (2e) for forming the via conductors (2d) are formed in the insulating layers by, for example, CO2 laser irradiation or the like.
Each of the conductor layer 13 and the conductor layer 14 is formed using, for example, a semi-additive method. That is, a metal film is formed on the surfaces of the insulating layer 21 and the insulating layer 22 and in the through holes (2e) by electroless plating or sputtering. A plating film is formed by pattern plating including electrolytic plating using the metal film as a power feeding layer. After that, unwanted portions of the metal film are removed, for example, by etching or the like. As a result, a conductor layer 13 including predetermined conductor patterns such as wiring patterns (13b), and a conductor layer 14 including predetermined conductor patterns such as wiring patterns (14b) are formed. The via conductors (2d) are formed in the through holes (2e).
After that, using the same method as that described with reference to FIG. 3N, a pair of an insulating layer 21 and a conductor layer 13 are further formed on the first surface (2a) side of the insulating layer 2, and a pair of an insulating layer 22 and a conductor layer 14 are further formed on the second surface (2b) side of the insulating layer 2. A solder resist 5 is formed on the outer conductor layer 13 and insulating layer 21 of the two pairs of conductor layers 13 and insulating layers 21. A solder resist 5 is formed on the outer conductor layer 14 and insulating layer 22 of the two pairs of conductor layers 14 and insulating layers 22. Each of the solder resists 5 is formed by applying, spraying, or laminating in a form of a film, a photosensitive epoxy resin or polyimide resin. Then, openings that each expose a portion of the conductor layer 13 or a portion of the conductor layer 14 are formed in the solder resists 5 by, for example, exposure and development, or laser processing, or the like. Through the above processes, the wiring substrate 100 in the example of FIG. 1 is completed.
A method for manufacturing a wiring substrate according to an embodiment of the present invention is not limited the method described with reference to the drawings. In the method for manufacturing a wiring substrate of the embodiment, it is also possible that any process other than the processes described above is added, or some of the processes described above are omitted.
Japanese Patent Application Laid-Open Publication No. 2001-298257 describes a method for manufacturing a printed wiring board in which a hole-filling paste is filled and cured in through holes of a substrate having the through holes. A high-viscosity hole-filling paste is press-fitted and filled into the through holes using a roller squeegee, and is cured after the filling is completed.
In filling the through holes with the high-viscosity filling paste described in Japanese Patent Application Laid-Open Publication No. 2001-298257, recesses may occur on surfaces of the through holes after curing. Flatness of a built-up layer near the through holes may be impaired, and a problem such as a connection failure in a circuit may occur.
A method for manufacturing a wiring substrate according to an embodiment of the present invention includes: preparing a substrate that includes an insulating layer and a metal foil laminated on both sides of the insulating layer; forming a through hole that penetrates the insulating layer and the metal foil; forming a first plating film on an entire surface of the metal foil and on an inner wall of the through hole; laminating a resin sheet on the first plating film; filling a resin exuded from the resin sheet into inside of the through hole surrounded by the first plating film by pressing the resin sheet; removing the resin sheet; and forming, on each of the both sides of the insulating layer, a second plating film that covers a surface of the resin filled in the inside of the through hole.
According to an embodiment of the present invention, it is thought that a method for manufacturing a wiring substrate is provided that allows a wiring substrate to be properly manufactured in which flatness of a through-hole surface and a built-up layer near a through hole is maintained.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
Patent Application
20230063719
