Patent Grant
11955554
The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the gate-all around transistor (GAA). The GAA device gets its name from the gate structure which can extend around the channel region providing access to the channel on two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. In conventional processes, GAA devices provide a channel in a silicon nanowire. However, integration of fabrication of the GAA features around the nanowire can be challenging. For example, while the current methods have been satisfactory in many respects, challenges with respect to performance of the resulting device may not be satisfactory in all respects.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a P-type metal-oxide-semiconductor device or an N-type metal-oxide-semiconductor multi-gate device. Specific examples may be presented and referred to herein as FINFET, on account of their fin-like structure. Also presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) device. A GAA device includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configuration. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanowires) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel (e.g., single nanowire) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.
Illustrated in
As with the other method embodiments and exemplary devices discussed herein, it is understood that parts of the semiconductor device 200 may be fabricated by a CMOS technology process flow, and thus some processes are only briefly described herein. Further, the exemplary semiconductor devices may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM) and/or other logic circuits, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure. In some embodiments, the exemplary devices include a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. Moreover, it is noted that the process steps of method 100, including any descriptions given with reference to
The method 100 begins at block 102 where a substrate is provided. Referring to the example of
In an embodiment of the method 100, in block 102, an anti-punch through (APT) implant is performed. The APT implant may be performed in a region underlying the channel region of a device for example, to prevent punch-through or unwanted diffusion.
Returning to
The epitaxial layers 208 or portions thereof may form a channel region of the multi-gate device 200. For example, the epitaxial layers 208 may be referred to as “nanowires” used to form a channel region of a multi-gate device 200 such as a GAA device. These “nanowires” are also used to form portions of the source/drain features of the multi-gate device 200 as discussed below. Again, as the term is used herein, “nanowires” refers to semiconductor layers that are cylindrical in shape as well as other configurations such as, bar-shaped. The use of the epitaxial layers 208 to define a channel or channels of a device is further discussed below.
It is noted that four (4) layers of each of epitaxial layers 206 and 208 are illustrated in
In some embodiments, the epitaxial layer 206 has a thickness range of about 2-6 nanometers (nm). The epitaxial layers 206 may be substantially uniform in thickness. In some embodiments, the epitaxial layer 208 has a thickness range of about 6-12 nm. In some embodiments, the epitaxial layers 208 of the stack are substantially uniform in thickness. As described in more detail below, the epitaxial layer 208 may serve as channel region(s) for a subsequently-formed multi-gate device and its thickness chosen based on device performance considerations. The epitaxial layer 206 may serve to define a gap distance between adjacent channel region(s) for a subsequently-formed multi-gate device and its thickness chosen based on device performance considerations.
By way of example, epitaxial growth of the layers of the stack 204 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers such as, the layers 208 include the same material as the substrate 202. In some embodiments, the epitaxially grown layers 206, 208 include a different material than the substrate 202. As stated above, in at least some examples, the epitaxial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer and the epitaxial layer 208 includes an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the epitaxial layers 206, 208 may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers 206, 208 may be chosen based on providing differing oxidation, etch selectivity properties. In various embodiments, the epitaxial layers 206, 208 are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3 to about 1×1017 cm−3), where for example, no intentional doping is performed during the epitaxial growth process.
The method 100 then proceeds to block 106 where fin elements are patterned and formed. With reference to the example of
The fin elements 210 may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer over the substrate 202 (e.g., over the epi stack 204), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, pattering the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of the substrate 202, and layers 204 formed thereupon, while an etch process forms trenches in unprotected regions through masking layer(s) such as hard mask, thereby leaving the plurality of extending fins. The trenches may be etched using a dry etch (e.g., reactive ion etching), a wet etch, and/or other suitable processes. The trenches may be filled with dielectric material forming, for example, shallow trench isolation features interposing the fins.
In some embodiments, the dielectric layer may include SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials known in the art. In various examples, the dielectric layer may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, and/or other suitable process. In some embodiments, after deposition of the dielectric layer, the device 200 may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (and subsequently formed STI features 302) may include a multi-layer structure, for example, having one or more liner layers.
In some embodiments of forming the isolation (STI) features, after deposition of the dielectric layer, the deposited dielectric material is thinned and planarized, for example by a chemical mechanical polishing (CMP) process. The CMP process may planarize the top surface thereby forming STI features 302. The STI features 302 interposing the fin elements are recessed. Referring to the example of
Numerous other embodiments of methods to form the fins on the substrate may also be used including, for example, defining the fin region (e.g., by mask or isolation regions) and epitaxially growing the epitaxial stack 204 in the form of the fin. In some embodiments, forming the fins may include a trim process to decrease the width of the fins. The trim process may include wet or dry etching processes.
The method 100 then proceeds to block 108 where sacrificial layers/features are formed and in particular, a dummy gate structure. While the present discussion is directed to a replacement gate process whereby a dummy gate structure is formed and subsequently replaced, other configurations may be possible.
With reference to
Thus, in some embodiments using a gate-last process, the gate stack 304 is a dummy gate stack and will be replaced by the final gate stack at a subsequent processing stage of the device 200. In particular, the gate stack 304 may be replaced at a later processing stage by a high-K dielectric layer (HK) and metal gate electrode (MG) as discussed below. In some embodiments, the gate stack 304 is formed over the substrate 202 and is at least partially disposed over the fin elements 210. The portion of the fin elements 210 underlying the gate stack 304 may be referred to as the channel region. The gate stack 304 may also define a source/drain region of the fin elements 210, for example, the regions of the fin and epitaxial stack 204 adjacent and on opposing sides of the channel region.
In some embodiments, the gate stack 304 includes the dielectric layer and a dummy electrode layer. The gate stack 304 may also include one or more hard mask layers (e.g., oxide, nitride). In some embodiments, the gate stack 304 is formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps. Exemplary layer deposition processes includes CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. In forming the gate stack for example, the patterning process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods.
As indicated above, the gate stack 304 may include an additional gate dielectric layer. For example, the gate stack 304 may include silicon oxide. Alternatively or additionally, the gate dielectric layer of the gate stack 304 may include silicon nitride, a high-K dielectric material or other suitable material. In some embodiments, an electrode layer of the gate stack 304 may include polycrystalline silicon (polysilicon). Hard mask layers such as SiO2, Si3N4, silicon oxynitride, alternatively include silicon carbide, and/or other suitable compositions may also be included.
The method 100 then proceeds to block 110 where a spacer material layer is deposited on the substrate. The spacer material layer may be a conformal layer (see, e.g.,
Referring to the example of
In some embodiments, the deposition of the spacer material layer is followed by an etching back (e.g., anisotropically) the dielectric spacer material. Referring to the example, with reference to the example of
The method 100 then proceeds to block 112 where an oxidation process is performed. The oxidation process may be referred to as a selective oxidation as due to the varying oxidation rates of the layers of the epitaxial stack 204, certain layers are oxidized. In some examples, the oxidation process may be performed by exposing the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, the device 200 is exposed to a wet oxidation process using water vapor or steam as the oxidant, at a pressure of about 1 ATM, within a temperature range of about 400-600° C., and for a time from about 0.5-2 hours. It is noted that the oxidation process conditions provided herein are merely exemplary, and are not meant to be limiting. It is noted that this oxidation process may in some embodiments, extend such that the oxidized portion of the epitaxial layer(s) of the stack abuts the sidewall of the gate structure 304.
With reference to the example of
By way of example, in embodiments where the epitaxial layers 206 include SiGe, and where the epitaxial layers portion 208 includes Si, the faster SiGe oxidation rate (i.e., as compared to Si) ensures that the SiGe layer 206 becomes fully oxidized while minimizing or eliminating the oxidization of other epitaxial layers 208. It will be understood that any of the plurality of materials discussed above may be selected for each of the first and second epitaxial layer portions that provide different suitable oxidation rates.
The method 100 then proceeds to block 114 where source/drain features are formed on the substrate. The source/drain features may be formed by performing an epitaxial growth process that provides an epitaxy material on the fin 210 in the source/drain region. In an embodiment, the epitaxy material of the source/drain is formed cladding the portions of the epitaxy layers remaining in the fins' source/drain regions. Referring to the example of
In various embodiments, the grown semiconductor material of the source/drain 702 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. In some embodiments, the material of the source/drain 702 may be in-situ doped during the epi process. For example, in some embodiments, epitaxially grown material may be doped with boron. In some embodiments, epitaxially grown material may be doped with carbon to form Si:C source/drain features, phosphorous to form Si:P source/drain features, or both carbon and phosphorous to form SiCP source/drain features. In an embodiment, the epitaxial material of the source/drain 702 is silicon and the layer 208 also is silicon. In some embodiments, the layers 702 and 208 may comprise a similar material (e.g., Si), but be differently doped. In other embodiments, the epitaxy layer for the source/drain 702 includes a first semiconductor material, the epitaxially grown material 208 includes a second semiconductor different than the first semiconductor material. In some embodiments, the epitaxially grown material of the source/drain 702 is not in-situ doped, and, for example, instead an implantation process is performed.
The method 100 then proceeds to block 116 where an inter-layer dielectric (ILD) layer is formed on the substrate. Referring to the example of
In some examples, after depositing the ILD (and/or CESL or other dielectric layers), a planarization process may be performed to expose a top surface of the gate stack 304. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer 802 (and CESL layer, if present) overlying the gate stack 304 and planarizes a top surface of the semiconductor device 200.
The method 100 then proceeds to block 118 where the dummy gate (see block 108) is removed. The gate electrode and/or gate dielectric may be removed by suitable etching processes. In some embodiments, block 118 also includes selective removal of the epitaxial layer(s) in the channel region of the device is provided. In embodiments, the selected epitaxial layer(s) are removed in the fin elements within the trench provided by the removal of the dummy gate electrode (e.g., the region of the fin on and over which the gate structure will be formed, or the channel region). Referring to the example of
The method 100 then proceeds to block 120 where a gate structure is formed. The gate structure may be the gate of a multi-gate transistor. The final gate structure may be a high-K/metal gate stack, however other compositions are possible. In some embodiments, the gate structure forms the gate associated with the multi-channels provided by the plurality of nanowires (now having gaps there between) in the channel region.
Referring to the example of
In some embodiments, the interfacial layer of the gate stack 1002 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The gate dielectric layer 1004 of the gate stack 1002 may include a high-K dielectric layer such as hafnium oxide (HfO2). Alternatively, the gate dielectric layer 1004 of the gate stack 1002 may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTSiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The high-K gate dielectric layer 1002 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods. The metal layer of the high-K/metal gate stack 1002 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the metal layer of gate stack 1002 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Jr, Co, Ni, other suitable metal materials or a combination thereof. In various embodiments, the metal layer of the gate stack 1002 may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the metal layer of the gate stack 1002 may be formed separately for N-FET and P-FET transistors which may use different metal layers. In various embodiments, a CMP process may be performed to remove excessive metal from the metal layer of the gate stack 1002, and thereby provide a substantially planar top surface of the metal layer of the gate stack 1002. The metal layer 1006 of the gate stack 1002 is illustrated in
In an embodiment, the oxidized layer 602 provides an inner spacer having a length in the x-direction of t1. t1 may be between approximately 10 nanometers (nm) and approximately 12 nm. The dimension t1 may extend an entire length of the source/drain region. In an embodiment, the oxidized layer 602 provides an inner spacer having a length in the y-direction of t2. t2 may be between approximately 5 nanometers (nm) and approximately 7 nm.
The semiconductor device 200 may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate 202, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method 100, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method 100.
Referring now to
The example embodiments of the method 1100 are illustrated in
The method 1100 begins at block 1102 where a substrate is provided. Block 1102 may be substantially similar to block 102, discussed above with reference to them method 100 of
The method 1100 proceeds to block 1104 where an epitaxial stack is provided. Block 1104 may be substantially similar to block 104, discussed above with reference to the method 100 of
The method 1100 proceeds to block 1106 where one or more fin elements are provided. Block 1106 may be substantially similar to block 106, discussed above with reference to the method 100 of
The method 1100 proceeds to block 1108 where a dummy gate structure is formed. Block 1108 may be substantially similar to block 108, discussed above with reference to the method 100 of
The method 1100 proceeds to block 1110 where spacer elements are formed. Block 1110 may be substantially similar to block 110, discussed above with reference to the method 100 of
The method 1100 proceeds to block 1112 where a select oxidation of epitaxial layers of the epitaxial stack is performed. Block 1112 may be substantially similar to block 112, discussed above with reference to the method 100 of
The method 1100 then proceeds to block 1113 where a selective etching process is performed. The selective etching may etch the oxidized layer, discussed above in block 1112. In some embodiments, the oxidized layers are removed from the source/drain region of the fin element(s) (e.g., the region of the fin adjacent the channel region underlying the gate stack). A portion of the oxidized layer directly underlying the spacer element adjacent the gate stack remains on the substrate (e.g., during the etching process the spacer element provides a masking element). As illustrated in
The method 1100 proceeds to block 1114 where a source/drain feature is formed. Block 1114 may include growing an epitaxial layer to form the source/drain feature. Block 1114 may be substantially similar to block 114, discussed above with reference to the method 100 of
The method 1100 proceeds to block 1116 where an inter-layer dielectric layer is formed. Block 1116 may be substantially similar to block 116, discussed above with reference to the method 100 of
The method 1100 proceeds to block 1118 where a dummy gate removal is performed and/or a release of the nanowires of the epitaxial stack in the channel region is performed. Block 1118 may be substantially similar to block 118, discussed above with reference to the method 100 of
The method 1100 proceeds to block 1120 where a gate structure (e.g., replacement gate structure, high-k metal gate structure) is formed. Block 1120 may be substantially similar to block 120, discussed above with reference to the method 100 of
In an embodiment, the oxidized layer portion 602A provides an inner spacer having a length in the x-direction of t3. t3 may be between approximately 4 nanometers (nm) and approximately 6 nm. In an embodiment, the oxidized layer 602A provides an inner spacer having a length in the y-direction, which may be between approximately 5 nanometers (nm) and approximately 7 nm.
Referring now to
The example embodiments of the method 1700 are illustrated in
The method 1700 begins at block 1702 where a substrate is provided. Block 1702 may be substantially similar to block 102, discussed above with reference to the method 100 of
The method 1700 proceeds to block 1704 where an epitaxial stack is provided. Block 1704 may be substantially similar to block 104, discussed above with reference to the method 100 of
The method 1700 proceeds to block 1706 where one or more fin elements are provided. Block 1706 may be substantially similar to block 106, discussed above with reference to the method 100 of
The method 1700 proceeds to block 1708 where a dummy gate structure is formed. Block 1708 may be substantially similar to block 108, discussed above with reference to the method 100 of
The method 1700 then proceeds to block 1709 where a selective etch of the epitaxial layers is performed. In an embodiment, a first composition of epitaxial material of the epitaxy stack provided in block 1704 is removed. In a further embodiment, the removed epitaxial layers are SiGe. Referring to the example of
The method 1700 then proceeds to block 1710 where spacer material elements are formed. Block 1710 may be substantially similar to block 110, discussed above with reference to the method 100 of
In some embodiments, block 1710 continues to include etch back of the spacer material layer to form spacer elements. The etch back may be substantially similar to as discussed above with reference to block 110 of the method 100 of
The method 1700 proceeds to block 1714 where a source/drain feature is formed. Block 1714 may include growing an epitaxial layer to form the source/drain feature. Block 1714 may be substantially similar to block 114, discussed above with reference to the method 100 of
The method 1700 proceeds to block 1716 where an inter-layer dielectric layer is formed. Block 1116 may be substantially similar to block 116, discussed above with reference to the method 100 of
The method 1700 proceeds to block 1718 where a dummy gate removal is performed and/or a release of the nanowires of the epitaxial stack in the channel region is performed. Block 1718 may be substantially similar to block 118, discussed above with reference to the method 100 of
The method 1700 proceeds to block 1720 where a gate structure (e.g., replacement gate structure, high-k metal gate structure) is formed. Block 1720 may be substantially similar to block 120, discussed above with reference to the method 100 of
In an embodiment, the spacer element 402 provides an inner spacer having a length in the x-direction of t4. t4 may be between approximately 4 nanometers (nm) and approximately 6 nm. In an embodiment, the spacer element 402 provides an inner spacer having a length in the y-direction of between approximately 5 nanometers (nm) and approximately 7 nm.
Referring now to
The example embodiments of the method 2500 are illustrated in
The method 2500 begins at block 2502 where a substrate is provided. Block 2502 may be substantially similar to block 102, discussed above with reference to the method 100 of
The method 2500 proceeds to block 2504 where an epitaxial stack is provided. Block 2504 may be substantially similar to block 104, discussed above with reference to the method 100 of
The method 2500 proceeds to block 2506 where one or more fin elements are provided. Block 2506 may be substantially similar to block 106, discussed above with reference to the method 100 of
The method 2500 proceeds to block 2508 where a dummy gate structure is formed. Block 2508 may be substantially similar to block 108, discussed above with reference to the method 100 of
The method 2500 then proceeds to block 2510 where spacer elements are formed. Block 2510 may be substantially similar to block 110, discussed above with reference to the method 100 of
The spacer material layer may be a conformal layer (see, e.g.,
The method 2500 then proceeds to block 2511 where a selective etch of the epitaxial layers is performed. In an embodiment, a first composition of epitaxial material of the epitaxy stack provided in block 2504 is removed. In a further embodiment, the removed epitaxial layers are SiGe. Referring to the example of
The method 2500 then proceeds to block 2512 where a select oxidation of the remaining epitaxial layers is performed. Again, it is noted during the selective etch removal of the epitaxial layers 206 in block 2511, that the spacer elements 402 protect the epitaxial layer portion 206A that is directly abutting the gate structure 304. In other words,
The oxidation process may be referred to as a selective oxidation as due to the varying oxidation rates of the layers of the epitaxial stack 204, certain layers are oxidized for example, portion 206A is oxidized to form oxidized portion 2702. In some examples, the oxidation process may be performed by exposing the device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, the device 200 is exposed to a wet oxidation process using water vapor or steam as the oxidant, at a pressure of about 1 ATM, within a temperature range of about 400-600° C., and for a time from about 0.5-2 hours. It is noted that the oxidation process conditions provided herein are merely exemplary, and are not meant to be limiting. Referring to the example of
The method 2500 proceeds to block 2514 where a source/drain feature is formed. Block 2514 may include growing an epitaxial layer to form the source/drain feature. Block 2514 may be substantially similar to block 114, discussed above with reference to the method 100 of
The method 2500 proceeds to block 2516 where an inter-layer dielectric layer is formed. Block 1116 may be substantially similar to block 116, discussed above with reference to the method 100 of
The method 2500 proceeds to block 2518 where a dummy gate removal is performed and/or a release of the nanowires of the epitaxial stack in the channel region are released. Block 2518 may be substantially similar to block 118, discussed above with reference to the method 100 of
The method 2500 proceeds to block 2520 where a gate structure (e.g., replacement gate structure, high-k metal gate structure) is formed. Block 2520 may be substantially similar to block 120, discussed above with reference to the method 100 of
In an embodiment, the oxidized portion 2702 provides an inner spacer having a length in the x-direction of t5. t5 may be between approximately 4 nanometers (nm) and approximately 6 nm. In an embodiment, the oxidized portion 2702 provides an inner spacer having a length in the y-direction of between approximately 5 nanometers (nm) and approximately 7 nm.
Thus, provided are methods and devices where a gate structure does not directly contact or abut a source/drain region. Configurations of dielectric materials (e.g., spacer elements (402) and/or oxidized epitaxial layers (e.g., 302)) interpose the source/drain features 702 and the gate structure 1002. In some embodiments, this provides a benefit of reducing the Cgd (gate-to-drain capacitance) of the device. In some embodiments, this provides Ceff (effective capacitance) of the device is reduced without obvious penalty to the Ieff. Therefore, in some embodiments, the speed of the circuit could be improved.
Thus, in an embodiment provided is a method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.
In another of the broader embodiments, a method of fabricating a semiconductor device is provided that includes forming a first silicon layer and a second silicon layer. A silicon germanium (SiGe) layer is formed interposing the first and second silicon layers. A first portion of the SiGe layer is removed to provide an opening between the first and second silicon layers in a channel region. An oxidized second portion of the SiGe layer is provided adjacent the opening. The method provides for epitaxially growing a source/drain feature on the first and second silicon layers and abutting a sidewall of the oxidized second portion of the SiGe layer. A first region of a gate structure is formed in the opening, wherein each of the first and second silicon layers adjacent the gate structure provides a channel.
Also discussed is a multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.
The present application is a continuation application of U.S. patent application Ser. No. 16/696,845, filed Nov. 26, 2019, which is a continuation of U.S. patent application Ser. No. 16/016,748, filed Jun. 25, 2018, now U.S. Pat. No. 11,145,762, entitled “MULTI-GATE DEVICE,” which is a divisional application of U.S. patent application Ser. No. 15/355,844, filed Nov. 18, 2016, now U.S. Pat. No. 10,008,603, entitled “MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF,” each of which is hereby incorporated by reference in its entirety.
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| Number | Date | Country | |
|---|---|---|---|
| Parent | 15355844 | Nov 2016 | US |
| Child | 16016748 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16696845 | Nov 2019 | US |
| Child | 17812997 | US | |
| Parent | 16016748 | Jun 2018 | US |
| Child | 16696845 | US |
