Patent Application
20070090531
The invention generally relates to manufacturing integrated circuits, and to manufacturing semiconductor wafers. In particular embodiments, the invention particularly relates to the formation of a wiring level and an electrical isolation associated with the wiring level on a semiconductor wafer.
In the field of manufacturing integrated circuits the process of forming conductive wiring levels, particularly metal levels, above a semiconductor substrate may be distinguished from the earlier formation of those electrical components, that depend on the presence of active areas within the monocrystalline silicon substrate. The corresponding process sequence aimed at the formation of those upper levels is thus also called “back-end of line” (BEOL). It comprises steps of forming wiring lines of a level, isolation layers between them and contacts in order to establish the desired connections between different wiring levels according the design of the integrated circuit to be manufactured.
As the integration level not only of the electrical components that are based on active areas increases, but also of the upper wiring levels, the electromagnetic interactions between the wiring lines have to be kept as small as possible in order to guarantee accurate functioning of the integrated circuit. This is particularly valid in the case of semiconductor memory products, wherein, for example, densely arranged bit lines form a first wiring level above the substrate (DRAM memory, dynamic random access memory). Consequently, an isolation between the wiring lines has to be provided, which minimizes among others the capacitive or inductive coupling between each two lines. The reduction of this coupling may be achieved by filling up the spacings between neighboring lines with a dielectric material, which has a low dielectric constant k.
Several low-k materials are known, but the corresponding process integration requires large efforts and costs. An alternative is to form voids within a dielectric layer, wherein the material deposited relates to conventional dielectrics having dielectric constants ranging from, e.g., 3.5 up to 4.5. A typical interlayer dielectric material is a silicon oxide having a dielectric constant k of around 4.0. The mean dielectric constant k of the layer may, however, be reduced by means of the voids, which are filled with air that has a constant k close to 1.
Interlevel (ILD) dielectric layers may be deposited upon the wiring lines of a wiring level in order to fill the spacings between the lines as well as to provide a separation between the next upper or lower wiring level. A common process to deposit dielectric materials for the ILD is high-density plasma deposition (HDP). HDP deposition is performed by means of a plasma reactor, which has in addition to a first plasma-generating high frequency source, a second high frequency source, which may be controlled separately from the plasma-generating source. This separate control may serve to direct and adjust the acceleration of high energy ions as a sputtering agent onto the target surface. Simultaneously the reactive species to be deposited on the target surface are supplied from the plasma. A hat-like profile results from this process. The capability of HDP for void-free filling is a function of the aspect ratio of the structures to be filled.
An advantage of HDP deposition arises from the fact that vertical walls of a deposition profile are more efficiently affected by the sputtering than horizontal surfaces. This is the reason why HDP deposition has been preferred over conventional plasma-enhanced CVD (PECVD: plasma enhanced chemical vapor deposition), since the deposition profile of PECVD-layers develops disadvantageous overhang sections due to the stronger growth of deposited material on horizontal surfaces as compared with vertical surfaces of structures on the wafer. The space beneath such an overhang effects a reduced ability to be accessed by further deposition, etc. Further, the overhangs reveal an increased roughness at the surface. Performing HDP deposition the overhangs cannot develop.
In various embodiments, the present invention reduces the effects of capacitive or inductive coupling between wiring or metal lines of a wiring level of integrated circuits. A more particular embodiment reduces the mean dielectric constant k of the filling between different wiring levels. Further embodiments improve the manufacturing process and the quality of back-end of line (BEOL) process steps.
For example, one embodiment method forms a wiring level and an electrical isolation associated with a wiring level on a surface of a semiconductor wafer. At least two electrically conductive wiring lines are formed upon the surface of the wafer such that each two of the wiring lines encompass a spacing arranged there between. A first layer of a first dielectric material is deposited upon the wiring lines and into the spacings by means of plasma enhanced chemical vapor deposition (PECVD) such that air-filled voids form in the first layer within the spacings between neighboring wiring lines.
In another embodiment, a wiring level and an electrical isolation associated with the wiring level are formed on a surface of a semiconductor wafer. At least two electrically conductive wiring lines are formed upon the surface such that each two of the wiring lines encompass a spacing arranged there between. A first layer of amorphous carbon is deposited upon the wiring lines by means of a plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids form below the first layer within the spacings between neighboring wiring lines.
According to embodiments of the invention, a plasma enhanced chemical vapor deposition (PECVD) is used to deposit dielectric material upon and, according to one aspect, between wiring lines of a wiring level. The deposition is performed, such that voids form between the wiring lines, i.e., within the spacings of those lines. The formation of voids is achieved by a suitable choice of parameter settings during deposition and depends on the particular apparatus employed for the deposition process.
It is noted that the HDP deposition also refers to a plasma enhanced CVD process. However, according to embodiments no sputtering is performed with respect to PECVD process as disclosed herein. This means that no HDP deposition is performed in such embodiments with respect to the deposition of the first layer. The formation of voids, which are air-filled, leads to a reduction of the mean dielectric constant k of the first layer. More explicitly, a dielectric constant k close to 1 of air may reduce the mean dielectric constant to values of less than 3.2,as an example.
Further, it has been found that the PECVD process, if adapted to form voids within spacings by means of the deposition parameter settings, may be controlled such that a target geometry, size and position of the voids within the spacings can be maintained up to a considerable degree.
In contrast, an HDP deposition may be adapted to form voids, but the voids thus formed are found to be hardly controllable. For example, the sizes of those voids may vary from spacing to spacing despite the depths and widths of those spacings between neighboring being similar. The same is similar with respect to position and geometry of those voids. In particular, voids as formed by HDP deposition may be located in undesired locations above a spacing, where a further CMP (chemical mechanical polishing) process may result in opening the void. A further deposition process, for example of a metal, may then lead to a malfunction of the resulting circuit. According to the invention, however, the voids may be well-controlled by the process parameter settings and the void characteristics are highly reproducible.
A preferred embodiment relates to forming voids by depositing amorphous carbon as the first layer. A highly non-conformal carbon deposition results in the formation of voids, which in this case fill up the complete spacing between two wiring lines. This means, that upon deposition of amorphous carbon as the first layer, the spacings may be kept free from amorphous carbon, which again yields a particularly low k value for these spacings. The reason is that amorphous carbon provides the feature, that under optimum parameter settings of the plasma reactor, the growth is directed merely upwards from horizontal surfaces, while vertical surfaces may be kept free from any deposition. In a PECVD carbon deposition process, the most inclined direction of growth, as measured from the normal axis, amounts to a maximum of 40°, or a minimum of 50° with respect to an idealized horizontal surface plane of the wafer.
It is found that leakage currents and breakdown voltages of air gaps are uncritical for the BEOL process applications as being considered herein.
Alternative embodiments relate to employing fluorine or carbon doped silicon glass as the dielectric material for the first layer. It is found that both materials may be advantageously employed in combination with the PECVD process yielding highly reproducible and conformal voids. In particular, the voids thus formed reside within the spacing, hardly extending out from this spacing into a region above it, which otherwise might lead to an interference with the next upper wiring level as explained above.
A further aspect of the invention relates to applying a second layer comprising a second dielectric material in addition to the first layer. Accordingly, the electrical isolation of the wiring level is provided by two different dielectric layers. Therein, the first layer formed by a PECVD process, which includes or leads to the formation of voids, mainly represents a so-called intrametal dielectric (IMD) layer. This layer serves to reduce capacitive and/or inductive coupling between wiring lines of the same wiring level. The second layer is provided as an interlevel dielectric (ILD) layer, which serves to reduce the capacitive and/or inductive coupling from wiring lines of one wiring level with respect to wirings lines of another wiring level.
In a preferred embodiment, the dielectric materials are chosen differently, such that the second layer (ILD) may serve as a hard mask with respect to etching the first layer (IMD) in order to form contacts between wiring lines of different wiring levels.
In one embodiment, the second layer may be a silicon oxide, or fluorine-doped or carbon-doped silicon glass, and the first layer is made of amorphous carbon. The silicon glass or oxide layer may serve as a hard mask for etching the carbon. This feature provides an accurate etch profile with respect to carbon on the one hand, and further the existence of a protection layer (silicon glass or oxide) with regard to amorphous carbon on the other hand. Amorphous carbon could be harmed when a further metal, for example tungsten, is deposited directly upon the carbon layer, because of the comparatively high temperatures applied during such a deposition.
With regard to the formation of wiring lines of the wiring level, the invention is not limited to sets of explicit steps as embodied herein. The formation of wiring levels starts with the provision of a wafer having a preferably plane surface. The surface can be planarized by means of, e.g., chemical mechanical polishing (CMP). The surface may relate to the substrate surface (silicon) or an isolation layer of a next lower wiring level.
For example, wiring lines may be formed by first depositing a sacrificial material, which will be removed later. The layer of this sacrificial material is then patterned using resist techniques. Removed portions of the pattern within this layer are filled with electrically conductive material, e.g., a metal such as tungsten, aluminum, copper or compositions comprising these materials, e.g., tungsten silicide. Planarizing the conductive layer back to the surface of the sacrificial layer restricts the conductive material to the removed portions within the layer of the sacrificial material. The remainder of the latter is also removed such that conductive wiring lines remain as raised structure elements upon the substrate surface.
Alternatively, the conductive material can be deposited upon the planarized surface of the isolation layer and be lithographically patterned to yield the wiring lines, for example.
Other aspects and many of the attendant advantages of embodiments of the present invention will be readily appreciated and become better understood by reference to the following more detailed description of preferred embodiments in connection with the accompanied drawings. Features that are substantially or functionally equal or similar will be referred to with the same reference signs.
The following list of reference symbols can be used in conjunction with the figures:
The surface 13 is provided by a planarized upper surface of an isolation layer 12, which pertains to a further wiring level arranged next below the present wiring level 14, and may contain a silicon oxide, a nitride, a doped silicon glass, etc. Alternatively, layer 12 may represent an isolation layer, which covers a silicon substrate (not shown).
The wiring lines 16 may comprise any electrically conductive material such as doped polysilicon or a metal, or a metal silicide, etc. It is further possible, that wiring lines 16 include stacks of electrically conductive layers as is the case with respect to word lines in a DRAM memory. Wiring lines 16 may also represent bit lines of such a memory.
Further, voids 210-213 are formed, which are filled with air. The voids might decrease the mean dielectric constant of material within spacings 30. However, the voids are positioned irregularly and have different sizes. The amount of electromagnetic interaction between neighboring wiring lines 16 thus differs from line to line, decreasing the reliability of the integrated circuit.
Further, at the outer edge 32 of the field of wiring lines 16, an overhang 38 comprising a disadvantageously rough surface develops. A first recess 40 of layer 36 is thus performed, which removes this overhang 38 as can be seen in
The hard mask etch 46 is illustrated in
Another embodiment according to the invention is indicated in
The thickness of the deposited layer 48 of amorphous carbon in this example amounts to 190 nm. The growth behavior of amorphous carbon is almost directed upwards starting from horizontal surfaces, which are the top sections of the wiring lines 16 herein. The direction of growth deviates from a vertical axis by 40° to 70° in this embodiment at the edges of the horizontal surfaces. No growth can be seen at vertical sidewalls of the wiring lines, where there are large aspect ratios of the spacings 30 between the wiring lines. It is noted that the aspect ratio is less important here, rather the spacing between lines has a strong influence on whether the voids as shown in the figure may develop or not. In current technology nodes, the spacing between raised lines may amount to less than 150 nm, which makes it suitable for air gap formation according to embodiments of the invention.
The upwards directed growth behavior leads to the formation of voids 23 within the spacings 30. The voids 23 differ from those voids provided in the previous examples in that the spacings 30 are nearly completely kept free of any deposition material as long as the aspect ratios are sufficiently large or the width of the spacings alone amounts to less than 170-200 nm.
The deposition of amorphous carbon by means of PECVD deposition is known from U.S. Pat. No. 6,573,030 B1, to Applied Materials, Inc., Santa Clara, Calif., which is incorporated herein by reference, for the purpose of manufacturing an antireflex coating or a temporary hard mask. As described therein, a layer of amorphous carbon may be formed from a mixture of a hydrocarbon compound and an added inert gas (He or Ar). The hydrocarbon compound may be expressed as CxHy, wherein x ranges from 2 to 4, and y ranges from 2 to 10, for the compounds considered therein. An example is propylene C3H6. Ar, He or N2 are added to control the density and deposition rate of the amorphous carbon layer.
In the document cited, the following process parameters are suggested—among others—to form the layer of amorphous carbon in a PECVD process:
The parameter ranges recited herein are provided for illustration purposes only, and the invention is, however, not limited to these parameter ranges as specified above. The ranges may further depend on the specific plasma reactor, which has been used.
In a next step, as shown in
A third embodiment is shown in the sequence of
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
