The disclosure of Japanese Patent Application No. 2012-212494 filed on Sep. 26, 2012 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
The present invention relates to techniques for manufacturing semiconductor devices, and relates to a technique effectively applied to the technique for manufacturing resin-sealed semiconductor devices, for example.
Japanese Patent Laid-Open No. 2001-257291 describes a technique, in which a brazing material, such as solder, is used for coupling between one conductive path and one circuit element, while a conductive paste, such as an Ag paste, is used for coupling between the other conductive path and the other circuit element.
In Japanese Patent Laid-Open No. 2010-114454, one semiconductor chip is mounted over a wiring substrate, and the wiring substrate and one semiconductor chip are coupled to each other using a first solder. This first solder is formed by a high melting point solder (e.g., a Pb(lead)-Sn(tin) solder containing Pb(lead)) that is in a liquid state at temperatures equal to or greater than 280° C., for example. Furthermore, the other semiconductor chip is also mounted over the wiring substrate, and the wiring substrate and the other semiconductor chip are coupled to each other using a second solder. This second solder is formed, for example, by a Pb free solder (e.g., a Sn (tin)-silver (Ag)-copper (Cu) solder) which does not contain Pb(lead) that is in a liquid state at temperatures equal to or greater than 200° C.
Japanese Patent Laid-Open No. 2008-53748 describes a technique, in which a control power MOSFET chip and a synchronous power MOSFET chip are provided. Then, drain terminals on the respective rear surfaces of the control power MOSFET chip and the synchronous power MOSFET chip are bonded to an input side plate-like lead portion and an output side plate-like lead portion, respectively, via a die bonding material, such as a silver paste, for example.
A semiconductor device is formed, for example, from a semiconductor chip having a semiconductor element, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), formed therein, and a package that is formed so as to cover this semiconductor chip. The package structure of such a semiconductor device includes various types, such as a BGA (Ball Grid Array) package, a QFP (Quad Flat Package) package, and a QFN (Quad Flat Non-leaded Package) package.
Here, attention is focused on the QFN package, for example. In a technique for manufacturing the QFN package using a MAP molding technique, employed is a technique which suppresses the leakage of resin into a rear surface terminal by applying a tape to the rear surface of a substrate.
Here, for example, there may be a case where there exists a step that heats at a first temperature an adhesive for bonding a semiconductor chip to a chip mounting portion formed on the substrate. In this case, if the tape is applied to the rear surface of the substrate in advance prior to this heating step, the tape might not be able to withstand the heat treatment at the above-described first temperature when the first temperature is higher than a heat-resisting temperature of the tape.
Therefore, it can be considered that the tape is applied to the rear surface of the substrate after the above-described heating step is carried out. However, in this case, a semiconductor chip is already mounted on the upper surface side of the substrate, and thus it may be difficult to stably apply the tape to the rear surface of the substrate while supporting the upper surface side of the substrate.
The other purposes and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings.
According to an embodiment, after a heating step of heating a first conductive adhesive and a second conductive adhesive at a first temperature is carried out, a tape applying step of applying a tape to a face opposite to a face, over which a first semiconductor chip is mounted, of a first lead frame is carried out. Here, the tape applying step applies the tape to the first lead frame while supporting a first metal plate.
Moreover, according to an embodiment, after the heating step of heating the first conductive adhesive and the second conductive adhesive at the first temperature is carried out, a tape applying step of applying a tape to a face opposite to a face, over which a first semiconductor chip is mounted, of a first lead frame is carried out. Subsequently, after a second semiconductor chip is mounted onto a second chip mounting portion via a third conductivity adhesive, the third conductive adhesive is heated at a second temperature. Here, the second temperature is lower than the first temperature.
According to an embodiment, it is possible to improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate.
The following embodiments will be explained, divided into plural sections or embodiments, if necessary for convenience. Except for the case where it shows clearly in particular, they are not mutually unrelated and one has relationships such as a modification, details, and supplementary explanation of some or entire of another.
In the following embodiments, when referring to the number of elements, and the like (including the number, a numeric value, an amount, a range, and the like, they may be not restricted to the specific number but may be greater or smaller than the specific number, except for the case where they are clearly specified in particular and where they are clearly restricted to a specific number theoretically.
Furthermore, in the following embodiments, it is needless to say that an element (including an element step and the like) is not necessarily indispensable, except for the case where it is clearly instructed in particular and where it is considered to be clearly indispensable from a theoretical point of view, or the like.
Similarly, in the following embodiments, when shape, position relationship, or the like of an element or the like is referred to, what resembles or is similar to the shape substantially shall be included, except for the case where it is clearly specified in particular and where it is considered to be clearly not right from a theoretical point of view. This statement also applies to the numeric value and range described above.
In all the drawings for explaining embodiments, the same symbol is attached to the same member, as a principle, and the repeated explanation thereof is omitted. In order to make a drawing intelligible, hatching may be attached even if it is a plan view.
Moreover, a gate electrode of the High-MOS transistor QH, and a gate electrode of the Low-MOS transistor QL are coupled to a control circuit CC, and the on/off of the High-MOS transistor QH and the on/off of the Low-MOS transistor QL are controlled by the control circuit CC. Specifically, the control circuit CC controls so as to turn off the Low-MOS transistor QL in turning on the High-MOS transistor QH and turn on the Low-MOS transistor QL in turning off the High-MOS transistor QH.
Here, for example, when the High-MOS transistor QH is on and the Low-MOS transistor QL is off, a current flows from the input terminal TE1 into the load RL via the High-MOS transistor QH and the inductor L. Subsequently, if the High-MOS transistor QH is turned off and the Low-MOS transistor QL is turned on, then first because the High-MOS transistor QH is off, the current flowing from the input terminal TE1 through the High-MOS transistor QH and the inductor L to the load RL is cut off. That is, the current flowing into the inductor L is cut off. However, if the current is reduced (cut off), the inductor L attempts to maintain the current flowing therethrough. Then, because the Low-MOS transistor QL is on, the current will then flow from the ground GND through the Low-MOS transistor QL and the inductor L to the load RL. Subsequently, again, the High-MOS transistor QH is turned on and the Low-MOS transistor QL is turned off. In the step-down DC/DC converter shown in
In the following, the reason is briefly described, why the output voltage Vout lower than the input voltage Vin is output across the both ends of the load RL by repeating the above-described switching operation when the input voltage Vin is input to the input terminal TE1. Note that, in the following, it is assumed that the current flowing through the inductor L is not intermittent.
First, it is assumed that the High-MOS transistor QH performs a switching operation in an ON period TON and an OFF period TOFF under the control of the control circuit CC. The switching frequency in this case is f=1/(TON+TOFF).
Here, for example, in
First, a case where the High-MOS transistor QH is on is considered. Because it is assumed that the output voltage Vout will not fluctuate within one cycle, the voltage applied to the inductor L is (Vin-Vout) and can be regarded as constant. As a result, if the inductance of the inductor L is denoted by L1, an increment ΔIon in the current in the ON period TON is given by Formula (1).
ΔIon=(Vin−Vout)/L1×TON (1)
Next, a case where the High-MOS transistor QH is off is considered. In this case, because the Low-MOS transistor QL is on, the voltage applied to the inductor L is 0−Vout=−Vout. Accordingly, an increment ΔIOFF in the current in the OFF period TOFF is given by Formula (2).
ΔIOFF−Vout/L1×TOFF (2)
Then, in a steady state, the current flowing through the inductor L will neither increase nor decrease within one cycle of switching operation. In other words, when the current flowing through the inductor L increases or decreases within one cycle, this means the state has not reached the steady state yet. Accordingly, in the steady state, Formula (3) is satisfied.
ΔIon+ΔIOFF=0 (3)
If the relationship of Formula (1) and the relationship of Formula (2) are substituted in this Formula (3), the Formula (4) shown below can be obtained.
Vout=Vin×TON/(TON+TOFF) (4)
In this Formula (4), because TON≧0 and TOFF≧0, Vout<Vin holds. That is, the step-down DC/DC converter shown in
In this manner, with the step-down DC/DC converter shown in
<Packaging Configuration of DC/DC Converter>
The control circuit CC, the Low-MOS transistor QL, and the High-MOS transistor QH included in the above-described DC/DC converter are commercialized as a single-packaged semiconductor device, for example. This single-packaged semiconductor device, including neither the inductor L nor the capacitor C shown in
A semiconductor device is formed from a semiconductor chip having a semiconductor element, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed therein, and a package formed so as to cover this semiconductor chip. The package has a function (1) to electrically couple a semiconductor element formed in a semiconductor chip to an external circuit and a function (2) to protect a semiconductor chip from external environments, such as humidity and temperature, and prevent the damage due to vibration or impact and/or the degradation of the characteristics of the semiconductor chip. Furthermore, the package also has functions, such as a function (3) to facilitate the handling of the semiconductor chip and function (4) to radiate the heat generated during the operation of the semiconductor chip and maximize the function of the semiconductor element.
The package structure of a semiconductor device includes various types, such as a BGA (Ball Grid Array) package, a QFP (Quad Flat Package) package, and a QFN (Quad Flat Non-leaded Package) package, for example. Among such variety of packaging forms, for example, a semiconductor device constituting a part of the above-described DC/DC converter is packaged and configured as a QFN package. Then, hereinafter, the packaging configuration of a semiconductor device including a QFN package constituting a part of the DC/DC converter is described.
Next,
Subsequently, the internal configuration of the semiconductor device PK1 is described.
In the drawing shown in the center of
The lead LD is arranged on a part of the outside of the chip mounting portion TAB(L), and this lead LD and the source electrode pad SP(L) of the Low-MOS chip CHP(L) are electrically coupled to each other by the Low-MOS clip CLP(L). That is, over the source electrode pad SP(L) of the Low-MOS chip CHP(L), the Low-MOS clip CLP(L) formed by a copper material, for example, is mounted, and an end of this Low-MOS clip CLP(L) is coupled to the lead LD. Specifically, as shown in a cross-sectional view on the lower side of
Next, in the drawing shown in the center of
The chip mounting portion TAB(L) is arranged so as to be adjacent to the chip mounting portion TAB(H). This chip mounting portion TAB(L) and the source electrode pad SP(H) of the High-MOS chip CHP(H) are electrically coupled to each other by the High-MOS clip CLP(H). That is, over the source electrode pad SP(H) of the High-MOS chip CHP(H), the High-MOS clip CLP(H) formed by a copper material, for example, is mounted, and an end of this High-MOS clip CLP(H) is coupled to the chip mounting portion TAB(L). Specifically, as shown in a cross-sectional view on the left side of
Subsequently, in the drawing shown in the center of
How the semiconductor device PK1 in the present first embodiment formed in this manner constitutes a part of the DC/DC converter is described. In the drawing shown in the center of
Similarly, in the drawing shown in the center of
Here, as shown in
Then, the source electrode pad SP(L) formed on the upper surface of the Low-MOS chip CHP(L) is electrically coupled to the lead LD via the Low-MOS clip CLP(L). Therefore, by coupling the lead LD, which is electrically coupled to the Low-MOS clip CLP(L), to the ground, it is possible to couple the source region of the Low-MOS transistor QL shown in
On the other hand, the rear surface (drain electrode) of the High-MOS chip CHP(H) is electrically coupled to the chip mounting portion TAB(H) via the high melting point solder HS1. Accordingly, by electrically coupling the chip mounting position TAB(H) to the input terminal TE1, it is possible to couple the drain region (drain electrode) of the High-MOS transistor QH shown in
In the semiconductor device PK1 in the present first embodiment, for example as shown in
This is because the semiconductor device PK1 in the present first embodiment is used as a component of the DC/DC converter and a high current flows into a current path that is coupled by the Low-MOS clip CLP(L) or by the High-MOS clip CLP(H) and thus the on-resistance needs to be reduced as much as possible. That is, in the Low-MOS chip CHP(L) or the High-MOS chip CHP(H), the Low-MOS transistor QL or High-MOS transistor QH for feeding a high current is formed, and in order to make full use of the characteristics of these transistors (power transistors), the Low-MOS clip CLP(L) or the High-MOS clip CLP(H) is used instead of using a wire. In particular, for the Low-MOS clip CLP(L) and the High-MOS clip CLP(H), a copper material with a low resistivity is used and also the contact area can be increased, and therefore the on-resistances of the Low-MOS transistor QL and the High-MOS transistor QH can be reduced.
Furthermore, from a viewpoint of reducing the on-resistance, for the coupling between the chip mounting portion TAB(L) and the Low-MOS chip CHP(L) mounted over this chip mounting portion TAB(L) or for the coupling between the Low-MOS chip CHP(L) and the Low-MOS clip CLP(L), solder is used instead of a silver paste. From the similar viewpoint, for the coupling between the chip mounting portion TAB(H) and the High-MOS chip CHP(H) mounted over this chip mounting portion TAB(H) or for the coupling between the High-MOS chip CHP(H) and the High-MOS clip CLP(H), solder is used instead of a silver paste. That is, in the silver paste, a silver filler is distributed inside a thermosetting resin, and thus the electric conductivity and the heat conductivity become small as compared with the solder that is a metallic material. From this, in the semiconductor device PK1 used for the DC/DC converter requiring reduction in the on-resistance, a solder having an electric conductivity larger than that of the silver paste is used, thereby reducing the on-resistances of the Low-MOS transistor QL and the High-MOS transistor QH. In particular, in the semiconductor device PK1 in the present first embodiment, because a current is also caused to flow through the rear surface of the Low-MOS chip CHP(L) and the rear surface of the High-MOS chip CHP(H), a reduction in the connection resistance by changing from the silver paste to solder is important from the viewpoint of reducing the on-resistance.
However, after the semiconductor device PK1 in the present first embodiment is completed as a product, it is mounted onto a circuit board (mounting board). In this case, the solder is used for coupling between the semiconductor device PK1 and the mounting board. In the case of coupling by solder, a heat treatment (reflow) is required in order to melt and couple the solder.
Here, when the solder used for the connection between the semiconductor device PK1 and the mounting board and the above-described solder used inside the semiconductor device PK1 are the same material, the solder used inside the semiconductor device PK1 will be also melted due to the heat treatment (reflow) applied in coupling the semiconductor device PK1 and the mounting board. In this case, the following failures will occur: a crack is generated in the resin sealing the semiconductor device PK1 due to the volume expansion caused by melting of the solder, and the melted solder leaks to the outside.
From this, the high melting point solder HS1 or the high melting point solder HS2 is used for the connection between the chip mounting portion TAB(L) and the Low-MOS chip CHP(L) mounted over this chip mounting portion TAB(L) or for the connection between the Low-MOS chip CHP(L) and the Low-MOS clip CLP(L). Similarly, the high melting point solder HS1 or the high melting point solder HS2 is used for the connection between the chip mounting portion TAB(H) and the High-MOS chip CHP(H) mounted over this chip mounting portion TAB(H) or for the connection between the High-MOS chip CHP(H) and the High-MOS clip CLP(H). In this case, the high melting point solder HS1 or the high melting point solder HS2 used inside the semiconductor device PK1 will not be melted by the heat treatment (reflow) applied for connection between the semiconductor device PK1 and the mounting board. Accordingly, it is possible to prevent the failures, such as the one that a crack is generated in the resin sealing the semiconductor device PK1 due to the volume expansion caused by the melting of the high melting point solder HS1 or the high melting point solder HS2, and the one that the melted solder leaks to the outside.
Here, for the solder used for the connection between the semiconductor device PK1 and the mounting board, a solder represented by an Sn(tin)-silver(Ag)-copper(Cu) whose melting point is approximately 220° C., is used, and the semiconductor device PK1 is heated up to approximately 260° C. during reflow. Accordingly, for example, the high melting point solder referred to herein is intended to be a solder that will not melt even if heated up to approximately 260° C. The typical one is, for example, a solder containing 90% by weight or more of Pb(lead) whose melting point is equal to or greater than 300° C. and whose reflow temperature is approximately 350° C.
Note that, in the present first embodiment, for example, exists the high melting point solder HS1 used for the connection between the chip mounting portion TAB(L) and the Low-MOS chip CHP(L) or for the connection between the chip mounting portion TAB(H) and the High-MOS chip CHP(H). Moreover, exists the high melting point solder HS2 used for the connection between the Low-MOS chip CHP(L) and the Low-MOS clip CLP(L) or for the connection between the High-MOS chip CHP(H) and the High-MOS clip CLP(H). Basically, in the present first embodiment, it is assumed that the above-described high melting point solder HS1 and the high melting point solder HS2 have the same material component, but, for example, the high melting point solder HS1 and the high melting point solder HS2 each may be constituted by a different material component.
<Room for Improvement in Transitioning from Individual Molding Technique to MAP Molding Technique>
The packaging form of the semiconductor device PK1 in the present first embodiment is a QFN package, but in particular, the semiconductor device PK1 in the above-described present first embodiment corresponds to a form in which the package is manufactured by a MAP molding technique (MAP: Matrix Array Package, a collective molding technique).
The examples of the techniques for sealing a semiconductor chip with resin include the so-called individual molding technique for forming a sealing body for each product region provided in a substrate (a lead frame or a wiring substrate). However, in the individual molding technique, a path (a gate or a runner) for injecting resin needs to be formed for each product region and this space needs to be secured and therefore it is difficult to increase the acquisition number of products.
For this reason, in recent years, there is the a so-called MAP molding technique, in which a plurality of product regions is included in a cavity and the product regions are collectively sealed with resin. According to this MAP molding technique, the product regions can be densely arranged because there is no need to provide a path for injecting resin for each product region. Thus, according to the MAP molding technique, the acquisition number of products can be increased and thereby cost reduction of the product can be achieved.
Now, attention is focused on the QFN package employed also in the semiconductor device PK1 in the present first embodiment. For example, in transitioning from a case where a QFN package is manufactured by the individual molding technique to a case where it is manufactured by the MAP molding technique, the technique typically used in the individual molding technique cannot sufficiently correspond to this transition from a viewpoint of improving the reliability of the QFN package, and thus there is a room for improvement. This is described with reference to the accompanying drawings.
In this manner, when a QFN package is manufactured by the individual molding technique, a lead frame (substrate) can be pressed by the upper mold UM for each product region, and therefore the protruding rear surface terminal BTE formed on the rear surface of the lead frame can be caused to bite into the sheet ST arranged over the lower mold BM (sheet molding technique). Thus, in forming a QFN package using the individual molding technique, a resin leakage (resin burr) into the rear surface terminal BTE can be prevented. That is, when a QFN package is manufactured by the individual molding technique, the resin leakage into the rear surface terminal BTE can be effectively suppressed by a sheet molding technique that is typically used in the individual molding technique. As a result, the reliability of the QFN package can be increased.
Next, a case where a QFN package is manufactured by the MAP molding technique is considered.
As described above, in transitioning from a case where a QFN package is manufactured by the individual molding technique to a case where it is manufactured by the MAP molding technique, the sheet molding technique typically used in the individual molding technique cannot sufficiently correspond to this transition from a viewpoint of improving the reliability of the QFN package, and thus there is a room for improvement.
Then, when a QFN package is manufactured by the MAP molding technique, a technique replacing the sheet molding technique employed in the individual molding technique is under study. Specifically, as shown in
A configuration, in which the tape TP is applied to the rear surface of the lead frame LF in this way, is primarily intended to sufficiently suppress the resin leakage to the rear side of the rear surface terminal BTE when a QFN package is manufactured by the MAP molding technique, but also has a further advantage.
For example, attention is focused on a wire bonding step. In the case of the individual molding technique, because a space region is secured between the product regions, it is possible to carry out the wire bonding step while pressing the space region provided in a lead frame with a window clamper. Thus, the reliability of the wire bonding step can be improved.
However, in the case of the MAP molding technique, because a plurality of product regions is densely arranged, it is difficult to secure, in a lead frame, a space region sufficient for pressing with the window clamper. Then, in a lead frame corresponding to the MAP molding technique, in the wire bonding step, the lead frame is vacuum-sucked onto a heat block to be arranged, and thereby the wire bonding step is carried out while the lead frame is fixed to the heat block. In this case, because in the lead frame itself there is a region without any lead (a gap between patterns), the lead frame cannot be vacuum-sucked onto the heat block.
In contrast, in a state where the tape TP is applied to the rear surface of the lead frame, the lead frame having the tape TP applied thereto can be easily vacuum-sucked. As a result, even for a lead frame corresponding to the MAP molding technique, the wire bonding step can be carried out while the lead frame is reliably fixed by vacuum suction. As described above, the configuration, in which the tape TP is applied to the rear surface of the lead frame LF, has advantages in suppressing the resin leakage to the rear side of the rear surface terminal BTE and in increasing the easiness of the vacuum suction in the wire bonding step, in a lead frame corresponding to the MAP molding technique.
<Room for Further Improvement by Using High Melting Point Solder>
When a QFN package is manufactured by the MAP molding technique, for example, as shown in
Then, for example, consider a case where the chip mounting portion TAB and the semiconductor chip CHP are bonded together with a silver paste. The silver paste is formed by, for example, a thermosetting resin, such as an epoxy resin, dispersed with a silver filler, and is subjected to heat treatment to cure the silver paste. Accordingly, heat will be applied also to the tape TP applied to the rear surface of the lead frame LF. However, the temperature of the heat treatment for curing the silver paste is approximately 125° C. to approximately 200° C., and is lower than the heat-resisting temperature (e.g., approximately 250° C.) of the tape TP. Therefore, even if the heat treatment for curing the silver paste is carried out in the state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP can withstand the heat treatment.
However, as shown in
Specifically, the tape TP is constituted mainly by a base material part and a paste part. For the base material part of the tape TP, typically, a polyimide resin is often used and thermal decomposition temperature of the polyimide resin is equal to or greater than 500° C. Therefore, thermal decomposition temperature of the polyimide resin is higher than the reflow temperature of the above-described high melting point solder HS and therefore the base material part of the tape TP can withstand the heat in the reflow of the high melting point solder HS. On the other hand, because the heat-resisting temperature of the paste part is lower than the reflow temperature of the high melting point solder HS, this paste part cannot withstand the reflow of the high melting point solder HS. That is, the heat-resisting temperature of the tape TP means the heat-resisting temperature of the paste part constituting the tape TP.
From the above, it can be seen that when a QFN package is manufactured by the MAP molding technique, configuration is useful, in which the tape TP is applied to the rear surface of the lead frame LF, but when the high melting point solder HS is used for connection between the chip mounting portion TAB and the semiconductor chip CHP, there is a room for further improvement from a viewpoint of maintaining the heat resistance of the tape TP. In particular, in the semiconductor device PK1 of the present first embodiment used for the DC/DC converter requiring a reduction of the on-resistance, a device for maintaining the heat resistance of the tape TP is needed because a high melting point solder having an electric conductivity higher than that of the silver paste is used.
Regarding this point, in order to maintain the heat resistance of the tape TP, a technique shown below can be contemplated. That is, as shown in
In this case, unless the tape TP is applied to the rear surface of the lead frame LF in the state where the upper surface opposite to the rear surface, to which the tape TP is applied, of the lead frame LF is supported, for example, by a support member, it is difficult to firmly apply the tape TP to the rear surface of the lead frame LF. That is, if the tape TP is applied to the rear surface of the lead frame LF in the state where the upper surface opposite to the rear surface, to which the tape TP is applied, of the lead frame LF is not supported, for example, by a support member, the lead frame LF will not be fixed. Thus, it is difficult to reliably apply the tape TP to the rear surface of the lead frame LF without involving a void and the like.
However, as shown in
In summary, when a QFN package is manufactured by the MAP molding technique, a configuration in which the tape TP is applied to the rear surface of the lead frame LF, is useful. However, when the high melting point solder HS is used for connection between the chip mounting portion TAB and the semiconductor chip CHP, the configuration, in which the tape TP is applied to the rear surface of the lead frame LF in advance, has a room for improvement from a viewpoint of maintaining the heat resistance of the tape TP. Then, it is contemplated that the heat treatment (reflow) of the high melting point solder HS is carried out before the tape TP is applied to the rear surface of the lead frame LF. However, in this case, the tape TP will be applied to the rear surface of the lead frame LF in the state where the semiconductor chip CHP is mounted over the chip mounting portion TAB via the high melting point solder HS. Then, although what can be contemplated is a configuration in which the upper surface opposite to the rear surface, to which the tape TP is applied, of the lead frame LF is directly supported by a support member, the upper surface of the semiconductor chip CHP will be also supported by the support member and the pressing pressure from the support member transmits to the semiconductor chip CHP and thus the semiconductor chip CHP might be damaged. Here, there is a room for improvement.
Then, in a method of manufacturing a semiconductor device in the present first embodiment shown below, a device for the revealed room for improvement is implemented. Hereinafter, the method of manufacturing a semiconductor device in the present first embodiment implementing this device is described with reference to the accompanying drawings.
The semiconductor device in the present first embodiment is, for example, as shown in
First, as shown in
As shown in
Furthermore, in the present first embodiment, a clip subassembly CLP as shown in
Next, as shown in
The high melting point solder HS1 referred to herein is intended to be a solder that will not melt even if heated up to approximately 260° C., the examples of which include a Pb-rich high melting point solder containing a lot of Pb (lead) whose melting point is equal to or greater than 300° C. and whose reflow temperature is approximately 350° C.
Subsequently, as shown in
Next, as shown in
Specifically, for example, using a coating method, the high melting point solder HS2 is also applied over the High-MOS chip CHP(H), over the Low-MOS chip CHP(L), over a partial region of the chip mounting portion TAB(L), and over a partial region of the lead. The high melting point solder HS2 formed at this time may have the same material component as the above-described high melting point solder HS1 or may have a different material component.
Subsequently, as shown in
Note that the mounting order of the High-MOS clip CLP(H) and the Low-MOS clip CLP(L) is not limited thereto but may be changed as required.
Subsequently, a reflow is carried out with respect to the high melting point solder HS1 and the high melting point solder HS2 (S110 of
Then, in the present first embodiment, in a state where the tape is not applied to the rear surface of the lead frame LF1 that is prepared in advance, the heat treatment (reflow) for melting the high melting point solder HS1 and the high melting point solder HS2 is carried out. Accordingly, in the case of the present first embodiment, even if the reflow temperature of the high melting point solder HS1 and the high melting point solder HS2 is higher than the heat-resisting temperature of the tape, the heat resistance of the tape will not pose a problem because the tape is originally not applied to the rear surface of the lead frame LF1. That is, according to the present first embodiment, the heat treatment (reflow) of the high melting point solder HS1 and the high melting point solder HS2 is carried out before the tape is applied to the rear surface of the lead frame LF1, and therefore the heat resistance of the tape can be secured regardless of the temperature of the heat treatment (reflow).
Thereafter, in order to remove a flux contained in the high melting point solder HS1 and the high melting point solder HS2, flux cleaning is carried out (S111 of
Next, as shown in
That is, the above-described reflow temperature of the high melting point solder HS1 and the high melting point solder HS2 is approximately 350° C., for example, and exceeds the heat-resisting temperature (e.g., approximately 250° C.) of the tape TP. Therefore, if a heat treatment for melting the high melting point solder HS1 and the high melting point solder HS2 is carried out in the state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP will not be able to withstand the heat treatment. Regarding this point, in the present first embodiment, in a step prior to the step of applying the tape TP, the heat treatment (reflow) at approximately 350° C. with respect to the high melting point solder HS1 and the high melting point solder HS2 is already completed. For this reason, in the present first embodiment, the heat resistance of the tape TP will not appear as a problem.
Here, unless the tape TP is applied to the rear surface of the lead frame LF1 in the state where the upper surface opposite to the rear surface, to which the tape TP is applied, of the lead frame LF1 is supported, for example, by a support member, it might be difficult to firmly apply the tape TP to the rear surface of the lead frame LF1. That is, if the tape TP is applied to the rear surface of the lead frame LF1 in the state where the upper surface opposite to the rear surface, to which the tape TP is applied, of the lead frame LF1 is not supported, for example, by a support member, the lead frame LF1 will not be fixed. Therefore, a reaction force from the lead frame LF1 generated in applying the tape TP to the rear surface of the lead frame LF1 becomes weak. As a result, it is difficult to reliably apply the tape TP to the rear surface of the lead frame LF1 without involving a void and the like.
However, in the present first embodiment, in a step prior to the step of applying the tape TP, the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L) are already mounted over the lead frame LF1. Therefore, when the upper surface opposite to the rear surface, to which the tape TP is applied, of the lead frame LF is directly supported by a support member, the upper surface of the driver IC chip CHP(C), for example, will be also supported by the support member, and a pressing pressure from the support member transmits to the driver IC chip CHP(C) and thus the driver IC chip CHP(C) might be damaged. Here, there is a room for improvement.
Therefore, in the present first embodiment, a device for the evident room for improvement is implemented. That is, the present first embodiment is characterized in a method of fixing the lead frame LF1 in applying the tape TP to the rear surface of the lead frame LF1. This characteristic will be described later.
Subsequently, as shown in
In
Here, in the present first embodiment, because the MAP molding technique is applied to the molding step, the product regions PR are densely arranged in the lead frame LF1 shown in
Then, in the lead frame LF1 corresponding to the MAP molding technique, in the wire bonding step, the lead frame LF1 is vacuum-sucked to a heat block to be arranged, and thereby the wire bonding step will be carried out while the lead frame LF1 is fixed to the heat block. In this case, for example, when the tape TP is not applied to the rear surface of the lead frame LF1, there is a region without any lead (a gap between patterns) and therefore it is difficult to vacuum-suck and fix the lead frame LF1 over the heat block.
In contrast, according to the present first embodiment, in a step prior to carrying out the wire bonding step, the tape TP is applied to the rear surface of the lead frame LF1. Therefore, according to the present first embodiment, the lead frame LF1 having the tape TP applied thereto can be easily vacuum-sucked. As a result, even with the lead frame LF1 corresponding to the MAP molding technique, it is possible to carry out the wire bonding step while reliably fixing the lead frame LF1 by vacuum suction. As a result, according to the present first embodiment, the reliability in the wire bonding step can be improved.
Note that, the wire bonding step is carried out in the state where the lead frame LF1 is heated to approximately 200° C. to approximately 250° C., for stabilization of the joint of the wire W. However, because the heat-resisting temperature of the tape TP applied to the rear surface of the lead frame LF1 is approximately 250° C., the heat resistance of the tape TP may not pose a problem caused by the heat treatment that is applied in the wire bonding step.
Next, as shown in
Then, in the present first embodiment, in a step prior to the resin sealing step (molding step) by the MAP molding technique, the adhesive tape TP is applied to the rear surface of the lead frame LF1. Therefore, according to the present first embodiment, for example, as shown in
Note that, as the resin used in the resin sealing step, a thermosetting resin is used, for example. Therefore, the resin sealing step is carried out in a state of being heated to approximately 160° C. to approximately 200° C., in order to cure the thermosetting resin. However, because the heat-resisting temperature of the tape TP applied to the rear surface of the lead frame LF1 is approximately 250° C., the heat treatment applied in the resin sealing step may not cause a problem in the heat resistance of the tape TP.
Thereafter, the tape TP applied to the rear surface of the lead frame LF1 is peeled off from the lead frame LF1 (S116 of
Next, as shown in
Thereafter, the singulated individual semiconductor device PK1 is sorted by an electric test (S121 of
Note that, here, a case example of carrying out plasma processing shown in S112 of
Next, the features in the present first embodiment are described with reference to the accompanying drawings. As described above, the present first embodiment is characterized in the method of fixing the lead frame LF1 in applying the tape TP to the rear surface of the lead frame LF1. In particular, the technical idea in the present first embodiment is to apply a tape to the rear surface of a lead frame in the state of supporting the upper surface side of the lead frame, while reducing the damage to a semiconductor chip. Hereinafter, the technical idea in the present first embodiment is specifically described.
In the present first embodiment, the tape TP will be applied to the rear surface of the lead frame LF1 that is formed in this manner. Then, in the present first embodiment, among the faces of the lead frame LF1, the tape TP will be applied to the rear surface of the lead frame LF1 while the upper surface opposite to the rear surface, to which the tape TP is applied, is supported by a support member. Here, in the present first embodiment, although the upper surface side of the lead frame LF1 will be supported by a support member, the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L) are already mounted on the upper surface side of the lead frame LF1 as described above. Therefore, in the present first embodiment, a device is implemented to support the upper surface side of the lead frame LF1 with the support member without damaging the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L).
Here, the upper surface side of the lead frame LF1 is supported by the support member SU so that the frame portion FU contacts the partition region DIV of the lead frame LF1. Thus, the ditch DIT sandwiched by the frame portions FU will be arranged at a location where it overlaps in a planar manner with the product region PR formed in the lead frame LF1. Then, in the present first embodiment, as shown in
On the other hand, as shown in
For example, from a viewpoint of not giving a damage due to the support member SU to the Low-MOS chip CHP(L), the upper surface of the Low-MOS clip CLP(L) mounted over the Low-MOS chip CHP(L) may be configured so as not to contact the bottom surface BS of the ditch DIT provided in the support member SU. However, if such a configuration is employed, the product region PR formed in the lead frame LF1 will not be supported by the support member SU at all. That is, when the upper surface of the Low-MOS clip CLP(L) is configured so as not to contact the bottom surface BS of the ditch DIT provided in the support member SU, the upper surface side of the lead frame LF1 will be supported, only with the frame portion FU of the support member SU contacting the partition region DIV surrounding the product region PR. In this case, given that the tape TP is applied to the rear surface of the lead frame LF1, the product region PR itself will not be supported by the support member SU at all. That is, if the tape TP is applied to the rear surface of the lead frame LF1 with no support of the upper surface opposite to the rear surface, to which the tape TP is applied, of the lead frame LF1, e.g., with no support of the product region PR itself at all, then among the regions of the lead frame LF1, in particular the product region PR is unstably fixed. As a result, in the product region PR of the lead frame LF1, a reaction force from the lead frame LF1 that is generated in applying the tape TP to the rear surface of the lead frame LF1 will be significantly weak. Thus, it is difficult to reliably apply the tape TP to the rear surface of the product region PR formed in the lead frame LF1 without involving a void and the like.
Then, in the present first embodiment, as shown in
In the present first embodiment, in supporting the upper surface side of the lead frame LF1 by the support member SU, there is a gap between the bottom surface BS of the ditch DIT provided in the support member SU and the upper surface of the driver IC chip CHP(C) as shown in
Thus, because the product region PR itself formed in the lead frame LF1 is not in the state without being supported by the support member SU at all, the stability of fixing of the product region PR can be improved. As a result, also in the product region PR of the lead frame LF1, a sufficient reaction force (repulsive force) from the lead frame LF1 that is generated in applying the tape TP to the rear surface of the lead frame LF1 can be secured. Therefore, according to the present first embodiment, it is possible to reliably apply the tape TP to the rear surface of the product region PR formed in the lead frame LF1 without involving avoid and the like. That is, according to the present first embodiment, even in a state where the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L) are mounted on the upper surface side of the lead frame LF1, it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).
Here, in the present first embodiment, for example, as shown in
First, from a viewpoint of reliably supporting the product region PR itself formed in the lead frame LF1 by the support member SU, the bottom surface BS of the ditch DIT formed in the support member SU may be configured so as to contact both the upper surface of the driver IC chip CHP(C) and the upper surface of the Low-MOS clip CLP(L).
However, configuring so that the bottom surface-BS of the ditch DIT contacts the upper surface of the driver IC chip CHP(C) means that the driver IC chip CHP(C) is directly supported by the support member SU. In this case, the pressing force from the support member SU will be applied directly to the driver IC chip CHP(C), and thus the damage to the driver IC chip CHP(C) may increase. Accordingly, in the present first embodiment, for example, as shown in
On the other hand, the upper surface of the Low-MOS clip CLP(L) mounted over the Low-MOS chip CHP(L) may be also configured so as not to contact the bottom surface BS of the ditch DIT provided in the support member SU. However, if such a configuration is employed, the product region PR formed in the lead frame LF1 will not be supported by the support member SU at all. As a result, the product region PR is unstably fixed. For this reason, in the product region PR of the lead frame LF1, a reaction force from the lead frame LF1 that is generated in applying the tape TP to the rear surface of the lead frame LF1 will be significantly weak. Accordingly, it is difficult to reliably apply the tape TP to the rear surface of the product region PR formed in the lead frame LF1 without involving a void and the like.
Then, in the present first embodiment, the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the ditch DIT formed in the support member SU contacts the upper surface of the Low-MOS clip CLP(L) mounted over the Low-MOS chip CHP(L).
Here, the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the ditch DIT contacts the upper surface of the Low-MOS clip CLP(L). In this case, whether or not a damage to the Low-MOS chip CHP(L) arranged in an underlayer of the Low-MOS clip CLP(L) will pose a problem is a question. However, the Low-MOS chip CHP(L) is not configured so as to cause the bottom surface BS of the ditch DIT to directly contact the upper surface of the Low-MOS chip CHP(L), but is configured so that the Low-MOS clip CLP(L) is interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT. That is, in the Low-MOS chip CHP(L), the bottom surface BS of the ditch DIT does not directly contact the upper surface of the Low-MOS chip CHP(L). That is, in the present first embodiment, the Low-MOS clip CLP(L) interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT functions as a buffer material. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the ditch DIT contacts the Low-MOS clip CLP(L), the damage to the Low-MOS chip CHP(L) can be reduced to a level having no problem.
From the above, in the present first embodiment, there is a gap between the bottom surface BS of the ditch DIT provided in the support member SU and the upper surface of the driver IC chip CHP(C). On the other hand, the bottom surface BS of the ditch DIT formed in the support member SU is configured so as to contact the upper surface of the Low-MOS clip CLP(L) mounted over the Low-MOS chip CHP(L).
Thus, according to the present first embodiment, such a significant effect can be obtained that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR) while reducing the damage to the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L).
Here, in the configuration of the present first embodiment, because the upper surface of the driver IC chip CHP(C) is not pressed by the support member SU, the entire product region PR is not pressed by the support member SU. However, for example, as shown in
Note that, the originality of the technical idea in the present first embodiment lies, for example, as shown in
Here, from a viewpoint of sufficiently exhibiting the function as a buffer material in the Low-MOS clip CLP(L), for example, the thickness of the Low-MOS clip CLP(L) may be set as large as possible. In this case, because the cross-sectional area of the Low-MOS clip CLP(L) will also increase, the electric resistance of the Low-MOS clip CLP(L) can be reduced and thus the on-resistance of the semiconductor device PK1 in the present first embodiment can be further reduced.
<Modification 1>
Next, a Modification 1 in the present first embodiment is described.
As shown in
Then, in the present Modification 1, the upper surface of the driver IC chip CHP(C) does not directly contact the bottom surface BS of the ditch DIT provided in the support member SU but indirectly contacts the bottom surface BS of the ditch DIT via the buffer material BUF. Therefore, even when the upper surface of the driver IC chip CHP(C) is supported by the support member SU, the damage to the driver IC chip CHP(C) can be reduced to a level having no problem.
From the above, according to the present Modification 1, such a remarkable effect can be obtained that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the entire rear surface of the product region PR) while reducing the damage to the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L).
<Modification 2>
Subsequently, a Modification 2 in the present first embodiment is described.
As shown in
Modification 2, because the entire product region PR can be supported by the support member SU, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).
Then, also in the present Modification 2, the upper surface of the driver IC chip CHP(C) does not directly contact the bottom surface BS of the ditch DIT provided in the support member SU but indirectly contacts the bottom surface BS of the ditch DIT via the buffer material BUF. Therefore, even when the upper surface of the driver IC chip CHP(C) is supported by the support member SU, the damage to the driver IC chip CHP(C) can be reduced to a level having no problem.
Furthermore, in the present Modification 2, the buffer material BUF is interposed also between the upper surface of the Low-MOS clip CLP(L) and the bottom surface BS of the ditch DIT provided in the support member SU. That is, in the present Modification 2, the Low-MOS clip CLP(L) and the buffer material BUF are interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT. That is, in the present Modification 2, the Low-MOS clip CLP(L) interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT functions as a buffer material, and furthermore the buffer material BUF is also provided between the Low-MOS clip CLP(L) and the bottom surface BS of the ditch DIT. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU, the damage to the Low-MOS chip CHP(L) can be more reliably reduced to a level having no problem.
From the above, also with the present Modification 2, such a remarkable effect can be obtained that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the entire rear surface of the product region PR) while reducing the damage to the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L).
<Specific Configuration of Buffer Material>
Next, the specific configuration and advantage of the buffer material (the Low-MOS clip CLP(L) and/or the buffer material BUF) described in the above-mentioned first embodiment, the Modification 1, and the Modification 2 are described.
In
Next, in
Subsequently, in
With reference to
Then, the Low-MOS chip CHP(L) is a semiconductor chip containing silicon as a main component, and the Low-MOS clip CLP(L) is formed by a copper material, for example. Moreover, the support member SU is formed by stainless, for example.
Accordingly, when silicon, copper, and stainless are compared with regard to the modulus of longitudinal elasticity, the modulus of longitudinal elasticity of silicon is the largest, followed by the modulus longitudinal elasticity of stainless, and the modulus of longitudinal elasticity of copper is the smallest. Here, focusing on the modulus of longitudinal elasticity, the larger the modulus of longitudinal elasticity, the harder the material thereof becomes. In other words, the smaller the modulus of longitudinal elasticity, the softer the material thereof becomes. Accordingly, when silicon, copper, and stainless are compared, the hardest material is silicon, the next hardest material is stainless, and the softest material is copper.
Therefore, for example, a case where the support member SU formed by stainless is in direct contact with over the Low-MOS chip CHP(L) formed by silicon is compared with a case where the support member SU formed by stainless is arranged over the Low-MOS chip CHP(L) formed by silicon via the Low-MOS clip CLP(L) formed by copper. In this case, the latter case where the Low-MOS clip CLP(L) formed by copper is interposed can better protect the Low-MOS chip CHP(L) against a pressing force due to the support member SU than the former case. That is, because the Low-MOS clip CLP(L) is the softest, it sufficiently functions as the buffer material in the case where the Low-MOS chip CHP(L) is supported by the support member SU. As a result, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the ditch DIT contacts the Low-MOS clip CLP(L), the damage to the Low-MOS chip CHP(L) can be reduced to a level having no problem.
(2) In the Case of the Modification 1
With reference to
Then, the driver IC chip CHP(C) is a semiconductor chip containing silicon as a main component, and the buffer material BUF is formed by a rubber material, such as a polyurethane rubber, a silicon rubber (silicone rubber), and a nitrile rubber, for example. Moreover, the support member SU is formed by stainless, for example.
Accordingly, when silicon, the rubber material, and stainless are compared with regard to the modulus of longitudinal elasticity, the modulus of longitudinal elasticity of silicon is the largest, followed by the modulus of longitudinal elasticity of stainless, and the modulus of longitudinal elasticity of the rubber material is the smallest. In particular, the modulus of longitudinal elasticity of the rubber material is extremely small as compared with silicon and stainless and the rubber material is found as an extremely soft material.
Thus, because the rubber material is the softest, it sufficiently functions as the buffer material BUF in the case where the driver IC chip CHP(C) is supported by the support member SU. As a result, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the ditch DIT contacts the buffer material BUF, the damage to the driver IC chip CHP(C) can be reduced to a level having no problem.
In particular, because the rubber material used as the buffer material BUF in the Modification 1 is extremely soft, even if there is any variation in the height of the upper surface of the driver IC chip CHP(C) mounted over the chip mounting portion TAB (C) via the high melting point solder HS1, the buffer material BUF can absorb this height variation and suppress an increase of the pressing force that is applied to the driver IC chip CHP(C) more than necessary. For example, consider a case where the height of the driver IC chip CHP(C) becomes higher than an average height due to manufacturing variations of the chip mounting portion TAB (C) the high melting point solder HS1, and/or the driver IC chip CHP(C). In this case, for example, when the upper surface of the driver IC chip CHP(C) is supported by the support member SU formed by stainless, the pressing force applied to the driver IC chip CHP(C) more than necessary may increase. In contrast, when the driver IC chip CHP(C) is supported by the support member SU with the buffer material BUF interposed over the driver IC chip CHP(C), the height variations can be absorbed by the soft buffer material BUF and therefore an unnecessary increase of the pressing force applied to the driver IC chip CHP(C) can be suppressed.
(3) In the Case of the Modification 2
With reference to
Then, the Low-MOS chip CHP(L) is a semiconductor chip containing silicon as a main component and the Low-MOS clip CLP(L) is formed by copper. Moreover, the buffer material BUF is formed by a rubber material, such as a polyurethane rubber, a silicon rubber (silicone rubber), and a nitrile rubber, for example, and the support member SU is formed by stainless, for example.
Accordingly, for example, when the moduli of longitudinal elasticity of copper and the rubber material are compared, the modulus of longitudinal elasticity of the rubber material is extremely small as compared with the modulus of longitudinal elasticity of copper, and the rubber material is found to be extremely soft.
Thus, because the rubber material is the softest, it sufficiently functions as the buffer material BUF when the Low-MOS chip CHP(L) is supported by the support member SU. Asa result, even if the upper surface side of the lead frame LF1 is supported by the support member SU, the damage to the Low-MOS chip CHP(L) can be further reduced to a level having no problem than in the first embodiment including only the Low-MOS clip CLP(L) formed by copper.
In particular, the rubber material used as the buffer material BUF in the Modification 2 is extremely soft. Therefore, even if there is a variation in the height of the upper surface of the Low-MOS clip CLP(L) mounted over the Low-MOS chip CHP(L) via the high melting point solder HS2, the Low-MOS chip CHP(L) being mounted over the chip mounting portion TAB(L) via the high melting point solder HS1, the buffer material BUF can absorb this height variation and suppress an increase of the pressing force that is applied to the Low-MOS chip CHP(L) more than necessary. For example, consider a case where the height of the Low-MOS clip CLP(L) becomes higher than an average height due to manufacturing variations of the chip mounting portion TAB(C), the high melting point solder HS1, the Low-MOS chip CHP(L), the high melting point solder HS2, and/or the Low-MOS clip CLP(L). In this case, for example, when the upper surface of the Low-MOS clip CLP(L) is supported by the support member SU formed by stainless, a pressing force applied to the Low-MOS chip CHP(L) may increase more than necessary. In contrast, in supporting by the support member SU with the buffer material BUF interposed over the Low-MOS clip CLP(L), because height variations can be absorbed by the soft buffer material BUF, an unnecessary increase of the pressing force applied to the Low-MOS chip CHP(L) can be suppressed.
In a present second embodiment, a technical idea is described for manufacturing a semiconductor device using a clip frame having therein a plurality of unit regions arranged in a matrix, each unit region having the High-MOS clip and the Low-MOS clip formed therein.
The packaging configuration of a semiconductor device PK2 in the present second embodiment is substantially the same as that of the semiconductor device PK1 in the above-described first embodiment.
Next,
Subsequently, the internal configuration of the semiconductor device PK2 is described.
Here, because the internal configuration of the semiconductor device PK2 in the present second embodiment shown in
The semiconductor device PK2 in the present second embodiment is configured as described above, and hereinafter the method of manufacturing the same is described with reference to the accompanying drawings.
First, the lead frame LF1 is prepared (S201 of
Furthermore, in the present second embodiment, a clip frame CLF as shown in
Hereinafter, the detailed configuration of the clip frame CLF shown in
In the clip frame CLF in the present second embodiment, as shown in
Now, attention is focused on the lead frame LF1 shown in
That is, in the present second embodiment, the arrangement pitch in the X direction of the product regions PR formed in the lead frame LF1 and the arrangement pitch in the X direction of the unit regions UR formed in the clip frame CLF are the same. Moreover, the arrangement pitch in the Y direction of the product regions PR formed in the lead frame LF1 and the arrangement pitch in the Y direction of the unit regions UR formed in the clip frame CLF are the same.
Here, the arrangement pitch in the X direction (a first direction) of a plurality of High-MOS clips CLP(H) or Low-MOS clips CLP(L) formed in the clip frame CLF and the arrangement pitch in the Y direction (a second direction) perpendicular to the X direction are referred to as a first pitch and a second pitch, respectively.
In this case, the arrangement pitch in the X direction and the arrangement pitch in the Y direction of the chip mounting portion (the chip mounting portion TAB (C), the chip mounting portion TAB(H), and the chip mounting portion TAB(L)) formed in the lead frame LF1 are also the first pitch and the second pitch, respectively.
As a result, in the present second embodiment, each of the product regions PR formed in the lead frame LF1 and each of the unit regions UR formed in the clip frame CLF can be arranged so as to overlap with each other in a plan view. More particularly, for example, the chip mounting portion TAB(H) shown in
Next, in each of the product regions PR formed in the lead frame LF1, a high melting point solder is formed over the chip mounting portion TAB (C), the chip mounting portion TAB(H), and the chip mounting portion TAB(L) (S202 of
Subsequently, in each of the product regions PR formed in the lead frame LF1, first the driver IC chip CHP(C) is mounted over the chip mounting portion TAB (C) (S203 of
Thereafter, the lead frame LF1 is set to a positioning dedicated-jig (S206 of
Next, as shown in
Specifically, for example, using a coating method, the high melting point solder HS2 is also applied over the High-MOS chip CHP(H), over the Low-MOS chip CHP(L), over a partial region of the chip mounting portion TAB(L), and over a partial region of the lead. The high melting point solder HS2 formed at this time may have the same material component as the above-described high melting point solder HS1 or may have a different material component.
Thereafter, as shown in
That is, in the present second embodiment, the arrangement pitch in the X direction of the product regions PR formed in the lead frame LF1 and the arrangement pitch in the X direction of the unit regions UR formed in the clip frame CLF are the same. Moreover, the arrangement pitch in the Y direction of the product regions PR formed in the lead frame LF1 and the arrangement pitch in the Y direction of the unit regions UR formed in the clip frame CLF are the same.
As a result, in the present second embodiment, each of the product regions PR formed in the lead frame LF1 and each of the unit regions UR formed in the clip frame CLF can be arranged so as to overlap with each other in a plan view. More particularly, for example, the High-MOS chip CHP(H) shown in
Thus, according to the present second embodiment, simply by overlapping the lead frame LF1 with the clip frame CLF, it is possible to overlap each of the product regions PR and each of the unit regions UR with each other in a planar manner. This means that the High-MOS clip CLP(H) formed in each of the unit regions UR can be mounted over the High-MOS chip CHP(H) formed in each of the product regions PR, at once. Similarly, this means that the Low-MOS clip CLP(L) formed in each of the unit regions UR can be mounted over the Low-MOS chip CHP(L) formed in each of the product regions PR, at once. As a result, according to the present second embodiment, the manufacturing process can be simplified and thus the manufacturing cost of the semiconductor device PK2 can be reduced.
In this manner, the source electrode pad formed in the High-MOS chip CHP(H) and the chip mounting portion TAB(L) will be electrically coupled to each other by the High-MOS clip CLP(H). Moreover, the source electrode pad formed in the Low-MOS chip CHP(L) and the lead, to which the reference potential is supplied, will be electrically coupled to each other by the Low-MOS clip CLP(L).
Subsequently, a reflow is carried out with respect to the high melting point solder (e.g., high melting point solder HS2) (S210 of
Then, in the present second embodiment, a heat treatment (reflow) for melting the high melting point solder is carried out in a state where a tape is not applied to the rear surface of the lead frame LF1 that is prepared in advance. Accordingly, in the case of the present second embodiment, even if the reflow temperature of the high melting point solder is higher than the heat-resisting temperature of the tape, the heat resistance of the tape will not pose a problem because the tape is originally not applied to the rear surface of the lead frame LF1. That is, according to the present second embodiment, because the heat treatment (reflow) of the high melting point solder is carried out before the tape is applied to the rear surface of the lead frame LF1, the heat resistance of the tape can be secured regardless of the temperature of the heat treatment (reflow).
Thereafter, flux cleaning is carried out in order to remove the flux contained in the high melting point solder (S211 of
Next, as shown in
That is, the reflow temperature of the above-described high melting point solder is, for example, approximately 350° C., and exceeds the heat-resisting temperature (e.g., approximately 250° C.) of the tape TP. Therefore, if the heat treatment for melting the high melting point solder is carried out in the state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP will not be able to withstand the heat treatment. Regarding this point, in the present second embodiment, in a step prior to the step of applying the tape TP, the heat treatment (reflow) at approximately 350° C. with respect to the high melting point solder is already complete. For this reason, in the present second embodiment, the heat resistance of the tape TP will not appear as a problem.
Subsequently, as shown in
In
Here, according to the present second embodiment, the tape TP is applied to the rear surface of the lead frame LF1 in a step prior to carrying out the wire bonding step. Therefore, according to the present second embodiment, the lead frame LF1 having the tape TP applied thereto can be easily vacuum-sucked. As a result, even with the lead frame LF1 corresponding to the MAP molding technique, it is possible to carry out the wire bonding step while reliably fixing the lead frame LF1 by vacuum suction. As a result, according to the present second embodiment, the reliability in the wire bonding step can be improved.
Note that, the wire bonding step is carried out in the state where the lead frame LF1 is heated to approximately 200° C. to approximately 250° C., for stabilization of the joint of the wire W. However, because the heat-resisting temperature of the tape TP applied to the rear surface of the lead frame LF1 is approximately 250° C., the heat treatment applied in the wire bonding step may not cause a problem in the heat resistance of the tape TP.
Next, the product regions formed in the lead frame LF1 are collectively sealed (molded) with the resin (S215 of
Then, in the present second embodiment, in a step prior to the resin sealing step (molding step) by the MAP molding technique, the adhesive tape TP is applied to the rear surface of the lead frame LF1. Therefore, according to the present second embodiment, the tape TP can be reliably applied to the rear surface terminal (lead) formed on the rear surface of the lead frame LF1. As a result, also in the resin sealing step employing the MAP molding technique, a gap is not formed between the rear surface terminal and the tape TP and thus the resin leakage (resin burr) into the rear surface of the rear surface terminal can be sufficiently suppressed.
Note that, as the resin used in the resin sealing step, a thermosetting resin is used, for example. Therefore, the resin sealing step is carried out in a state of being heated to approximately 160° C. to approximately 200° C., in order to cure the thermosetting resin. However, because the heat-resisting temperature of the tape TP applied to the rear surface of the lead frame LF1 is approximately 250° C., the heat treatment applied in the resin sealing step may not cause a problem in the heat resistance of the tape TP.
Thereafter, the tape TP applied to the rear surface of the lead frame LF1 is peeled off from the lead frame LF1 (S216 of
Subsequently, a dicing tape is applied to the upper surface of the sealing body formed by the resin (S219 of
Thereafter, the singulated individual semiconductor device PK2 is sorted by an electric test (S221 of
Next, the features in the present second embodiment are described with reference to the accompanying drawings. The present second embodiment is characterized in the method of fixing the lead frame LF1 in applying the tape TP to the rear surface of the lead frame LF1. In particular, the technical idea in the present second embodiment is to apply a tape to the rear surface of a lead frame in the state where the upper surface side of the lead frame is supported, while reducing the damage to a semiconductor chip. Hereinafter, the technical idea in the present second embodiment is specifically described.
Here, above the partition region DIV of the lead frame LF1, the partition region DIV2 of the clip frame CLF is arranged, and the upper surface side of the lead frame LF1 is supported by the support member SU so that this partition region DIV2 contacts the support member SU. Thus, the ditch DIT of the support member SU will be arranged at a location where it overlaps with the product region PR formed in the lead frame LF1 in a planar manner. Then, in the present second embodiment, as shown in
On the other hand, as shown in
Thus, because the product region PR itself formed in the lead frame LF1 is not in the state without being supported by the support member SU at all, the stability of fixing of the product region PR can be improved. As a result, also in the product region PR of the lead frame LF1, a sufficient reaction force (repulsive force) from the lead frame LF1 generated in applying the tape TP to the rear surface of the lead frame LF1 can be secured. Therefore, according to the present second embodiment, it is possible to reliably apply the tape TP to the rear surface of the product region PR formed in the lead frame LF1 without involving a void and the like. That is, according to the present second embodiment, even in a state where the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L) are mounted on the upper surface side of the lead frame LF1, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).
Here, the Low-MOS chip CHP(L) is not configured so as to cause the bottom surface BS of the ditch DIT to directly contact the upper surface of the Low-MOS chip CHP(L), but is configured so that the Low-MOS clip CLP(L) is interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT. That is, in the Low-MOS chip CHP(L), the bottom surface BS of the ditch. DIT does not directly contact the upper surface of the Low-MOS chip CHP(L). That is, in the present second embodiment, the Low-MOS clip CLP(L) interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT functions as a buffer material. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the ditch DIT contacts the Low-MOS clip CLP(L), the damage to the Low-MOS chip CHP(L) can be reduced to a level having no problem.
From the above, also in the present second embodiment, as with the above-described first embodiment, there is a gap between the bottom surface BS of the ditch DIT provided in the support member SU and the upper surface of the driver IC chip CHP(C). On the other hand, the bottom surface BS of the ditch DIT formed in the support member SU contacts the upper surface of the Low-MOS clip CLP(L) mounted over the Low-MOS chip CHP(L).
Thus, according to the present second embodiment, such a remarkable effect can be obtained that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR) while reducing the damage to the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L).
<Modification 1>
Next, a Modification 1 in the present second embodiment is described.
As shown in
Then, in the present Modification 1, the upper surface of the driver IC chip CHP(C) does not directly contact the bottom surface BS of the ditch DIT provided in the support member SU but indirectly contacts the bottom surface BS of the ditch DIT via the buffer material BUF. Therefore, even when the upper surface of the driver IC chip CHP(C) is supported by the support member SU, the damage to the driver IC chip CHP(C) can be reduced to a level having no problem.
From the above, according to the present Modification 1, such a remarkable effect can be obtained that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the entire rear surface of the product region PR) while reducing the damage to the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L).
<Modification 2>
Subsequently, a Modification 2 in the present second embodiment is described.
As shown in
Then, also in the present Modification 2, the upper surface of the driver IC chip CHP(C) does not directly contact the bottom surface BS of the ditch DIT provided in the support member SU but indirectly contacts the bottom surface BS of the ditch DIT via the buffer material BUF. Therefore, even when the upper surface of the driver IC chip CHP(C) is supported by the support member SU, the damage to the driver IC chip CHP(C) can be reduced to a level having no problem.
Furthermore, in the present Modification 2, the buffer material BUF is interposed also between the upper surface of the Low-MOS clip CLP(L) and the bottom surface BS of the ditch DIT provided in the support member SU. That is, in the present Modification 2, the Low-MOS clip CLP(L) and the buffer material BUF are interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT. That is, in the present Modification 2, the Low-MOS clip CLP(L) interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT functions as a buffer material, and furthermore the buffer material BUF is also provided between the Low-MOS clip CLP(L) and the bottom surface BS of the ditch DIT. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU, the damage to the Low-MOS chip CHP(L) can be further reduced to a level having no problem.
From the above, also with the present Modification 2, such a remarkable effect can be obtained that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the entire rear surface of the product region PR) while reducing the damage to the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L).
Also in a present third embodiment, the high melting point solder HS1 is used for the connection between the chip mounting portion TAB(H) and the High-MOS chip CHP(H) and for the connection between the chip mounting portion TAB(L) and the Low-MOS chip CHP(L). On the other hand, in the present third embodiment described is an example, in which the silver paste PST is used for the connection between the chip mounting portion TAB (C) and the driver IC chip CHP(C).
Because the packaging configuration of a semiconductor device in the present third embodiment is substantially the same as that of the semiconductor device PK2 in the above-described second embodiment, the description is provided focusing on differences.
In
Here, also in the present third embodiment, as shown in
The semiconductor device in the present third embodiment is configured as described above, and hereinafter the method of manufacturing a semiconductor device in the present third embodiment is described with reference to the accompanying drawings.
First, the lead frame LF1 is prepared (S301 of
Furthermore, also in the present third embodiment, as with the above-described second embodiment, the clip frame CLF as shown in
Here, for example, as shown in
Next, as shown in
Next, as shown in
Thereafter, the lead frame LF1 is set to the positioning dedicated-jig (S305 of
Next, as shown in
Specifically, for example, using a coating method, the high melting point solder HS2 is also applied over the High-MOS chip CHP(H), over the Low-MOS chip CHP(L), over the partial region of the chip mounting portion TAB(L), and over the partial region of the lead. The high melting point solder HS2 formed at this time may have the same material component as that of the above-described high melting point solder HS1, or may have a different material component.
Thereafter, as shown in
Thus, according to the present third embodiment, simply by overlapping the lead frame LF1 with the clip frame CLF, it is possible to overlap each of the product regions PR and each of the unit regions UR with each other in a planar manner. This means that the High-MOS clip CLP(H) formed in each of the unit regions UR can be mounted over the High-MOS chip CHP(H) formed in each of the product regions PR, at once. Similarly, this means that the Low-MOS clip CLP(L) formed in each of the unit regions UR can be mounted over the Low-MOS chip CHP(L) formed in each of the product regions PR, at once. As a result, according to the present third embodiment, the manufacturing process can be simplified and thus the manufacturing cost of the semiconductor device PK3 can be reduced.
In this manner, the source electrode pad formed in the High-MOS chip CHP(H) and the chip mounting portion TAB(L) will be electrically coupled to each other by the High-MOS clip CLP(H). Moreover, the source electrode pad formed in the Low-MOS chip CHP(L) and the lead, to which the reference potential is supplied, will be electrically coupled to each other by the Low-MOS clip CLP(L).
Subsequently, the reflow is carried out with respect to the high melting point solder HS1 and the high melting point solder HS2 (S309 of
Then, in the present third embodiment, a heat treatment (reflow) for melting the high melting point solder HS1 and the high melting point solder HS2 is carried out in a state where a tape is not applied to the rear surface of the lead frame LF1 that is prepared in advance. Accordingly, in the case of the present third embodiment, even if the reflow temperature of the high melting point solder HS1 and the high melting point solder HS2 is higher than the heat-resisting temperature of the tape, the heat resistance of the tape will not pose a problem because the tape is originally not applied to the rear surface of the lead frame LF1. That is, according to the present third embodiment, because the heat treatment (reflow) of the high melting point solder is carried out before the tape is applied to the rear surface of the lead frame LF1, the heat resistance of the tape can be secured regardless of the temperature of the heat treatment (reflow).
Thereafter, in order to remove the flux contained in the high melting point solder HS1 and the high melting point solder HS2, flux cleaning is carried out (S310 of
Next, as shown in
That is, the reflow temperature of the above-described high melting point solder HS1 and high melting point solder HS2 is approximately 350° C., for example, and exceeds the heat-resisting temperature (e.g., approximately 250° C.) of the tape TP. Therefore, if the heat treatment for melting the high melting point solder HS1 and the high melting point solder HS2 is carried out in the state where the tape TP is applied to the rear surface of the lead frame LF, the tape TP will not be able to withstand the heat treatment. Regarding this point, in the present third embodiment, in a step prior to the step of applying the tape TP, the heat treatment (reflow) at approximately 350° C. with respect to the high melting point solder HS1 and the high melting point solder HS2 is already completed. For this reason, in the present third embodiment, the heat resistance of the tape TP will not appear as a problem.
Here, in the present third embodiment, in carrying out the step of applying the tape TP to the current rear surface of the lead frame LF1, the driver IC chip CHP(C) has not been mounted over the chip mounting portion TAB (C) yet. For this reason, in the present third embodiment, the chip mounting portion TAB(C), in which the driver IC chip CHP(C) is not mounted, can be also pressed. Therefore, the present third embodiment is characterized in that the region for pressing the lead frame LF1 increases and thus the tape TP can be reliably applied to the rear surface of the lead frame LF1. The detail of this feature is described later.
Subsequently, as shown in
Next, as shown in
That is, in the present third embodiment, in a step after applying the tape TP to the rear surface of the lead frame LF1, the driver IC chip CHP(C) is mounted over the chip mounting portion TAB (C). The purpose of this is to support the chip mounting portion TAB (C) itself without damaging the driver IC chip CHP(C), by configuring such that in applying the tape TP to the rear surface of the lead frame LF1, the driver IC chip CHP(C) is not yet mounted over the chip mounting portion TAB (C) at this stage.
That is, in the present third embodiment, in applying the tape TP to the rear surface of the lead frame LF1, the mounting of the driver IC chip CHP(C) to the chip mounting portion TAB (C) is carried out in a step after applying the tape TP to the rear surface of the lead frame LF1 so that the upper surface itself of the chip mounting portion TAB (C) can be also pressed. Thus, according to the present third embodiment, because the area for supporting the upper surface side of the lead frame LF1 can be increased, the tape TP can be reliably applied to the rear surface of the lead frame LF1.
In the case of this configuration, if the high melting point solder HS1 is used for the connection between the chip mounting portion TAB (C) and the driver IC chip CHP(C), the heat treatment (reflow) applied to the high melting point solder HS1 will cause a problem in the heat resistance of the tape TP. Then, in the present third embodiment, the silver paste PST is used for the connection between the chip mounting portion TAB(C) and the driver IC chip CHP(C).
In this case, the heat treatment (bake treatment) is carried out in order to cure the silver paste PST, and this heat treatment is carried out at approximately 125° C. to approximately 200° C., for example. On the other hand, because the tape TP is already applied to the rear surface of the lead frame LF1 and the heat-resisting temperature of this tape TP is approximately 250° C., the heat treatment applied in the curing step of the silver paste PST does not cause a problem in the heat resistance of the tape TP.
As described above, in the present third embodiment, in applying the tape TP to the rear surface of the lead frame LF1, the mounting of the driver IC chip CHP(C) to the chip mounting portion TAB(C) is carried out in a step after applying the tape TP to the rear surface of the lead frame LF1 so that the upper surface itself of the chip mounting portion TAB(C) can be also pressed. Then, taking into consideration a fact that if the high melting point solder HS1 is used for the connection between the chip mounting portion TAB(C) and the driver IC chip CHP(C), then the heat treatment (reflow) applied to the high melting point solder HS1 causes a problem in the heat resistance of the tape TP, the silver paste PST is used for the connection between the chip mounting portion TAB(C) and the driver IC chip CHP(C).
Here, even if not the high melting point solder HS1, but the silver paste PST, is used for the connection between the chip mounting portion TAB (C) and the driver IC chip CHP(C), there is no problem in the characteristics. Hereinafter, the reason for this is described. For example, a power MOSFET is formed inside the High-MOS chip CHP(H) and inside the Low-MOS chip CHP(L), and the rear surface of the chip functions as a drain electrode (drain region) of this power MOSFET. Therefore, in order to reduce the on-resistance, the high melting point solder HS1 having a low electric resistance needs to be used for a connection member that connects the rear surface of the High-MOS chip CHP(H) or of the Low-MOS chip CHP(L) to the chip mounting portion (the chip mounting portion TAB(H) or the chip mounting portion TAB(L)).
On the other hand, in the driver IC chip CHP(C), although a MOSFET (field effect transistor) and a wiring layer constituting the control circuit CC are formed, a power MOSFET is not formed and thus the rear surface of the driver IC chip CHP(C) is not used as the drain electrode. That is, a current does not flow through the rear surface of the driver IC chip CHP(C). Therefore, in the driver IC chip CHP(C), the necessity for reduction of the on-resistance is lower than in the High-MOS chip CHP(H) and in the Low-MOS chip CHP(L). That is, in the driver IC chip CHP(C), for the connection between the chip mounting portion TAB (C) and the rear surface of the driver IC chip CHP(C), the high melting point solder HS1 does not necessarily need to be used and the silver paste PST is enough for this purpose.
Focusing on this fact, in the present third embodiment the high melting point solder HS1 is not used for the connection between the chip mounting portion TAB (C) and the driver IC chip CHP(C), but the silver paste PST is used for the connection between the chip mounting portion TAB(C) and the driver IC chip CHP(C). As a result, according to the present third embodiment, because the heat resistance of the tape TP can be secured, the driver IC chip CHP(C) can be mounted over the chip mounting portion TAB (C) in a step after applying the tape TP to the rear surface of the lead frame LF1.
This means that in applying the tape TP to the rear surface of the lead frame LF1, the driver IC chip CHP(C) can be configured so as not to be mounted over the chip mounting portion TAB (C) at this stage. Thus, according to the present third embodiment, it is possible to support the chip mounting portion TAB(C) itself without damaging the driver IC chip CHP(C). Therefore, according to the present third embodiment, the area for supporting the upper surface side of the lead frame LF1 can be increased and thus the tape TP can be reliably applied to the rear surface of the lead frame LF1.
Subsequently, as with the above-described second embodiment, the wire bonding step is carried out (S316 of
Note that, the wire bonding step is carried out in the state where the lead frame LF1 is heated to approximately 200° C. to approximately 250° C. for stabilization of the joint of the wire W. However, because the heat-resisting temperature of the tape TP applied to the rear surface of the lead frame LF1 is approximately 250° C., the heat treatment applied in the wire bonding step may not cause a problem in the heat resistance of the tape TP.
Here, in the present third embodiment, in a step after carrying out the flux cleaning, the driver IC chip CHP(C) is mounted over the chip mounting portion TAB (C), and in the subsequent step a wire is bonded to an electrode pad formed in the driver IC chip CHP(C). One of the characteristics of the present third embodiment is such a process order.
That is, as the cleaning fluid used in the flux cleaning, a cleaning fluid containing hydrocarbon is used, for example. At this time, if the flux cleaning step is carried out at a stage after the driver IC chip CHP(C) is mounted over the chip mounting portion TAB(C), the electrode pad formed in the driver IC chip CHP(C) will be exposed to the cleaning fluid. As a result, the electrode pad formed in the driver IC chip CHP(C) will be contaminated by the cleaning fluid, which might adversely affect the coupling between these electrode pad and wire.
In contrast, in the present third embodiment, in a step after carrying out the flux cleaning, the driver IC chip CHP(C) is mounted over the chip mounting portion TAB (C). Therefore, there is no need to worry about the contamination of the electrode pad formed in the driver IC chip CHP(C) due to the cleaning fluid used in the flux cleaning. That is, according to the present third embodiment, because there is no adverse effect on the electrode pad formed in the driver IC chip CHP(C) due to the flux cleaning, the reliability of coupling between the electrode pad formed in the driver IC chip CHP(C) and the wire can be improved.
Next, the product regions formed in the lead frame LF1 are collectively sealed (molded) by a resin (S317 of
Then, in the present third embodiment, in a step prior to the resin sealing step (molding step) by the MAP molding technique, the adhesive tape TP is applied to the rear surface of the lead frame LF1. Therefore, according to the present third embodiment, the tape TP can be reliably applied to the rear surface terminal (lead) formed in the rear surface of the lead frame LF1. As a result, also in the resin sealing step employing the MAP molding technique, a gap is not formed between the rear surface terminal and the tape TP and thus the resin leakage (resin burr) into the rear side of the rear surface terminal can be sufficiently suppressed.
Note that, as the resin used in the resin sealing step, a thermosetting resin is used, for example. Therefore, the resin sealing step is carried out in a state of being heated to approximately 160° C. to approximately 200° C., in order to cure the thermosetting resin. However, because the heat-resisting temperature of the tape TP applied to the rear surface of the lead frame LF1 is approximately 250° C., the heat treatment applied in the resin sealing step may not cause a problem in the heat resistance of the tape TP.
Thereafter, the tape TP applied to the rear surface of the lead frame LF1 is peeled off from the lead frame LF1 (S318 of
Subsequently, a dicing tape is applied to the upper surface of the sealing body formed by the resin (S321 of FIG. 50). Then, the sealing body formed by the resin is cut for each product region (package dicing) (S322 of
Thereafter, the singulated individual semiconductor device PK3 is sorted by an electric test (S323 of
Note that, in the present third embodiment, for example, an example using the clip frame CLF shown in
Next, the features in the present third embodiment are described with reference to the accompanying drawings. The present third embodiment is characterized in the method of fixing the lead frame LF1 in applying the tape TP to the rear surface of the lead frame LF1. In particular, the technical idea in the present third embodiment is that after applying the tape TP to the rear surface of the lead frame LF1, the driver IC chip CHP(C) is mounted over the chip mounting portion TAB(C) so as to be able to press the top of the chip mounting portion TAB(C) by the support member SU. Hereinafter, the technical idea in the present third embodiment is specifically described.
In the present third embodiment, the clip frame CLF is mounted so as to overlap with the lead frame LF1 in a planar manner. In this clip frame CLF, the unit regions UR are arranged in a matrix, and each of the unit regions UR is partitioned by a partition region (boundary region) DIV2. Now, attention is focused on each of the unit regions UR. The High-MOS clip CLP(H) and the Low-MOS clip CLP(L) are arranged in each of the unit regions UR. Thus, in the present third embodiment, the High-MOS clip CLP(H) is arranged so as to span from over the High-MOS chip CHP(H) to over the chip mounting portion TAB(L), and the Low-MOS clip CLP(L) is arranged so as to span from over the Low-MOS chip CHP(L) to over the lead. Then, the High-MOS clip CLP(H) and the Low-MOS clip CLP(L) are coupled to the partition region DIV2 of the clip frame CLF by the suspension lead HL.
Here, above the partition region DIV of the lead frame LF1, the partition region DIV2 of the clip frame CLF is arranged, and the upper surface side of the lead frame LF1 is supported by the support member SU so that this partition region DIV2 contacts the support member SU. Thus, the ditch DIT of the support member SU will be arranged at a location where it overlaps with the product region PR formed in the lead frame LF1 in a planar manner.
Then, in the present third embodiment, as shown in
Thus, the following effects can be obtained. That is, over the chip mounting portion TAB(C), the driver IC chip CHP(C) is mounted in a subsequent step. In this driver IC chip CHP(C), a large number of electrode pads are formed, and a wire is electrically coupled to these electrode pads in the wire bonding step. This wire bonding step is carried out while vacuum-sucking the lead frame LF1 to a heat block, for example. At this time, for example, if the adhesion between the chip mounting portion TAB(C) and the tape TP is insufficient due to a sandwiched void (air bubble) and the like, then the chip mounting portion TAB(C) cannot be securely fixed, and also the transmission of ultrasonic vibration used in the wire bonding step cannot be sufficiently realized and thus the reliability of wire connection to the driver IC chip CHP(C) might be reduced.
Regarding this point, in the present third embodiment, particularly because the chip mounting portion TAB(C) is directly pressed by the protrusion PJN, a sufficient reaction force (repulsive force) can be obtained from the chip mounting portion TAB(C) side in applying the tape TP to the rear surface of the chip mounting portion TAB (C). As a result, according to the present third embodiment, the tape TP can be reliably applied to the rear surface of the chip mounting portion TAB (C). Thus, according to the present third embodiment, also in the wire bonding step, the chip mounting portion TAB(C) can be securely fixed to the heat block, and the transmission of ultrasonic vibration can be also sufficiently realized and the reliability of wire connection to the driver IC chip CHP(C) can be improved.
In particular, the present third embodiment has an advantage in pressing the chip mounting portion TAB (C), over which the driver IC chip CHP(C) is to be mounted, by the protrusion PJN. This is because among the High-MOS chip CHP(H), the Low-MOS chip CHP(L), and the driver IC chip CHP(C), the number of electrode pads formed in the driver IC chip CHP(C) is the largest and thus the wire connection reliability in the wire bonding step here is important. Also from this point, the configuration of the present third embodiment, in which the chip mounting portion TAB(C) on which the driver IC chip CHP(C) is to be mounted is directly pressed by the protrusion PJN, is highly advantageous.
On the other hand, also in the present third embodiment, as shown in
Because this increases the area for supporting the product region PR formed in the lead frame LF1, the stability in fixing the product region PR can be improved. As a result, also in the product region PR of the lead frame LF1, a sufficient reaction force (repulsive force) from the lead frame LF1 generated in applying the tape TP to the rear surface of the lead frame LF1 can be secured. Therefore, according to the present third embodiment, it is possible to reliably apply the tape TP to the rear surface of the product region PR formed in the lead frame LF1 without involving a void and the like. That is, according to the present third embodiment, even in a state where the High-MOS chip CHP(H) and the Low-MOS chip CHP(L) are mounted on the upper surface side of the lead frame LF1, the tape TP can be reliably applied to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR).
Here, the Low-MOS chip CHP(L) is not configured so as to cause the bottom surface BS of the ditch DIT to directly contact the upper surface of the Low-MOS chip CHP(L) but is configured so that the Low-MOS clip CLP(L) is interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT. That is, in the Low-MOS chip CHP(L), the bottom surface BS of the ditch DIT does not directly contact the upper surface of the Low-MOS chip CHP(L). That is, in the present third embodiment, the Low-MOS clip CLP(L) interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT functions as a buffer material. For this reason, even if the upper surface side of the lead frame LF1 is supported by the support member SU so that the bottom surface BS of the ditch DIT contacts the Low-MOS clip CLP(L), the damage to the Low-MOS chip CHP(L) can be reduced to a level having no problem.
From the above, in the present third embodiment, the protrusion PJN protruding from the ditch DIT is configured so as to directly press the chip mounting portion TAB(C). Furthermore, in the present third embodiment, the bottom surface BS of the ditch DIT formed in the support member SU contacts the upper surface of the Low-MOS clip CLP(L) mounted over the Low-MOS chip CHP(L).
Thus, according to the present third embodiment, such a remarkable effect that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the rear surface of the product region PR) while reducing the damage to the High-MOS chip CHP(H) and the Low-MOS chip CHP(L), can be obtained.
<Modification>
Subsequently, a modification in the present third embodiment is described.
As shown in
From the above, also with the present modification, such a remarkable effect that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF1 (in particular, to the entire rear surface of the product region PR) while reducing the damage to the High-MOS chip CHP(H) and the Low-MOS chip CHP(L), can be obtained.
In the above-described first embodiment to third embodiment, a semiconductor device, in which the driver IC chip CHP(C), the High-MOS chip CHP(H), and the Low-MOS chip CHP(L) are sealed by a sealing body, has been described, but the technical idea in the above-described first embodiment to third embodiment can be also applied, for example, to a semiconductor device, in which the High-MOS chip CHP(H) and the Low-MOS chip CHP(L) are sealed by a sealing body.
In the present fourth embodiment, the tape TP will be applied to the rear surface of the lead frame LF2 configured in this manner.
Then, in the present fourth embodiment, among the faces of the lead frame LF2, the tape TP will be applied to the rear surface of the lead frame LF2 while the upper surface opposite to the rear surface, to which the tape TP is applied, is supported by a support member. Here, in the present fourth embodiment, the upper surface side of the lead frame LF2 will be supported by the support member, but the High-MOS chip CHP(H) and the Low-MOS chip CHP(L) are already mounted on the upper surface side of the lead frame LF2 as described above. Therefore, also in the present fourth embodiment, as with the above-described first embodiment to the present third embodiment, the upper surface side of the lead frame LF2 needs to be supported by the support member without damaging the High-MOS chip CHP(H) and the Low-MOS chip CHP(L).
As shown in
Similarly, in the present fourth embodiment, the buffer material BUF is interposed also between the upper surface of the Low-MOS clip CLP(L) and the bottom surface BS of the ditch DIT provided in the support member SU. That is, in the present fourth embodiment, the Low-MOS clip CLP(L) and the buffer material BUF are interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT. That is, in the present fourth embodiment, the Low-MOS clip CLP(L) interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT functions as a buffer material, and furthermore the buffer material BUF is also provided between the Low-MOS clip CLP(L) and the bottom surface BS of the ditch DIT. For this reason, even if the upper surface side of the lead frame LF2 is supported by the support member SU, the damage to the Low-MOS chip CHP(L) can be further reduced to a level having no problem.
From the above, also with the present fourth embodiment, such a remarkable effect that it is possible to reliably apply the tape TP to the rear surface of the lead frame LF2 (in particular, to the entire rear surface of the product region PR) while reducing the damage to the High-MOS chip CHP(H) and the Low-MOS chip CHP(L), can be obtained.
Note that, in the present fourth embodiment, an example using the buffer material BUF has been described, but as with the above-described first embodiment, without using the buffer material BUF, the bottom surface BS of the ditch DIT may be configured so as to contact the top of the High-MOS clip CLP(H) and the top of the Low-MOS clip CLP(L).
Subsequently, as shown in
<Modification 1>
A Modification 1, as with the fourth embodiment, is also directed to a semiconductor device, in which the High-MOS chip CHP(H) and the Low-MOS chip CHP(L) are sealed by a sealing body, but in particular in the present Modification 1, an example, in which the High-MOS clip CLP(H) is not mounted over the High-MOS chip CHP(H), is described.
In the present Modification 1, the tape TP will be applied to the rear surface of, the lead frame LF2 configured in this manner.
Then, in the present Modification 1, among the faces of the lead frame LF2, the tape TP will be applied to the rear surface of the lead frame LF2 while the upper surface opposite to the rear surface, to which the tape TP is applied, is supported by a support member. Here, in the present Modification 1, although the upper surface side of the lead frame LF2 will be supported by a support member, the driver IC chip CHP(C) is already mounted on the upper surface side of the lead frame LF2 as described above. Therefore, also in the present Modification 1, the upper surface side of the lead frame LF2 needs to be supported by a support member without damaging the Low-MOS chip CHP(L).
Furthermore, in the present Modification 1, the buffer material BUF is interposed also between the upper surface of the Low-MOS clip CLP(L) and the bottom surface BS of the ditch DIT provided in the support member SU. That is, in the present Modification 1, the Low-MOS clip CLP(L) and the buffer material BUF are interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT. That is, in the present Modification 1, the Low-MOS clip CLP(L) interposed between the Low-MOS chip CHP(L) and the bottom surface BS of the ditch DIT functions as a buffer material, and furthermore the buffer material BUF is also provided between the Low-MOS clip CLP(L) and the bottom surface BS of the ditch DIT. For this reason, even if the upper surface side of the lead frame LF2 is supported by the support member SU, the damage to the Low-MOS chip CHP(L) can be reduced to a level having no problem.
Note that, also in the present Modification 1, an example using the buffer material BUF has been described, but for example, without using the buffer material BUF, the bottom surface BS of the ditch DIT may be configured so as to contact the top of the Low-MOS clip CLP(L).
Subsequently, in each of the product regions PR formed in the lead frame LF2, a silver plate is applied over the chip mounting portion TAB(H). Then, as shown in
<Modification 2>
In a Modification 2 is described a semiconductor device, in which for example a single semiconductor chip having a power MOSFET (a switching field effect transistor) formed therein is sealed by a sealing body.
In the present Modification 2, the tape TP will be applied to the rear surface of the lead frame LF3 configured in this manner.
Then, in the present Modification 2, among the faces of the lead frame LF3, the tape TP will be applied to the rear surface of the lead frame LF3 in a state where the upper surface opposite to the rear surface, to which the tape TP is applied, is supported by a support member. Here, in the present Modification 2, the upper surface side of the lead frame LF3 will be supported by a support member, but the semiconductor chip CHP2 is already mounted on the upper surface side of the lead frame LF3 as described above. Therefore, also in the present Modification 2, the upper surface side of the lead frame LF3 needs to be supported by a support member without damaging the semiconductor chip CHP2.
Note that, also in the present Modification 2, an example using buffer material BUF has been described, but for example, without using the buffer material BUF, the bottom surface BS of the ditch DIT may be configured so as to contact the top of the clip CLP2.
Thereafter, as shown in
The present invention of the present inventors has been described specifically according to the embodiments. However, it is obvious that the present invention is not limited to the embodiments, but various modifications are possible without departing from the scope of the invention.
Number | Date | Country | Kind |
---|---|---|---|
2012-212494 | Sep 2012 | JP | national |
Number | Date | Country | |
---|---|---|---|
Parent | 14037360 | Sep 2013 | US |
Child | 14685145 | US |