Patent Application
20140097907
1. Field of the Invention
The present invention relates to a micro CMOS power amplifier, in which an output transformer is configured as a substrate of a multilayer structure, and an amplifier circuit module is stacked on the output transformer.
2. Background of the Related Art
Generally, low power, low price, small size, high data rate, soft defined radio (SDR, a function of supporting multiple standards) and the like are items required for wireless terminals. From the viewpoint of power amplifier design, external surface mounting (SMT) components are developed so as to be embedded in a main RF chip if possible while reducing the number of the SMT components through a CMOS process, rather than a GaAS process, in order to accomplish the requirements on small size and low price. Currently, CMOS power amplifiers are considered as the biggest issue in the field of power amplifier (PA) research.
Since the CMOS power amplifiers can be implemented in a single chip of a Radio Frequency Integrated Circuit (RFIC) and are competitive in price, they are expected to be an amplifier of future wireless terminals. However, although a power amplifier having high linearity is required to design a transmitter of a high data rate, linearity of the CMOS power amplifier is unfortunately inferior to that of a GaAs power amplifier, and thus a transmitter structure for compensating the inferior linearity is required.
As communication systems evolve from 2 and 3 generations such as GSM, CDMA, WCDMA and the like to 3.5 and 4 generation schemes such as 3GPP LTE, Mobile WiMAX and the like, signals to be transmitted are complicated more and more. For the 3.5 and 4 generation communication systems, broad signal bands are required in communications of wireless terminals, and a further higher peak-to-average power ratio (PAPR) should be provided. Accordingly, next-generation power amplifiers for the wireless terminals are required to have high linearity and high efficiency.
Although chips designed as a linear CMOS power amplifier are developed and released in the market, they are still within the range of low and middle power. Amplifiers used for Bluetooth, ultra wideband (UWB) and the like are representative amplifiers of the lower power range. In addition, linear CMOS power amplifiers (PA) or the like for substituting GaAs power amplifiers used for existing WLAN are amplifiers of the middle power range.
However, linear CMOS power amplifiers of high power range are not commercialized until present. It is since that the linear CMOS power amplifiers of high power have a lot of limitations due to shortcomings of CMOS substrates compared with the GaAs substrates.
Since CMOS transistors have a characteristic of low breakdown voltage, it is not easy to develop a CMOS power amplifier generating high output power. Accordingly, they are disadvantageous in that battery use time is shortened due to low efficiency, which is one of the most important factors of a power amplifier for terminals. Such a disadvantage will be an obstacle to commercialization of power amplifiers using a CMOS process.
In order to solve the above problems, methods applying a cascode scheme and a voltage combining scheme of an output transformer are proposed as techniques for overcoming the characteristic of low breakdown voltage of the CMOS transistors.
Particularly, a differential structure using a transformer ideally solves source degeneration of a transistor caused by bonding wires and thus obtains a further higher gain.
However, a power amplifier should output a power higher than 30 dBm with respect to a power gain of 1 dB so as to be used as a 3G or 4G power amplifier for mobile communication. Although the CMOS power amplifier configures transistors as a two-stage cascode, a power amplifier of a single-ended structure is able to output only a power of about 28 dBm in maximum with respect to P1 dB. In addition, since it does not have a backside via, the source terminal is not grounded, and thus performance is severely degraded.
At this point, if a two-way transformer is used, a virtual ground (ground from the viewpoint of AC) of the source terminal can be rendered. In this case, although current is maintained as is, voltage swing is doubled, and thus output power is doubled (3 dB). Therefore, the power amplifier may output a power of 30 dBm. Accordingly, the transformer should be configured as described above in order to enhance output power of the CMOS power amplifier.
Meanwhile, the transformer can be configured inside or outside of a CMOS chip. A transformer implemented outside the CMOS chip is referred to as an ‘off chip transformer’, and a transformer implemented inside the CMOS chip is referred to as an ‘on chip transformer’.
a is a view showing a picture of a 3G CMOS power amplifier. Although a power amplifier of the on chip transformer scheme can be manufactured by configuring a transformer inside a CMOS chip as shown in
In addition, since the transformer is configured inside the chip, power loss increases due to the silicon medium. Generally, a big loss is generated by the medium when matching is performed using lumped components, and the loss can be reduced greatly if a transformer of a slab inductor scheme with a small loss is used.
As shown in
However, although the transformer configured as described above is absolutely needed in the CMOS power amplifier to increase output power, power loss occurs due to the structure and material of the transformer, and the transformer occupies almost 50% of the entire chip size of the power amplifier, and thus it is a big obstacle to commercialization of the power amplifier.
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a micro CMOS power amplifier, in which an output transformer is configured as a substrate of a multilayer structure, and an amplifier circuit module is stacked on the output transformer.
To accomplish the above object, according to one aspect of the present invention, there is provided a micro CMOS power amplifier including: an amplifier circuit module chip configured by modularizing circuits for amplifying power as a module; and an output transformer for outputting output of the amplifier circuit module chip to outside through a transformer circuit, in which the output transformer is implemented on a multilayer substrate, and the amplifier circuit module chip and the output transformer are configured as a stack.
In addition, in the micro CMOS power amplifier, the output transformer forms a primary winding and a secondary winding on different layers, and the layers are stacked so that the primary and secondary windings are overlapped to face each other.
In addition, in the micro CMOS power amplifier, the amplifier circuit module chip is implemented as a CMOS chip.
In addition, in the micro CMOS power amplifier, the output transformer includes: a second layer formed with a primary winding pattern; a first layer formed with a first input terminal pattern and a primary winding connection pattern, in which the primary winding connection pattern is vertically connected to the primary winding pattern through a via hole; a third layer formed with a secondary winding pattern; and a fourth layer formed with a second input terminal pattern and an output terminal pattern, in which the second input terminal pattern is vertically connected to the first input terminal pattern through a via hole, and the output terminal pattern is vertically connected to the secondary winding pattern through a via hole, wherein the first to fourth layers are vertically arranged in order.
In addition, in the micro CMOS power amplifier, the amplifier circuit module chip is positioned to be stacked on the first layer, and external terminals of the amplifier circuit module chip are connected to the primary winding connection pattern or the first input terminal pattern through a wire.
In addition, in the micro CMOS power amplifier, both end units of the primary and secondary winding patterns are positioned in opposite directions.
In addition, in the micro CMOS power amplifier, the third layer is formed with an extension unit by extending a first end unit of the secondary winding pattern, and the second layer is formed with a condenser pattern facing the extension unit, in which the condenser pattern is connected to the a second end unit of the secondary winding pattern through a via hole.
The preferred embodiments of the invention will be hereafter described in detail, with reference to the accompanying drawings.
In addition, in the drawings illustrating the embodiments of the invention, elements having like functions will be denoted by like reference numerals and details thereon will not be repeated.
First, the configuration of the circuit of a micro CMOS power amplifier according to a first embodiment of the present invention is described with reference to
As shown in
The input circuit 10 is a circuit for inputting signals, which is configured as an input balun transformer. The input balun transformer is a circuit for transforming balanced signals into unbalanced signals, which generates a differential signal from a single input signal.
The matching circuit 20 has a plurality of condensers C1, C2, C3 and C4 and an inductor L2, which is a general matching circuit for impedance matching of the input terminal in order to transmit a signal with least power loss.
The cascode circuit 30 is configured as a differential cascode circuit in order to increase output voltage without increasing breakdown voltage. This is a circuit for solving the problem of limiting maximum output power due to low breakdown voltage of a CMOS circuit. The differential cascode structure may increase voltage swing and breakdown voltage, compared with a single-ended structure. In addition, since via ground is not allowed in the CMOS process, ground is generally implemented using wire bonding. However, since the differential structure has a virtual AC ground at the source terminal of a transistor, the inductor effect can be reduced using the wire bonding. In addition, since the differential structure is a symmetrical structure and thus does not have harmonic waves of even numbers, harmonic components can be further decreased compared with the single-ended structure.
The output transformer circuit 40 is a circuit for stably amplifying output power by being electrically separated from the output 50, and it includes a primary winding 41 at the cascade circuit 30 terminal and a secondary winding 42 at the output 50 terminal.
In addition, the bias circuit 70 is a circuit for supplying bias voltage to a transistor circuit used in the cascade circuit 30, and it receives the bias voltage from outside.
Meanwhile, inductors WL1 to WL9 of the harmonic tuning circuit 60 or the like are implemented through wire bonding when the power amplifier 1 is configured. This will be described below in further detail.
Next, the configuration of a micro CMOS power amplifier according to a first embodiment of the present invention is described with reference to
As shown in
The amplifier circuit module chip 100 modularizes circuits for amplifying power (hereinafter, referred to as an amplifier circuit) as one module and configures the circuit as a substrate or a chip. Preferably, the amplifier circuit module chip 100 is configured as a CMOS circuit and manufactured as a chip.
As shown in
In addition, external terminals of the amplifier circuit module chip 100 include an input terminal 110, connection terminals 120, a bias voltage terminal 130 and an inductor ground terminal 140. The input terminal 110 is a terminal for receiving input signals at the input circuit 10, and the connection terminals 120 are terminals for outputting amplified signals, which are connected to the primary winding 41 of the output transformer circuit 40.
The bias voltage terminal 130 is a terminal for applying bias voltage of the bias circuit 70, and the inductor ground terminal 140 is a terminal for configuring inductors grounded through wire bonding. As shown in
In the output transformer 200, the output transformer circuit 40 is implemented on a multilayer substrate such as low temperature co-fired ceramics (LTCC), and the layers are electrically connected through via holes.
Before describing the configuration of the output transformer 200, the circuit of the output transformer 200 is described in further detail with reference to
As shown in
Hereinafter, the multilayer structure of the output transformer 200 is described in further detail.
Next, the multilayer substrate structure of the output transformer 200 of the micro CMOS power amplifier 1 according to a first embodiment of the present invention is described with reference to
As shown in
In each of the layers 210 to 240, a copper foil layer is stacked on a dielectric layer 219, 229, 239 and 249, and a pattern is formed by etching parts of the copper foil layer. Hereinafter, the patterns formed on the layers are described by separating the layers into the first and second layers 210 and 220 and the third and fourth layers 230 and 240.
First, the first and second layers 210 and 220 are described.
The first and second layers 210 and 220 are layers which form the circuit of the primary winding unit 260 of the output transformer 200 shown in
A primary winding pattern 221 constituting the primary winding unit 260 is formed on the second layer 220. The primary winding pattern 221 is formed as a conductive pattern, which is a conductive loop connected in series around the center of the substrate. The conductive loop is not formed as a closed loop, but a portion of the loop is disconnected. The disconnected portion of the conductive loop becomes both end parts (i.e., both end units) 222 of the primary winding pattern 221.
Via holes 222a are formed at both end units 222 of the primary winding pattern 221, and a via hole 223a is also formed at the center unit 223 of the primary winding pattern 221. The via holes 222a formed at both end units function as the signal terminals 262 of the primary winding unit, and the via hole 223a formed at the center unit functions as the power terminal 263.
In addition, a condenser pattern 225 is formed near the center unit 223 of the primary winding pattern, and a via hole 225a is formed inside the condenser pattern 225. The condenser pattern 225 is a pattern for implementing the condenser C10 connected to the secondary winding unit 270. The function of the condenser pattern 225 will be described in further detail when the third layer is described.
On the other hand, patterns for connecting to the terminals of the primary winding unit 210 and patterns for connecting to the external terminals of the amplifier are formed on the first layer 210. In addition, a ground pattern 218 is formed in the other areas.
The patterns connected to the terminals of the primary winding unit 210 include signal connection patterns 212 and a power connection pattern 213. Via holes 212a and 213a are formed in the signal connection patterns 212 and the power connection pattern 213, respectively.
The signal connection patterns 212 are formed at the positions of the both end units 222 of the primary winding pattern of the first layer 220, and the power connection pattern 213 is formed at the position of the center unit 223 of the primary winding pattern. Accordingly, the via holes 212a of the signal connection patterns are vertically connected to the via holes 222a of the both end units of the primary winding pattern, and the via hole 213a of the power connection pattern is vertically connected to the via hole 223a of the center unit of the primary winding pattern and electrically communicates with the via hole 223a of the center unit.
Accordingly, the signal connection patterns 212 function as the signal terminals 262 of the primary winding unit 270 respectively, and the power connection pattern 213 functions as the power terminal 263.
Next, the patterns connected to the external terminals of the amplifier include a first input terminal pattern 215, a first bias terminal pattern 216 and a first power terminal pattern 217.
The first input terminal pattern 215 is a conductive pattern for receiving external signals, and the first bias terminal pattern 216 is a conductive pattern for receiving power applied to the bias circuit. The first power terminal pattern 217 is a conductive pattern for receiving main power. The first input terminal pattern 215, the first bias terminal pattern 216 and the first power terminal pattern 217 are preferably formed on one side of the first layer 210.
On the other hand, on the first layer 210, the ground pattern 218 is formed in the areas other than the patterned areas, and at least one via hole 218a is formed in the ground pattern 218. The via hole 218a of the ground pattern is electrically connected to a ground pattern 248 of the fourth layer 240 and functions as ground.
In addition, a heat sink pattern 214 is preferably formed near the center of the first layer 210. Particularly, the heat sink pattern 214 is formed at the position of the amplifier circuit module chip 100 stacked on the first layer 210. Since the amplifier circuit module chip 100 is an integrated circuit and may emit large amounts of heat, the heat sink pattern 214 is formed as a pattern for dissipating the heat.
Meanwhile, on the second layer 220, via penetration holes 228a, through which via holes pass through, are formed at the positions the same as those of the via holes 218a and 248a so that the via holes 218a of the ground pattern may pass through and connect to the via holes 248a of the pattern ground.
An embodiment of stacking the amplifier circuit module chip 100 on the first layer 210 is described with reference to
As shown in
Specifically, the input terminal 110 WL1 of the amplifier circuit module chip 100 is connected to the first input terminal pattern 215 through a wire, and the bias voltage terminal 130 WL11 is connected to the first bias terminal pattern 216. In addition, the connection terminals 120 WL9/WL10 of the amplifier circuit module chip 100 are connected to the signal connection patterns 212 and, in the end, connected to the primary winding pattern 221 through the via holes 212a and 222a.
The inductor ground terminals 140 WL3, WL4, WL5, WL6 and W17 of the amplifier circuit module chip 100 are bonded to the ground pattern 218 through wires. That is, an inductor ground function is implemented through wire bonding.
Meanwhile, the power connection pattern 213 is coupled to a main power pattern 217 through a wire. In the end, the main power pattern 217 is connected to the center unit 223 of the primary winding pattern 221 through the via holes 213a and 223a.
Next, the third and fourth layers 230 and 240 are described.
The third and fourth layers 230 and 240 are layers which form the circuit of the secondary winding unit 270 of the output transformer 200 shown in
A secondary winding pattern 231 constituting the secondary winding unit 270 is formed on third layer 230. The secondary winding pattern 231 is formed as a conductive pattern, which is a conductive loop connected in series around the center of the substrate. The conductive loop is not formed as a closed loop, but a portion of the loop is disconnected. The disconnected portion of the conductive loop becomes both end parts (i.e., both end units) 232 and 233 of the secondary winding pattern 231.
At this point, the conductive loop is preferably formed to face the primary winding pattern 221. However, the both end units 232 and 233 of the secondary winding pattern 231 are preferably positioned in a direction opposite to the positions of the both end units 222 of the primary winding pattern. Via holes 232a and 233a are formed at both end units 232 and 233 of the secondary winding pattern 231.
At this point, either of the both end units implements the output unit terminal 272 of the secondary winding unit 270, and the other end unit implements the ground unit terminal 273. For convenience, the former is referred to as an output end unit 232, and the latter is referred to as a ground end unit 233.
In addition, the conductive pattern of either the output end unit 232 or the ground end unit 233 is extended. For convenience, it is assumed that the output end unit 232 is extended, and the extended portion is referred to as an extension unit 232b.
As shown in
In addition, the condenser pattern 225 is formed to be overlapped with the extension unit 232b in parallel. Accordingly, the extension unit 232b connected to the output end unit 232 is formed to face the condenser pattern 225 connected to the ground end unit 233 and functions as the condenser C10.
Meanwhile, patterns for connecting to the external terminals of the power amplifier 1 are formed on the fourth layer 210, and the ground pattern 248 is formed in the other areas.
An output terminal pattern 242, a second input terminal pattern 245, a second bias terminal pattern 246 and a second power terminal pattern 247 are formed as the patterns for connecting to the external terminals of the power amplifier 1.
The output terminal pattern 242 is formed at a position the same as that of the output end unit 232 of the third layer 230, and a via hole 232a is formed to vertically connect the output terminal pattern 242 to the output end unit 232. In addition, the second input terminal pattern 245, the second bias terminal pattern 246 and the second power terminal pattern 247 are formed at positions the same as those of the first input terminal pattern 215, the first bias terminal pattern 216 and the first power terminal pattern 217 respectively and connected through the via holes.
On the other hand, on the fourth layer 240, the ground pattern 248 is formed in the areas other than the patterned areas, and at least one via hole 248a is formed in the ground pattern 248 so as to be electrically connected to the ground pattern 218 of the first layer 210.
Next, the effects according to a first embodiment of the present invention will be described in further detail with reference to
As shown in
As shown in
The transformer according to a first embodiment of the present invention actually generates a loss of 0.3 dB, and this is exceptionally excellent performance compared with a loss of 1 dB or higher of the on chip scheme according to a conventional technique.
According to the micro CMOS power amplifier of the present invention described above, an output transformer occupying a large space in a conventional power amplifier is configured as a multilayer substrate, and thus the chip size can be reduced within 50% without decreasing output power of the power amplifier.
While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by the embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2012-0112020 | Oct 2012 | KR | national |
