Patent Application
20160374210
Embodiments of the present description generally relate to the field of microelectronic device fabrication, and, more particularly, to metallization structures for build-layers and methods of fabricating the same.
Microelectronic devices are generally fabricated from various components, including, but not limited to, at last one microelectronic die (such as a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, or the like), at least one passive component (such as resistors, capacitors, inductors and the like), and at least one microelectronic substrate (such as interposers, motherboards, and the like) for mounting the components. The various components may be interconnected to one another through build-up layers comprising a plurality of dielectric layers with a plurality of metallization structures, such as conductive traces and conductive vias formed on and/or through the dielectric layers. These build-up layers may be formed on any of the components within the microelectronic device.
The microelectronic industry is continually striving to produce ever faster and smaller microelectronic devices for use in various electronic products, including, but not limited to portable products, such as portable computers, digital cameras, electronic tablets, cellular phones, and the like. As the size of components, such as microelectronic dice and microelectronic substrates, are reduced, the size of the metallization must also be reduced. Therefore, there is a need to develop metallization structures and methods of fabrication thereof to reduce the size of the metallization structures.
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The present disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
The terms “over”, “to”, “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
Currently, the formation of build-up layers is achieved by forming a dielectric material layer, wherein a surface of this dielectric material layer is roughened, by any appropriate technique, and exposed to a metallization catalyst in an ionic or colloidal solution. Molecules of the metallization catalyst complex with the dielectric material layer and an activation process, such as by reducing chemistry (for example, dimethylamineborane) is used to bring the metallization catalyst to a correct oxidation state to enhance catalyst activity, as will be understood to those skilled in the art. The activated dielectric material layer is then exposed to a solution of a desired metal, such as copper, and a reducing agent, which results in the deposition of a metal layer in areas with the metallization catalyst complexed to dielectric material layer (i.e. the metallization catalyst is required to initiate the metal layer deposition). This process is known in the industry as electroless deposition. However, such methods lack spatial specificity and rely on deposition of the metal layer over relatively large areas through total immersion in catalyst solution.
Embodiments of the present description include methods of fabricating a build-up layer having a high degree of control over the metal layer deposition or “patterning” and include the build-up layers formed with these methods. In one embodiment, a microelectronic dielectric layer may be formed to include a dielectric material with a metallization catalyst dispersed therein. A primer layer may be formed on the microelectronic dielectric layer and a recess may then be formed through the primer layer and into the dielectric material layer with an ablating laser. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess, such as the high precision of the ablating laser.
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The microelectronic dielectric layer 110 may be formed by any process known in the art, including, but not limited to, doping, co-deposition, and the like. Furthermore, the microelectronic dielectric layer 110 may include a filler material (not shown) to assist in the prevention of the thermal expansion issues, as will be understood by those skilled in the art. In one embodiment, the filler material (not shown) may have a maximum filler size of about 1 μm and an average filler size of less than about 0.3 μm. In a specific example, the microelectronic dielectric layer 110 may comprise an epoxy-polymer blend for the dielectric material 112 and may further include a silica filler material.
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In an embodiment of the present description, the primer layer 120 may be relatively thin. In one embodiment, the primer layer 120 may have a thickness T of less than about 1 μm. With a relatively thin primer layer 120, the material formulation thereof can be much less demanding in terms of designing for minimizing the effects of thermal expansion, as will be understood to those skilled in the art.
The primer layer 120 may include a filler material (not shown), which may have a relatively small particle size. In one embodiment, the filler material may have a particle size of less than about 100 nm, such that any side reactions therewith are avoided during subsequent processing steps, as will be understood to those skilled in the art. It is noted that using a primer layer 120 without a filler material may be advantageous, as it will entirely avoid such side reactions. It is understood that the primer layer 120 need not be removed, such that it will be a permanent feature of the build-up layer resulting from the embodiments of the present description.
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The activation solution 140, if used, may be any appropriate reduction solution, such as dimethyborane. The various components and processes used for catalytic activation are well known to those skilled in the art, and for the sake of brevity and conciseness will not be described or illustrated herein.
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The communication chip enables wireless communications for the transfer of data to and from the computing device. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
Any of the microelectronic components within the computing device 200 may include a build-up layer comprising a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, and a primer layer formed on the microelectronic dielectric layer, as described herein.
In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in
The following examples pertain to further embodiments, wherein Example 1 is a method of fabricating a microelectronic build-up layer, comprising forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, wherein the microelectronic dielectric layer includes a first surface; forming a primer layer on the microelectronic dielectric layer first surface; forming a recess through the primer layer and into the microelectronic dielectric layer; and forming a metal layer adjacent the microelectronic dielectric layer within the recess.
In Example 2, the subject matter of Example 1 can optionally include forming the recess through the primer layer and into the microelectronic dielectric layer comprising laser ablating a recess through the primer layer and into the microelectronic dielectric layer.
In Example 3, the subject matter of either Example 1 or 2 can optionally include forming the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprising an epoxy-polymer blend dielectric material.
In Example 4, the subject matter of either Example 1 or 2 can optionally include forming the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprising a metallization catalyst selected from the group consisting of palladium salts, silver salts, copper salts, platinum salts, and nickel salts.
In Example 5, the subject matter of either Example 1 or 2 can optionally include forming the primer layer on the microelectronic dielectric layer first surface comprises forming an organic polymer primer layer on the microelectronic dielectric layer first surface.
In Example 6, the subject matter of Example 5 can optionally include forming the organic polymer primer layer on the microelectronic dielectric layer first surface comprising forming an organic polymer primer layer selected from the group consisting of epoxy-phenol materials and epoxy-imide materials.
In Example 7, the subject matter of either Examples 1 or 2 can optionally include forming the metal layer on the dielectric material layer within the recess comprising activating the microelectronic dielectric layer within the recess to form an activated layer within the dielectric material layer; and depositing a metal layer on the activated layer.
In Example 8, the subject matter of Example 7 can optionally include activating the microelectronic dielectric layer comprising immersing the microelectronic dielectric layer and primer layer in an activation solution.
In Example 9, the subject matter of Example 8 can optionally include immersing the microelectronic dielectric layer and primer layer in the activation solution comprising immersing the microelectronic dielectric layer and primer layer in a dimethylborane activation solution.
In Example 10, the subject matter of Example 7 can optionally include depositing a metal layer on the activated layer comprising immersing the activated layer in a deposition solution.
In Example 11, the subject matter of Example 10 can optionally include immersing the activated layer in a deposition solution comprising immersing activated layer in an aqueous deposition solution comprising a metal salt and a reducing agent.
In Example 12, the subject matter of Example 11 can optionally include immersing the activated layer in an aqueous deposition solution comprising a metal salt and a reducing agent comprising immersing the activated layer in an aqueous deposition solution comprising a copper salt and a reducing agent.
The following examples pertain to further embodiments, wherein Example 13 is a microelectronic build-up layer, comprising a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, wherein the microelectronic dielectric layer includes a first surface; a primer layer on the microelectronic dielectric layer first surface; a recess through the primer layer and into the microelectronic dielectric layer; and a metal layer adjacent the microelectronic dielectric layer within the recess.
In Example 14, the subject matter of Example 13 can optionally include the recess through the primer layer and into the microelectronic dielectric layer comprising a laser ablated recess through the primer layer and into the microelectronic dielectric layer.
In Example 15, the subject matter of Example 13 can optionally include the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprising an epoxy-polymer blend dielectric material.
In Example 16, the subject matter of any of Examples 13 to 15 can optionally include the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprising a metallization catalyst selected from the group consisting of palladium salts, silver salts, copper salts, platinum salts, and nickel salts.
In Example 17, the subject matter of any of Examples 13 to 15 can optionally include the primer layer on the microelectronic dielectric layer first surface comprising an organic polymer primer layer on the microelectronic dielectric layer first surface.
In Example 18, the subject matter of Example 17 can optionally include the organic polymer primer layer on the microelectronic dielectric layer first surface comprising an organic polymer primer layer selected from the group consisting of epoxy-phenol materials and epoxy-imide materials.
In Example 19, the subject matter of any of Examples 13 to 15 can optionally include an activated layer disposed between the metal layer and the dielectric material layer within the recess.
In Example 20, the subject matter of any of Examples 13 to 15 can optionally include the metal layer comprising a conformal metal layer.
In Example 21, the subject matter of any of Examples 13 to 15 can optionally include the metal layer comprising a copper layer.
The following examples pertain to further embodiments, wherein Example 22 is a electronic system, comprising a board; and a microelectronic component attached to the board, wherein the microelectronic component includes microelectronic build-up layer, comprising a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, wherein the microelectronic dielectric layer includes a first surface; a primer layer on the microelectronic dielectric layer first surface; a recess through the primer layer and into the microelectronic dielectric layer; and a metal layer adjacent the microelectronic dielectric layer within the recess.
In Example 23, the subject matter of Example 22 can optionally include the recess through the primer layer and into the microelectronic dielectric layer comprising a laser ablated recess through the primer layer and into the microelectronic dielectric layer.
In Example 24, the subject matter of Example 22 can optionally include the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprising an epoxy-polymer blend dielectric material.
In Example 25, the subject matter of any of Examples 22 to 24 can optionally include the microelectronic dielectric layer comprising the dielectric material with the metallization catalyst dispersed therein comprising a metallization catalyst selected from the group consisting of palladium salts, silver salts, copper salts, platinum salts, and nickel salts.
In Example 26, the subject matter of any of Examples 22 to 24 can optionally include the primer layer on the microelectronic dielectric layer first surface comprising an organic polymer primer layer on the microelectronic dielectric layer first surface.
In Example 27, the subject matter of Example 26 can optionally include the organic polymer primer layer on the microelectronic dielectric layer first surface comprising an organic polymer primer layer selected from the group consisting of epoxy-phenol materials and epoxy-imide materials.
In Example 28, the subject matter of any of Examples 22 to 24 can optionally include an activated layer disposed between the metal layer and the dielectric material layer within the recess.
In Example 29, the subject matter of any of Examples 22 to 24 can optionally include the metal layer comprising a conformal metal layer.
In Example 30, the subject matter of any of Examples 22 to 24 can optionally include the metal layer comprising a copper layer.
Having thus described in detail embodiments of the present description, it is understood that the present description defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2015/016072 | 2/16/2015 | WO | 00 |
