Claims
- 1. A method of manufacturing a reinforced resin coated copper prepreg comprising:a. coating resin onto a copper foil surface; b. applying a reinforcing material comprising micro-fiber glass into the resin coating on the copper foil; and c. drying the solvent out of the resin and advancing the cure of the resin to between 10% and 50% of full cure.
- 2. A method for manufacturing a multiple layer electronic circuit that includes a plurality of lased vias comprising the steps of:(a) applying a prepreg having a first surface and a second surface and comprising a non-woven reinforcing material consisting primarily of micro-fiber glass impregnated with a partially cured polymer to a substrate consisting of a first layer of circuitry located on the surface of the substrate such that the first surface of the prepreg is in contact with the first layer of circuitry; (b) exposing the prepreg to elevated temperatures and pressure for a period of time sufficient to fully cure the partially cured prepreg polymer to give a laminate including a dielectric surface layer; and (c) lasing a plurality of micro-vias into the dielectric surface layer.
- 3. The method of claim 2 wherein a conductive material is applied to the via.
- 4. The method of claim 2 wherein a conductive metal foil layer is applied to the prepreg second surface prior to step (b).
- 5. The method of claim 4 wherein the lased vias include vias that extend from the conductive metal foil layer to the first layer of circuitry.
- 6. The method of claim 4 wherein a second circuit pattern is created on the conductive metal foil layer.
- 7. The method of claim 4 wherein the micro-vias are formed by laser drilling holes through both the conductive metal foil layer and the dielectric surface layer.
- 8. The method of claim 2 wherein the substrate includes an embedded circuitry layers that is separated from the first circuitry layer by a dielectric layer wherein at least one of the lased vias extends from the dielectric surface layer to the embedded circuitry layer.
- 9. The method of claim 2 wherein a plurality of holes are formed in the conductive metal foil layer prior to laser via formation and wherein the micro-vias are lased in the exposed holes.
- 10. The method of claim 2 wherein at least 95% of the plurality of micro-vias comprise an acceptable measure of thermal damage.
- 11. The method of claim 9 wherein a circuit is formed on or from the metal foil layer covering the dielectric surface layer following the lasing of at least one micro-via.
- 12. The method of claim 6 wherein the circuit is formed on or from the metal foil layer before the lasing of at least one micro-via.
- 13. The method of claim 2 wherein the laminate is processed by the further steps of:(i) applying a layer of sputtered metal onto the dielectric surface layer and into the micro-vias oft he laminate to give a sputtered metal surface; (ii) applying a resist layer to the sputtered metal surface, imaging the resist layer to define wanted and unwanted resist layer portions, and removing the unwanted resist layer portions to expose at least a portion of the sputtered metal surface and at least one micro-via; (iii) electroplating the metal layer to fill the exposed micro-vias with electroplated metal, and to build-up a second circuit layer corresponding to the exposed sputtered metal surface; (iv) removing the wanted portion of the resist layer; and (v) removing the sputtered metal layer below the removed wanted portion of the resist layer.
- 14. The method of claim 2 wherein the dielectric surface layer includes from about 5 to about 45 wt % non-woven micro-fiber glass and from about 55 to about 95 wt % polymner.
- 15. The method of claim 13 wherein 80% of the micro-fiber glass has a diameter less than about 1 micron.
- 16. The method of claim 2 wherein each micro-via is lased using a laser with a uniform power setting.
Parent Case Info
This application is a divisional application of allowed U.S. application Ser. No. 09/344,038, which was filed Jun. 25, 1999 now U.S. Pat. No. 6,224,965.
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