Patent Application
20250218908
Semiconductor wafers are circular pieces of semiconductor material, such as silicon, that are used to manufacture semiconductor chips. Generally, complex manufacturing processes are used to form numerous integrated circuits on a single wafer. The formation of such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is cut into multiple pieces, called semiconductor dies, with each die containing one of the circuits. The cutting, or sawing, of the wafer into individual dies is called singulation. Dies are then coupled to a lead frame and are covered by a mold compound, which is subsequently sawn to produce a package.
In examples, an isolation device comprises a multi-level substrate having opposing first and second surfaces. The multi-level substrate includes a first coil in a first layer of the substrate, the first coil having first and second terminals, a second coil in a second layer of the substrate that is vertically distanced from the first layer, the second coil having third and fourth terminals, and a dielectric material covering the first and second coils. The device comprises a first semiconductor die coupled to the first surface and to the first and second terminals, a second semiconductor die coupled to the second surface and to the third and fourth terminals, the second semiconductor die galvanically isolated from the first semiconductor die, conductive terminals coupled to the multi-level substrate, and a mold compound covering the multi-level substrate, the first and second semiconductor dies, and the conductive terminals.
In examples, a method for manufacturing an isolation device comprises coupling a first semiconductor die to a first coil of a multi-layer substrate using first solder bumps, the substrate including a second coil and a dielectric material covering the first and second coils; coupling the substrate to conductive terminals of a lead frame; coupling a second semiconductor die to the second coil using second solder bumps, the first and second semiconductor dies coupled to opposing surfaces of the substrate; covering the substrate and the first and second semiconductor dies with a mold compound; and trimming the conductive terminals to detach the conductive terminals from the lead frame.
FIGS. 4A1-4F3 are a process flow for manufacturing an isolation device in accordance with various examples.
Some isolation devices contain laminate transformers and, optionally, semiconductor dies coupled to the transformers. Some isolation devices include multiple, co-planar die pads, with a first die pad coupled to a transformer, a second die pad coupled to a semiconductor die, and a third die pad coupled to a different semiconductor die. Some isolation devices include multiple, co-planar semiconductor dies coupled to a top surface of the transformer. Some isolation devices include transformer coils that are wire bonded directly to bond pads or leads of the isolation device. These isolation devices suffer from numerous technical disadvantages. For example, the dies and transformers in these configurations are unable to adequately dissipate the heat typically generated in power applications. In addition, in some of the isolation devices described above, bond wires are used to couple dies to the transformer. These bond wires inherently introduce parasitics into the isolation device, and because the bond wires are coupled in series with the coils of the transformer, the bond wires introduce inductive asymmetry and leakage in series with the magnetic components into the isolation device, which can adversely impact isolation device operation. Thus, engineers must account for such bond wire parasitics in the design stage, which presents a substantial technical challenge because of the limited modeling capabilities at the design stage and added design margins which must be considered. In some of the isolation devices described above, to comply with spatial design restrictions, the semiconductor dies must be spaced closely. When a voltage potential exists between the dies, especially in galvanic isolation applications, this proximity between the dies forms a high electric field region between the dies, which can adversely impact isolation device operation and galvanic isolation capability. In addition, in isolation devices where the semiconductor dies are coupled to the same side of the transformer, the transformer must be specifically designed to provide coil terminals to respective semiconductor dies, which can prove to be spatially challenging when fewer transformer coil layers are desired. Isolation devices devised to address such problems suffer from their own challenges. For example, isolation devices designed to minimize the number of transformer layers suffer from strict limits on the number of possible transformer coil turns.
This disclosure describes various examples of an isolation device that mitigates the various technical challenges described above. In examples, an isolation device comprises a multi-level substrate having opposing first and second surfaces. The multi-level substrate includes a first coil in a first layer of the substrate. The first coil has first and second terminals. A second coil in a second layer of the substrate is vertically distanced from the first layer. The second coil has third and fourth terminals. The substrate also includes an insulative material covering the first and second coils. The isolation device comprises a first semiconductor die coupled to the first surface and to the first and second terminals, a second semiconductor die coupled to the second surface and to the third and fourth terminals, conductive terminals coupled to the multi-level substrate, and a mold compound. The mold compound covers the multi-level substrate, the first and second semiconductor dies, and the conductive terminals. Such isolation devices are technically advantageous for several reasons. First, because the first and second semiconductor dies are positioned on opposing first and second surfaces of the substrate, they facilitate heat dissipation from the first and second coils, respectively. Second, the electric fields that are generated between semiconductor dies on the same surface of the substrate, as well as their adverse impact on isolation device operation, are significantly reduced by positioning the first and second dies on opposing surfaces of the substrate. Third, the design challenges associated with connecting coil terminals to dies positioned on the same surface of the substrate are eliminated by positioning the first and second dies on opposing surfaces of the substrate. Fourth, because the first and second semiconductor dies are coupled to their respective terminals by metallic (e.g., solder) bumps instead of bond wires, the disadvantages introduced by the bond wire parasitics as described above are mitigated. Fifth, the isolation device achieves operational symmetry, thus mitigating against the deleterious operational effects of external disturbances acting upon the isolation device. Sixth, because positioning semiconductor dies on opposing surfaces of the multi-layer substrate results in less complex routing of the coils in the substrate (e.g., by eliminating any need for complex coil terminal configurations), fewer layers may be used in the substrate, resulting in a thinner substrate and a thinner isolation device (e.g., up to 50% thinner). Various examples of the isolation device are now described with reference to the drawings.
In examples, the multi-layer substrate 112 comprises multiple transformer coils 114, 116 positioned in different layers of the substrate 112. In examples, the coil 114 is in a layer of the substrate 112 that is between the surface 113 and the surface 115, and that is between the surface 113 and the layer in which the coil 116 is positioned. Similarly, in examples, the coil 116 is in a layer of the substrate 112 that is between the surface 113 and the surface 115, and that is between the surface 115 and the layer in which the coil 114 is positioned. The coils 114, 116 are composed of any suitable type of metal or metal alloy, such as copper. Any number of coils (i.e., two or greater) may be useful. Each coil 114, 116 may have any suitable number of turns. In examples in which more than two coils are used, each such coil may have any suitable number of turns. In examples, the coil 114 is exposed to the surface 113, and in other examples, the coil 114 is embedded within the substrate 112 such that the coil 114 is not exposed to the surface 113. In examples, the coil 116 is exposed to the surface 115, and in other examples, the coil 116 is embedded within the substrate 112 such that the coil 116 is not exposed to the surface 115. In some examples, the coils 114, 116 are vertically overlapping, as vertical overlap is defined above.
The substrate 112 includes traces 118 that may be horizontally co-planar with the coil 114. The substrate 112 includes traces 120 that may be horizontally co-planar with the coil 116. The traces 120 are coupled to the conductive terminals 104, such as by soldering or any other appropriate coupling technique. The traces 118 may be coupled to the conductive terminals 104 by way of one or more of the traces 120. The traces 118 may be coupled to the traces 120 by way of vias 122. Solder bumps 124 couple the device side 109 of the semiconductor die 108 to terminals of the coil 114 and to the traces 118. Similarly, solder bumps 126 couple the device side 111 of the semiconductor die 110 to terminals of the coil 116 and to at least some of the traces 120. The substrate 112 includes a dielectric material 117 (e.g., a solid, non-air dielectric material, such as AJINOMOTO® build-up film, BT Laminate, or another suitable build-up film) that contacts the metal structures of the substrate 112, such as the coils 114, 116, the traces 118, 120, and the vias 122. In some examples, the conductive terminals 104 are coupled to the surface 115, and in other examples, the conductive terminals 104 are coupled to the surface 113 (by way of metal traces 118 and additional metal traces 118 not expressly shown in
A multi-layer substrate is defined as a component of a semiconductor package, where the component includes multiple metal layers formed by plating (e.g., electroplating) and that further includes a dielectric such as a mold compound or film (e.g., AJINOMOTO® build-up film (ABF)) filling spaces between and around the multiple metal layers. A multi-layer substrate differs from a printed circuit board (PCB) because the multi-layer package substrate is within the isolation device 100, whereas the PCB is outside the isolation device 100. The multi-layer substrate includes multiple metal layers that are separated by a solid, tangible dielectric, whereas the PCB may contain multiple layers of printed circuit board that may not be separated by a dielectric material other than air.
In operation, the semiconductor die 108 provides power and/or data to and receives power and/or data from the coil 114. The semiconductor die 110 provides power to and receives power from the coil 116. When energized by the semiconductor die 108, the coil 114 produces a fluctuating magnetic field that induces a voltage in the coil 116 through mutual inductance. Similarly, when energized by the semiconductor die 110, the coil 116 produces a fluctuating magnetic field that induces a voltage in the coil 114 through mutual inductance. The semiconductor dies 108, 110 communicate with devices outside of the isolation device 100 by way of the conductive terminals 104. For example, the isolation device 100 may be coupled to a printed circuit board (PCB) on which one or more other devices are mounted, and the isolation device 100 may communicate with such other devices by way of the conductive terminals 104 and metal traces on the PCB.
Because the semiconductor dies 108, 110 are positioned on opposing surfaces 113, 115, respectively, of the multi-layer substrate 112, numerous technical advantages are realized. First, the positioning of the semiconductor dies 108, 110 facilitates heat dissipation from the coils 114, 116, respectively. Second, minimal or no electric fields are generated between the semiconductor dies 108, 110, and thus any adverse impacts on operation of the isolation device 100 due to such electric fields are mitigated or eliminated. Third, the design challenges associated with connecting coil terminals to dies positioned on the same surface of the substrate are eliminated by positioning the semiconductor dies 108, 110 on opposing surfaces 113, 115 of the substrate 112. Fourth, because the semiconductor dies 108, 110 are coupled to their respective terminals by metallic (e.g., solder) bumps 124, 126 instead of bond wires, the disadvantages introduced by the bond wire parasitics as described above are mitigated.
The semiconductor dies 108, 110 may vary in size, position, or both. The positioning of the semiconductor dies 108, 110 on the opposing surfaces 113, 115 of the substrate 112 eliminates any adverse effects that would otherwise result by positioning the semiconductor dies 108, 110 in proximity to each other, such as the formation of electric fields that adversely impact isolation device 100 operation. For example, the semiconductor dies 108, 110 may be centered directly above and below the substrate 112, respectively, as opposed to the configuration of
The method 300 includes forming a substrate, such as the substrate 112, through an iterative plating (e.g., electroplating) and dielectric film deposition process (302). FIG. 4A1 is a profile, cross-sectional view of the substrate 112 having been formed through an iterative process of electroplating and dielectric film deposition. For example, in a first step, a seed layer may be deposited on a metal carrier, and photolithographic processes may be used to plate some or all of a first coil (e.g., the coil 116) and first traces co-planar with the first coil (e.g., the traces 120). In a second step, dielectric film may be deposited (e.g., by way of lamination) on and around the first coil and the first traces. In a third step, the dielectric film and electroplated metal may be grinded. These steps may be repeated until the first coil and first traces are fully formed. Subsequently, one or more layers of dielectric film may be deposited, followed by another iterative process in which electroplating, photolithography, and grinding are used to form a second coil (e.g., the coil 114) and second traces co-planar with the second coil (e.g., the traces 118). This iterative process is continued until the second coil and second traces are fully formed, and adequate dielectric film has been deposited to surround and contact the second coil and second traces (e.g., until the multi-layer substrate 112 of
The method 300 includes coupling a bottom die to a bottom surface of the substrate by solder reflow (304). FIG. 4B1 is a profile, cross-sectional view of the structure of FIG. 4A1, except with the addition of the semiconductor die 110 coupled to the surface 115 of the substrate 112 by solder bumps 126. Specifically, the device side 111 of the semiconductor die 110 is coupled to the coil 116 and metal traces 120 by way of the solder bumps 126, as shown. FIG. 4B2 is a top-down view of the structure of FIG. 4B1, in accordance with various examples. FIG. 4B3 is a perspective view of the structure of FIG. 4B1, in accordance with various examples.
The method 300 includes coupling the substrate to a lead frame strip by solder reflow, with the bottom semiconductor die facing downward toward the lead frame conductive terminals (306). FIG. 4C1 is a profile, cross-sectional view of the structure of FIG. 4B1, except that the structure of FIG. 4B1 has been coupled to conductive terminals 104 of a lead frame strip. As shown, the conductive terminals 104 are flat, not bent as in
The method 300 includes coupling a top die to a top surface of the substrate by solder reflow (308). FIG. 4D1 is a profile, cross-sectional view of the structure of FIG. 4C1, except that the semiconductor die 108 has been coupled to the surface 113 of the substrate 112 by way of solder bumps 124. FIG. 4D2 is a top-down view of the structure of FIG. 4D1, in accordance with various examples. FIG. 4D3 is a perspective view of the structure of FIG. 4D1, in accordance with various examples.
The method 300 includes applying a mold compound to the structures of FIG. 4D1 (310). FIG. 4E1 is a profile, cross-sectional view of the structure of FIG. 4D1, except that the mold compound 102 has been applied to cover the various structures of FIG. 4D1, as shown. Any suitable technique may be useful to apply the mold compound 102, such as injection molding. FIG. 4E2 is a top-down view of the structure of FIG. 4E1, in accordance with various examples. FIG. 4E3 is a perspective view of the structure of FIG. 4E1, in accordance with various examples.
The method 300 includes trimming the leads from the lead frame and bending the leads (312). FIG. 4F1 is a profile, cross-sectional view of the structure of FIG. 4E1, except that the conductive terminals 104 have been trimmed so as to detach from a lead frame strip, and the conductive terminals 104 are subsequently bent to have a gullwing (or other suitable) shape. FIG. 4F2 is a top-down view of the structure of FIG. 4F1, in accordance with various examples. FIG. 4F3 is a perspective view of the structure of FIG. 4F1, in accordance with various examples.
The scope of this disclosure is not limited to the precise manufacturing process flow shown in FIGS. 4A1-4F3. For example, solder paste may be stencil printed onto a substrate 112, and the substrate 112 may be coupled to the top surfaces of the leads of a lead frame (e.g., by reflowing the solder paste that was stencil printed onto the substrate 112). A semiconductor die (e.g., semiconductor die 110) may be coupled to the bottom surface of the substrate 112 (i.e., the surface of the substrate 112 facing the leads). Another semiconductor die (e.g., semiconductor die 108) may be coupled to the top surface of the substrate 112 (i.e., the surface of the substrate 112 facing away from the leads). A mold compound may then be applied to cover the dies 108, 110, the substrate 112, the leads, and other components of the package.
As described above, an advantage to coupling semiconductor dies 108, 110 on opposing surfaces 113, 115 of the substrate 112 is increased heat dissipation from the coils 114, 116. Efficient heat dissipation is particularly valuable in power applications, such as in the isolation device 100, where significant amounts of heat are generated. Positioning the semiconductor die 108 directly above the coil 114, as shown in
The second (i.e., middle) sub-graph illustrates the common mode voltage transfer function seen across the halves of the receiving transformer coil (i.e., from one end of the coil to the center tap, and from the opposite end of the coil to the center tap) for the frequency sweep depicted on the x-axis. The curves 608, 610 depict the voltage response for the common mode voltages typical of traditional isolation devices (e.g., such as the isolation device of
The first (i.e., top-most) sub-graph represents the differential between the common mode voltages (i.e., the voltage across the receiving coil). At the channel operating frequency 602, the curve 616 (which depicts the behavior in an example isolation device, such as isolation device 100, or the isolation device of
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A. Other types of coupling, such as inductive, capacitive, and optical coupling, are also contemplated and included in the scope of this disclosure.
A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
Uses of the term “ground” and variations thereof in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.
