Patent Application
20220189901
The present application relates to Integrated Circuit (IC) technology; and more particularly to the packaging of processors with memory.
Integrated Circuit (IC) technology has advanced greatly over the past fifty years. ICs are now pervasive and present in electronic devices, machinery, vehicles, appliances, and many other devices. The density of transistors in modern ICs can reach 100 million transistors per square millimeter, and some large processing ICs now include billions of transistors while memory ICs may include hundreds of billions of transistors. However, the processing capability of a single IC may not be sufficient to meet the requisite processing needs of certain systems. Thus, multiple IC dies or devices are sometimes closely coupled and packaged together to provide greater processing capabilities.
Such multiple IC packages are used in a great number of differing applications including, without limitation, mobile communication devices, artificial intelligence devices, and graphics processing units. Typically, an Application Processor (AP) used in such devices includes a specialized processing structure to service the particular application, e.g., communications processor, graphics processor, etc. The AP typically has significant memory requirements, including large memory bandwidth as well as rapid memory access. Thus, multiple IC packages now often include both an AP and high bandwidth memory.
Current POP (Package on Package) packages use memory that provides up to 51.2 GBps peak bandwidth for LPDDR (Low Power Double Data Rate, e.g., 5th Generation) installations. To increase IO speed beyond 51.2 GBps would be very difficult for LPDDR due to limited pin availability. Further, increasing memory access speeds increases power consumption and internal heat production, and may compromise signal integrity. Certain prior art alternatives involve stacking WIO (Wide Input/Output) memory on a back-side of a processor, which requires through silicon vias (TSVs). Another prior art solution involves use of an interposer or lateral FO (Fan Out) connection, which increases package size. Still other prior art alternatives require vias that extended through the AP. Other prior alternatives have additional potential shortcomings, such as strict alignment requirements and poor signal pathways.
The present disclosure provides various aspects that may be employed with one or more of the embodiments. These aspects may be combined with one another singularly, in various combinations, or in total. According to a first embodiment of the present disclosure, a packaged Integrated Circuit (IC) is provided, the packaged IC including a fanout layer having conductive lines and conductive vias. The packaged IC further includes a processor having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the processor, and a memory coupled to a second surface of the RDL, wherein a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor.
In this embodiment, an encapsulant surrounds a portion of the memory, the RDL, and the processor, the encapsulant contacting the fanout layer on a first side and having an exposed second side. The packaged IC additionally includes a first plurality of conductive posts coupled between the fanout layer and the RDL through a portion of the encapsulant disposed beneath the first portion of the memory adjacent a first side of the processor, the first plurality of conductive posts providing data communication links between the processor and the memory via the fanout layer and the RDL. A second plurality of conductive posts are coupled between the fanout layer and conductive features of the RDL through a portion of the encapsulant that is proximate a second side of the processor, the conductive features of the RDL coupled to power inputs of the second portion of the memory. This embodiment further includes a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.
According to a first aspect of the first embodiment, the packaged IC further comprises a third plurality of conductive posts coupled between the fanout layer and the RDL through a portion of the encapsulant that is proximate the first side of the processor. The third plurality of conductive posts is coupled, via the RDL, to power inputs of the first portion of the memory. According to a second aspect of the packaged IC of the first embodiment, the second plurality of conductive posts are further coupled between the fanout layer and conductive features of the RDL through a portion of the encapsulant that is proximate at least a third side of the processor.
According to a third aspect of the first embodiment, the processor is one or more of a graphics processing unit, a communications processor, or an application specific processor. According to a fourth aspect of the packaged IC of the first embodiment, the packaged IC further comprises a dummy silicon substrate disposed adjacent the memory. According to a fifth aspect of the first embodiment, the packaged IC further includes a ball grid array coupled to the plurality of TMVs, and a Package on Package (POP) memory coupled to the ball grid array. According to a sixth aspect of the first embodiment, the memory is a high bandwidth memory relative to the POP memory. According to a seventh aspect of the first embodiment, the packaged IC further comprises a PCB ball grid array coupled to a second surface of the fanout layer.
In a second embodiment of the present disclosure, a method is provided for constructing a packaged Integrated Circuit (IC). According to the method, first level conductive posts are formed on a carrier substrate. The method of this embodiment further includes attaching a first side of a memory to the carrier substrate, the memory having a second side with conductive contacts for power inputs and data connections of the memory, and encapsulating the first level conductive posts and the memory with first encapsulant that contacts the carrier substrate on a first side and has an exposed second side.
In accordance with the method, a Redistribution Layer (RDL) is placed on the exposed second side of the first encapsulant, such that a first side of the RDL is disposed adjacent to and extends beyond the second side of the memory. The method further includes forming second level conductive posts on a second side of the RDL, and placing a processor on the second side of the RDL such that a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor. According to the method, the second level conductive posts and the processor are encapsulated with second encapsulant that contacts the second side of the RDL and has an exposed second side.
In this second embodiment, the method further includes forming a fanout layer on the exposed second side of the second encapsulant such that a first plurality of the second level conductive posts provide data communication links, via the RDL, between the processor and the conductive contacts for the data connections of the memory, a second plurality of the second level conductive posts are coupled, via the RDL, to the conductive contacts for the power inputs of the memory, and the first level conductive posts and a third plurality of the second level conductive posts form Through Mold Vias (TMVs) extending between the carrier substrate and the fanout layer.
The second embodiment also includes a plurality of aspects that may apply singularly or in combination. According to a first aspect of the method of the second embodiment, the data connections of the memory are disposed on the first portion of the memory and the power inputs are disposed on the second portion of the memory. According to a second aspect of the second embodiment, the second plurality of the second level conductive posts are disposed outside a footprint of the memory.
According to a third aspect of the second embodiment, the method further includes removing the carrier substrate to expose the first level conductive posts, forming a ball grid array on the exposed first level conductive posts, and placing Package on Package (POP) memory on the ball grid array. According to a fourth aspect of the second embodiment, the method further comprises forming a PCB ball grid array on an exposed surface of the fanout layer. According to a fifth aspect of the GPU of the second embodiment, the method further includes placing a dummy silicon substrate beside the memory, wherein the first encapsulant surrounds at least a portion of the dummy silicon substrate.
According to a third embodiment of the present disclosure, a packaged Integrated Circuit (IC) is provided, the packaged IC including a fanout layer having conductive lines and conductive vias. The packaged IC further includes a processor having a first surface residing substantially adjacent a first surface of the fanout layer, a plurality of conductive posts extending from the fanout layer, and a first encapsulant surrounding at least a portion of the processor and the plurality of conductive posts, the first encapsulant contacting the fanout layer on a first side and having an exposed second side. In this third embodiment, the packaged IC also includes a Redistribution Layer (RDL) having a first surface coupled to a second surface of the processor and the exposed second side of the first encapsulant, and a memory coupled to a second surface of the RDL, wherein a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor.
According to this third embodiment, a first plurality of conductive posts are coupled between the fanout layer and the RDL through a portion of the first encapsulant disposed beneath the first portion of the memory adjacent a first side of the processor, the first plurality of conductive posts providing data communication links between the processor and the memory. Additionally, a second plurality of conductive posts are coupled between the fanout layer and conductive features of the RDL through a portion of the first encapsulant that is proximate a second side of the processor, the conductive features of the RDL coupled to power inputs of the second portion of the memory. In this third embodiment, the packaged IC further includes a first plurality of Through Mold Vias (TMVs) extending from the fanout layer through the first encapsulant, a second encapsulant surrounding at least a portion of the memory and the RDL, and a second plurality of TMVs extending from the first plurality of TMVs through the second encapsulant.
The third embodiment also includes a plurality of aspects that may apply singularly or in combination. According to a first aspect of the third embodiment, the packaged IC further comprises a third plurality of conductive posts coupled between the fanout layer and the RDL through a portion of the first encapsulant that is proximate the first side of the processor, the third plurality of conductive posts coupled, via the RDL, to power inputs of the first portion of the memory. According to a second aspect of the third embodiment, the second plurality of conductive posts are further coupled between the fanout layer and conductive features of the RDL through a portion of the first encapsulant that is proximate at least a third side of the processor.
According to a third aspect of the third embodiment, the packaged IC further comprises a dummy silicon substrate disposed adjacent the memory. According to a fourth aspect of the third embodiment, the packaged IC further comprises a ball grid array coupled to the second plurality of TMVs, and a Package on Package (POP) memory coupled to the ball grid array. According to a fifth aspect of the third embodiment, the packaged IC further includes a PCB ball grid array coupled to a second surface of the fanout layer. The third embodiment can further include additional aspects such as those described above in conjunction with the first embodiment.
The disclosed embodiments introduce multi-side power delivery to a memory device in a packaged IC including a processor. Power delivery to the memory is provided, in part, by a fanout layer and conductive features of an RDL. As compared to prior architectures, the disclosed embodiments offer power delivery with reduced IR drop across the memory, and do not require use of relatively expensive through silicon vias (TSVs) or the larger package sizes associated with side-by-side placement of a processor and memory. These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.
For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.
It should be understood at the outset that, although illustrative implementations of one or more embodiments are provided below, the disclosed devices and/or methods may be implemented using any number of techniques and materials, whether currently known or in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents. Throughout the various views and illustrative embodiments described below, like reference numerals are used to designate like elements in some embodiments.
Novel methodologies and architectures are introduced below for improving power distribution and utilization in a packaged Integrated Circuit (IC) without utilizing through silicon vias (TSVs). As described in greater detail below, a packaged IC in accordance with the present disclosure a fanout layer and conductive features of an RDL to provide power deliver to multiple sides of a memory (e.g., a high bandwidth memory) that supports a processor. In an example, a first portion of the memory is disposed outside of a footprint of the processor. Data communications links are formed between the processor and the first portion of the memory, the links including conductive posts (e.g., Through Mold Vias (TMVs)) disposed beneath the first portion of the memory proximate to a first side of the processor. Multi-side power delivery to the memory is provided by the RDL and additional conductive post disposed proximate at least a second side of the processor. In this manner, power delivery to the memory is relatively symmetric, thereby minimizing undesirable IR drops across the memory.
Referring now to
In this example, a Redistribution Layer (RDL) 108b has a first surface that is partially disposed over or coupled to a second surface of the processor 102. The RDL 108b can also be formed in a semiconductor manufacturing process and provides power conductors formed therein that couple to the power conductors and vias 108 of the fanout layer 110 through conductive posts 108a. As described more fully below, the RDL 108b further services data communication links between the processor 102 and the memory 104 through conductive posts 112a. All of these power and/or signal conductors may be formed of copper with dimensions greater than one micrometer, for example.
In the illustrated packaged IC 100 of
In the embodiment of
Optionally, the memory 104 can be further configured to communicate wirelessly with the processor 102, e.g., via inductive coupling, capacitive coupling or Radio Frequency (RF) coupling. The memory 104 may include antennas, contacts, and/or coils to assist with the wireless communications. The processor 102 may also include antennas, contacts, and/or coils to support wireless communications with the memory 104. In an alternate construct, the antennas, contacts, and/or coils may be formed external to the memory 104 and/or the processor 102 and electrically couple thereto.
In the illustrated embodiment, an encapsulant 116 surrounds a substantial portion of the memory 104, the RDL 108b, and the processor 102. As used herein, the term “substantial portion” refers to most or all of the otherwise exposed outer surface of an encapsulated element. For example, an encapsulant can surround at least one of a top or bottom surface of a semiconductor element of a packaged IC, as well as all or most of the side surfaces of the semiconductor element. In the embodiment of
As illustrated in
In the illustrated embodiment, the packaged IC 400 includes a fanout layer 110 having power conductors and vias 108 and signal conductors and vias 112/114, a processor 102 having a first surface residing substantially adjacent a first surface of the fanout layer 110, and a plurality of conductive posts 204 and 208 and TMVs or conductive posts 216 extending from the fanout layer 110. The packaged IC 100 further includes a first encapsulant 200 that surrounds a substantial portion of the processor 102 and the plurality of conductive posts 204, 208 and 216, the first encapsulant 200 contacting the fanout layer 110 on a first side and having an exposed second side.
In this example, the packaged IC 400 also includes RDL 222 having a first surface coupled to a second surface of the processor 102 and the exposed second side of the first encapsulant 200. A memory 104 couples to a second surface of the RDL 222 and is configured to communicate with the processor 102 through communication links formed by I/O contacts (e.g., short conductive posts 212) of the processor 102, the fanout layer 110, the plurality of conductive posts 204, the RDL 222, and data connections/conductive contacts 210 of the memory 104. Likewise, a plurality of conductive posts 208 disposed proximate at least one side of the memory 104 are coupled to the fanout layer 110 and conductive features of the of the RDL 222 which are coupled to power inputs/conductive contacts 206 of the memory 104. In an example, the power inputs 206 are arranged in a manner that allows relatively symmetric power delivery to the memory 104.
As shown in
In the illustrated embodiment, a second encapsulant 202 surrounds a portion of the memory 104 and the RDL 222, and a second plurality of TMVs or conductive posts 218 extends from the first plurality of TMVs or conductive posts 216 through the second encapsulant 202 (for providing connections between the fanout layer 110 and a POP memory 106). In an example, connections between the POP memory 106 and the processor 102 are provided by conductive features 224 of the fanout layer 110 (explicit connections between the conductive features 224 and the processor 102 have been omitted in
The fabrication flow proceeds as shown in
In the fabrication step illustrated by
The fabrication flow continues as shown in
The fabrication flow proceeds as shown in
Referring to
Operations 600 continue with placing a Redistribution Layer (RDL) on the exposed second side of the first encapsulant, wherein a first side of the RDL is disposed adjacent to and extending beyond the second side of the memory (step 608), and forming second level conductive posts on a second side of the RDL (step 610). Operations 600 further include placing a processor on the second side of the RDL such that a first portion of the memory is disposed outside a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor (step 612). In addition, the second level conductive posts and the processor are encapsulated with second encapsulant that contacts the second side of the RDL and has an exposed second side (step 614). Operations 600 further include forming a fanout layer on the exposed second side of the second encapsulant, such that a first plurality of the second level conductive posts provide data communication links, via the RDL, between the processor and the memory, a second plurality of the second level conductive posts are coupled, via the RDL, to power inputs of the memory, and the first level conductive posts and a third plurality of the second level conductive posts form Through Mold Vias (TMVs) extending between the carrier substrate and the fanout layer (step 616).
As may be used herein, the terms “processor” and/or “processing unit” or their equivalents (such as identified above) may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. A processor and/or processing unit may further include memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of another processor and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processor and/or processing unit includes more than one processing device, the processing devices may be directly coupled together via a wired and/or wireless bus structure.
One or more embodiments of the disclosure have been described above with the aid of method steps illustrating the performance of specified fabrication functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified fabrication functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claims. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined if the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant fabrication functionality. To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the present disclosure.
In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without necessarily departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and may be made without departing from the spirit and scope disclosed herein.
The one or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples of the disclosure. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from Figure to Figure, the embodiments may incorporate the same or similarly named structures, steps, components, etc. that may use the same or different reference numbers and, as such, the structures, steps, components, etc. may be the same or similar structures, steps, components, etc. or different ones.
This application is a continuation of PCT Patent Application No. PCT/US2019/049708 entitled “MULTI-SIDE POWER DELIVERY IN STACKED MEMORY PACKAGING”, filed Sep. 5, 2019, which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/US2019/049708 | Sep 2019 | US |
| Child | 17687220 | US |
