Data storage devices generally operate to store and retrieve data in a fast and efficient manner. Some storage devices utilize a semiconductor array of solid-state memory cells to store individual bits of data. Such memory cells can be volatile (e.g., DRAM, SRAM) or non-volatile (RRAM, STRAM, flash, etc.).
As will be appreciated, volatile memory cells generally retain data stored in memory only so long as operational power continues to be supplied to the device, while non-volatile memory cells generally retain data storage in memory even in the absence of the application of operational power.
In these and other types of data storage devices, it is often desirable to increase efficiency of memory cell formation, particularly with regard to the reading of data from the memory cell.
Various embodiments of the present invention are generally directed to a method and apparatus for forming a non-volatile memory cell, such as but not limited to a PCM memory cell.
In accordance with various embodiments, a first electrode is connected to a source while a second electrode is connected to a ground. An ionic region is located between the first and second electrodes and comprises a doping layer, composite layer, and electrolyte layer. The composite layer has a low resistive state and the electrolyte layer switches from a high resistive state to a low resistive state based on the presence of a filament.
In other embodiments, an electrolyte layer is deposited on a first electrode. A composite layer is coupled to the electrolyte layer and a doping layer is deposited onto the composite layer. A second electrode is coupled to the doping layer, wherein the composite layer has a low resistive state and the electrolyte layer that switches between a low resistive state and a high resistive state based on the presence of a filament.
These and various other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings.
Top level control of the device 100 is carried out by a suitable controller 102, which may be a programmable or hardware based microcontroller. The controller 102 communicates with a host device via a controller interface (I/F) circuit 104 and a host I/F circuit 106. Local storage of requisite commands, programming, operational data, etc. is provided via random access memory (RAM) 108 and read-only memory (ROM) 110. A buffer 112 serves to temporarily store input write data from the host device and readback data pending transfer to the host device.
A memory space is shown at 114 to comprise a number of memory arrays 116 (denoted Array 0-N), although it will be appreciated that a single array can be utilized as desired. Each array 116 comprises a block of semiconductor memory of selected storage capacity. Communications between the controller 102 and the memory space 114 are coordinated via a memory (MEM) I/F 118. As desired, on-the-fly error detection and correction (EDC) encoding and decoding operations are carried out during data transfers by way of an EDC block 120.
While not limiting, in some embodiments the various circuits depicted in
Any number of data storage and transfer protocols can be utilized, such as logical block addressing (LBAs) whereby data are arranged and stored in fixed-size blocks (such as 512 bytes of user data plus overhead bytes for ECC, sparing, header information, etc). Host commands can be issued in terms of LBAs, and the device 100 can carry out a corresponding LBA-to-PBA (physical block address) conversion to identify and service the associated locations at which the data are to be stored or retrieved.
The actual configurations of the cells and the access lines thereto will depend on the requirements of a given application. Generally, however, it will be appreciated that the various control lines will generally include enable lines that selectively enable and disable the respective writing and reading of the value(s) of the individual cells.
Control logic 126 receives and transfers data, addressing information and control/status values along multi-line bus paths 128, 130 and 132, respectively. X and Y decoding circuitry 134, 136 provide appropriate switching and other functions to access the appropriate cells 124. A write circuit 138 represents circuitry elements that operate to carry out write operations to write data to the cells 124, and a read circuit 140 correspondingly operates to obtain readback data from the cells 124. Local buffering of transferred data and other values can be provided via one or more local registers 144. At this point it will be appreciated that the circuitry of
Data are written to the respective memory cells 124 as generally depicted in
As explained below, in some embodiments the memory cell 124 takes a modified RRAM configuration, in which case the write power source 146 is characterized as a current driver connected through a memory cell 124 to a suitable reference node 148, such as ground. The write power source 146 provides a stream of power by moving through a material in the memory cell 124.
The cell 124 may take either a relatively low resistance (RL) or a relatively high resistance (RH). While not limiting, exemplary RL values may be in the range of about 1000 ohms (Ω) or so, whereas exemplary RH values may be in the range of about 2000Ω or so. Other resistive memory type configurations (e.g., RRAMS) are supplied with a suitable voltage or other input, but provide a much broader range of resistance values (RL˜100Ω and RH·10 MΩ). These values are retained by the respective cells until such time that the state is changed by a subsequent write operation. While not limiting, in the present example it is contemplated that a high resistance value (RH) denotes storage of a logical 1 by the cell 124, and a low resistance value (RL) denotes storage of a logical 0.
The logical bit value(s) stored by each cell 124 can be determined in a manner such as illustrated by
The voltage reference VREF can be selected from various embodiments such that the voltage drop VMC across the memory cell 124 will be lower than the VREF value when the resistance of the cell is set to RL, and will be higher than the VREF value when the resistance of the cell is set to RH. In this way, the output voltage level of the comparator 154 will indicate the logical bit value (0 or 1) stored by the memory cell 124.
A memory cell 180 operated in accordance with various embodiments of the present invention is generally illustrated in
It can be appreciated by one skilled in the art that electrolyte layer 198 can comprise a solid state electrolyte material that is ionically conductive. Further, the doping layer 196 can comprise a doped metal rich material. The formation of the memory cell can be defined by, but not limited to, nano-trench, hard mask, or etch post cell material deposition. In addition, a cross-bar or pin contact structure can be utilized to define the memory cell 180.
In
A flow diagram of a cell formation operation 220 performed in accordance with the various embodiments of the present invention is shown in
Further in some embodiments, the composite layer 202 is constructed to have a low resistance. A third base 236 is formed by depositing a doping layer 196 on the composite layer 202. For example, in the case of superionic embedded chalcogenide, a doping layer 196 can be deposited in sequence with chalcogenide materials due to the composite layer's low resistance. In the case of superionic or metal doping inside the oxide materials of a composite layer, co-sputtering can be utilized by controlling the ratio of superionic phase to oxide by deposition and the conductive composite layer 202 can be grown directly. In alternative embodiments, a heat treatment or UV application may be undertaken, but is not required. It can be appreciated that various methods can be used to create the composite layer 202; however, the components of the layer must be an electrical conductor initially due to a self-promoted chemical reaction between the layers or by a doping affect. The result of the low resistance state of the composite layer 202 is that the filament 200 shown in
In addition, the function of composite layer 202 is essential to the operation of the memory cell 180. The low resistance state of the composite layer 202 that is different from the resistance of the doping metal in the doping layer 196 effectively regulates the ionic flow from the adjacent doping layer 196 to the electrolyte layer 198. Due to the relative high bonding energy of doping metal ion inside the composite layer 202, it does not supply metal ion as easily as the conventional memory cell 158.
Finally, a memory cell 238 is completed by the coupling of a second electrode layer 186 to the doping layer 196. Furthermore, the separation of the metal ion supply from the filament forming layer lowers the stress associated with the switching rate and cell retention. The electrolyte layer 198 thickness can also be reduced by using high ionically conductive and high breakdown materials while the composite layer 202 regulating the metal ion supply to the electrolyte layer 198.
As can be appreciated by one skilled in the art, the various embodiments illustrated herein provide advantages in both memory cell efficiency and complexity due to the separation of the filament forming layer and the metal ion supply. The regulation of the migration of metal ions from the doping layer 198 to the electrolyte layer 198 provides heightened performance. Moreover, manufacturing accuracy can be greatly improved by reducing the complexity of the filament forming layer. However, it will be appreciated that the various embodiments discussed herein have numerous potential applications and are not limited to a certain field of electronic media or type of data storage devices.
It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this detailed description is illustrative only, and changes may be made in detail, especially in matters of structure and arrangements of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.