The present invention relates to nonvolatile switching devices having nanotube components and methods of forming such devices.
There is an ever-increasing demand for ever-denser memories that enable larger memory functions, both stand alone and embedded, ranging from 100's of kbits to memories in excess of 1 Gbit. These required larger memories at increasingly higher densities, sold in increasing volumes, and at lower cost per bit, are challenging the semiconductor industry to rapidly improve geometries and process features. For example, such demands drive photolithography technology to smaller line and spacing dimensions with corresponding improved alignment between layers, improved process features/structures such as smaller transistors and storage elements, but also including increased chip size required to accommodate larger memory function, or combined memory and logic function. Sensitivity to smaller defect size increases due to the smaller geometries, while overall defect densities must be significantly reduced.
When transitioning to a new denser technology node, lithography and corresponding process changes typically result in insulator and conductor dimensional reduction of 0.7× in the X and Y directions, or an area reduction of 2× for logic circuits and memory support circuits. Process features unique to the memory cell are typically added, resulting in an additional typical 0.7× area reduction beyond the area reduction resulting from photolithographic improvements, such that the memory cell achieves a cell area reduction of approximately 2.8×. In DRAMs, for example, a process feature change such as a buried trench or stacked storage capacitor is introduced with corresponding optimized cell contact means between one capacitor plate and the source of a cell select FET formed in the semiconductor substrate. The tradeoffs described with respect to DRAM memories are similar to those for other memory types such as EPROM, EEPROM, and Flash.
Memory efficiency is determined by comparing the bit storage area and the corresponding overhead of the support circuit area. Support circuit area is minimized with respect to array storage area. For 2-D memories, that is memories in which a cell select transistor is formed in a semiconductor substrate, for a transition to a denser new technology node (technology generation) the bit area may be reduced by more than the support circuit area as illustrated further above with respect to a memory example where the bit area is reduced by 2.8× while the support circuit area is reduced by 2×. In order to preserve memory efficiency, memory architecture may be changed such that larger sub-arrays are fabricated, that is sub-arrays with more bits per word line and more bits per bit line. In order continue to improve memory performance while containing power dissipation, new memory architectures use global and local (segmented) word line and global and local (segmented) bit line architectures to accommodate larger sub-arrays with more bits per word and bit lines as described for example in U.S. Pat. No. 5,546,349, the entire contents of which are incorporated herein by reference.
In addition to the growth in memory sub-array size, chip area may grow as well. For example, if the memory function at a new technology node is to have 4× more bits, then if the bit area reduction is 2.8×, chip area growth will be at least 1.4-1.5×.
Continuing with the memory example described further above, if the chip area of a memory at the present technology node is 60% bit area array and 40% support circuit area, then if chip architecture is not changed, and if bit area efficiency for a new technology node is improved by 2.8× while support circuit layout is improved by 2×, then bit area and support circuit areas will both be approximately 50% of chip area. Architecture changes and circuit design and layout improvements to increase the number of bits per word and bit lines, such as global and local segmented word and bit lines described in U.S. Pat. No. 5,546,349, may be used to achieve 60% bit area and 40% support circuits for a new 4× larger memory function chip design at a new technology node. However, the chip area will be 1.4× to 1.5× larger for the 4× the memory function. So for example, if the present chip area is 100 mm2, then the new chip area for a 4× larger memory will be 140 to 150 mm2; if the present chip area is 70 mm2, then the new chip area for a 4× larger memory function will be at least 100 mm2.
From a fabrication (manufacturing) point of view, transition to high volume production of a new 4× larger memory function at a new technology node does not occur until the cost per bit of the new memory function is competitive with that of the present generation. Typically, at least two and sometimes three new chips are designed with incremental reductions in photolithographic linear dimensions (shrinks) of 10 to 15% each, reducing chip area of the 4× memory function to 100 mm2 or less to increase the number of chips per wafer and reduce the cost per bit of memory to levels competitive with the present generation memory.
Crafts et al., U.S. Pat. No. 5,536,968, the entire contents of which are incorporated herein by reference, discloses a OTP field-programmable memory having a cell formed by a diode in series with a nonvolatile OTP element, in this patent a polysilicon fuse element. Each cell includes an as-formed polysilicon fuse of typically 100s of Ohms and a series select diode. The memory array is a 2-D memory array with a long folded narrow polyfuse element. If selected, milli-Amperes of current blow a selected polysilicon fuse which becomes nonconducting. The storage cell is large because of large polysilicon fuse dimensions, so the OTP memory described in U.S. Pat. No. 5,536,968 does not address the memory scaling problems describe further above.
Roesner, U.S. Pat. No. 4,442,507, the entire contents of which are incorporated herein by reference, discloses a one-time-programmable (OTP) field-programmable memory using a 3-dimensional (3-D) memory cell and corresponding process, design, and architecture to replace the 2-dimensional (2-D) memory approach of increasing chip area while reducing individual component size (transistors) and interconnections for each new generation of memory. U.S. Pat. No. 4,442,507 illustrates an EPROM (one-time-programmable) memory having a 3-D EPROM array in which cell select devices, storage devices, and interconnect means are not fabricated in or on a semiconductor substrate, but are instead formed on an insulating layer above support circuits formed in and on a semiconductor substrate with interconnections between support circuits and the 3-D EPROM memory array. Such a 3-D memory approach significantly reduces lithographic and process requirements associated with denser larger memory function.
3-D EPROM prior art array 100 illustrated in
N+ polysilicon patterned layer semiconductor 122 is used as one Schottky diode 142 contact and as an array interconnect line. N+ polysilicon semiconductor 122 may be silicon or germanium, for example, and is typically doped to 1020 dopant atoms/cm3 with a resistance of 0.04 Ohms/square. While semiconductor 122 may be used as an array line, a lower resistance array line may be formed by depositing N+ polysilicon semiconductor 122 on a molybdenum silicide conductor 120 between the N+ semiconductor layer and the surface of insulator 115. A second N− polycrystalline silicon or germanium semiconductor patterned layer (semiconductor) 125, in contact with semiconductor 122, is typically doped in the range of 1014 to 1017 dopant atoms/cm3, with a resistance of 15 Ohms/square and forms the cathode terminal of Schottky diode 142 which is used as a cell selection device. Dopants may be arsenic, phosphorous, and antimony for example. Polysilicon conductors 122 and 125 are typically 400 nm thick and 2 um in width.
The anode of Schottky diode device 142 is formed by patterned conductor 140 using a noble metal such as platinum of thickness 25 nm deposited on N− polycrystalline silicon conductor 125, and heated to 600 degrees C. to form a compound (e.g. platinum silicide) with the underlying polycrystalline material. The silicide of noble metal 140 and the underlying N− polysilicon semiconductor 125 forms junction 145 of Schottky diode 142. Schottky diode 142 measurements resulted in a turn-on voltage of approximately 0.4 volts and a reverse breakdown voltage of approximately 10 volts.
The nonvolatile state of the memory cell is stored in antifuse 155 as a resistive state. The resistive state of antifuse 155 is alterable (programmable) once (OTP) after the fabrication process is complete. Preferably, the material 150 used to form antifuse 155 is a single element N−semiconductor such as silicon or germanium, typically having a doping of less than 1017 atoms/cm3, where arsenic and phosphorous are suitable N-type dopants as described further in U.S. Pat. No. 4,442,507. After patterning to form antifuse 155, a conductive barrier layer 160 of TiW 100 nm thick is deposited in contact with antifuse 155 and insulator 130. Then, an 800 nm aluminum layer is deposited and patterned to form conductor 170. Both conductor 170 and conductive barrier layer 160 are patterned. Conductive barrier layer 160 is used to prevent aluminum from migrating into the N− polysilicon material 150.
The resistance of the antifuse is typically 107 ohms as formed. Initially, all antifuses in all cells have a resistance value of approximately 107 ohms as-fabricated. If a cell is selected and programmed such that an antifuse threshold voltage of approximately 10 volts is reached, then the antifuse resistance changes to 102 ohms, with programming current limited to approximately 50 uA, and with programming time in the microsecond range. An antifuse may be programmed only once, and the nonvolatile new lower resistance state stored in a memory cell of the 3-D EPROM memory with the array region above underlying support circuits 110 in and on semiconductor substrate 105.
While U.S. Pat. No. 4,442,507 introduces the concept of 3-D EPROM memory arrays having all cell components and interconnections decoupled from a semiconductor substrate, and above support circuits, the approach is limited to OTP memories.
Prior art
U.S. Pat. No. 5,670,803, the entire contents of which are incorporated herein by reference, to co-inventor Bertin, discloses a 3-D SRAM array structure with simultaneously defined sidewall dimensions. This structure includes vertical sidewalls simultaneously defined by trenches cutting through multiple layers of doped silicon and insulated regions in order avoid (minimize) multiple alignment steps. These trenches cut through multiple semiconductor and oxide layers and stop on the top surface of a supporting insulator (SiO2) layer between the 3-D SRAM array structure and an underlying semiconductor substrate. U.S. Pat. No. 5,670,803 also teaches in-trench vertical local cell interconnect wiring within a trench region to form a vertically wired 3-D SRAM cell. U.S. Pat. No. 5,670,803 also teaches through-trench vertical interconnect wiring through a trench region to the top surface of a 3-D SRAM storage cell that has been locally wired within a trench cell.
The present invention provides nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same.
Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.
One or more embodiments include one or more of the following features. In a first logic state of the plurality of logic states a conductive pathway between the first and second terminals is substantially disabled and in a second logic state of the plurality of logic states a conductive pathway between the first and second terminals is enabled. In the first logic state the nanotube article has a relatively high resistance and in the second logic state the nanotube article has a relatively low resistance. The nanotube fabric article includes a non-woven network of unaligned nanotubes. In the second logic state the non-woven network of unaligned nanotubes includes at least one electrically conductive pathway between the semiconductor element and the second terminal. The nanotube fabric article is a multilayered fabric. The nanotube fabric article includes a first plurality of nanotubes and a second plurality of additional nanoscopic material particles. In the second logic state the plurality of nanotubes provides at least one electrically conductive pathway between the semiconductor element and the second terminal. Above a threshold voltage between the first and second terminals, the semiconductor element is capable of flowing current from the anode to the cathode and below the threshold voltage between the first and second terminals the semiconductor element is not capable of flowing current from the anode to the cathode. In the first logic state, the conductive pathway between the anode and the second terminal is disabled. In the second logic state, the conductive pathway between the anode and the second terminal is enabled. A conductive contact interposed between and providing an electrical communication pathway between the nanotube fabric article and the semiconductor element. The first terminal is in electrical communication with the anode and the cathode is in electrical communication with the conductive contact of the nanotube switching element. In the second logic state, the device is capable of carrying electrical current substantially flowing from the first terminal to the second terminal. The first terminal is in electrical communication with the cathode and the anode is in electrical communication with the conductive contact of the nanotube switching element. When in the second logic state, the device is capable of carrying electrical current substantially flowing from the second terminal to the first terminal. The anode includes a conductive material and the cathode includes an n-type semiconductor material. The anode includes a p-type semiconductor material and the cathode includes a n-type semiconductor material.
Under another aspect, a two-terminal non-volatile state device includes: first and second terminals; a semiconductor field effect element having a source, a drain, a gate in electrical communication with one of the source and the drain, and a channel disposed between the source and the drain, the gate capable of controllably forming an electrically conductive pathway in the channel between the source and the drain; a nanotube switching element having a nanotube fabric article and a conductive contact, the nanotube fabric article disposed between and capable of forming an electrically conductive pathway between the conductive contact and the second terminal; wherein the first terminal is in electrical communication with one of the source and the drain, the other of the source and drain is in electrical communication with the conductive contact; and wherein a first set of electrical stimuli on the first and second conductive terminals causes a first logic state and a second set of electrical stimuli on the first and second conductive terminals causes a second logic state.
One or more embodiments include one or more of the following features. The first logic state corresponds to a relatively non-conductive pathway between the first and second terminals and the second logic state corresponds to a conductive pathway between the first and second terminals. The first set of electrical stimuli causes a relatively high resistance state in the nanotube fabric article and the second set of electrical stimuli causes a relatively low resistance state in the nanotube fabric article. The nanotube fabric article includes a non-woven network of unaligned nanotubes. The nanotube fabric article includes a multilayered fabric. In response to the second set of electrical stimuli, the non-woven network of unaligned nanotubes provides at least one electrically conductive pathway between the conductive contact and the semiconductor field-effect element. In response to the second set of electrical stimuli, a conductive pathway between the source and the drain is formed in the conductive channel. The semiconductor field effect element includes a PFET. The semiconductor field effect element includes a NFET. The source of the semiconductor field-effect element is in electrical communication with the first terminal and the drain is in electrical communication with the conductive contact of the nanotube switching element. The drain of the semiconductor field-effect element is in electrical communication with the first terminal and the source of the is in electrical communication with the conductive contact of the nanotube switching element.
Under another aspect, a voltage selection circuit includes: an input voltage source; an output voltage terminal and a reference voltage terminal; a resistive element; and a nonvolatile nanotube diode device including: first and second terminals; a semiconductor element in electrical communication with the first terminal; a nanotube switching element disposed between and capable of conducting electrical stimulus between the semiconductor element and the second terminal; wherein the nonvolatile nanotube diode device is capable of conducting electrical stimulus between the first and second terminals, wherein the resistive element is disposed between the input voltage source and the output voltage terminal, the nonvolatile nanotube diode device is disposed between and in electrical communication with the output voltage terminal and the reference voltage terminal, and wherein the voltage selection circuit is capable of providing a first output voltage level when, in response to electrical stimulus at the input voltage source and the reference voltage terminal, the nonvolatile nanotube diode substantially prevents the conduction of electrical stimulus between the first and second terminals and wherein the voltage selection circuit is capable of providing a second output voltage level when, in response to electrical stimulus at the input voltage source and the reference voltage terminal, the nonvolatile nanotube diode conducts electrical stimulus between the first and second terminals.
One or more embodiments include one or more of the following features. The semiconductor element includes an anode and a cathode, the anode in electrical communication with the first terminal and the cathode in communication with the nanotube switching element. The semiconductor element includes a field effect element having a source region in communication with the first terminal, a drain region in electrical communication with the nanotube switching element, a gate region in electrical communication with one of the source region and the drain region, and a channel region capable of controllably forming and unforming an electrically conductive pathway between the source and the drain in response to electrical stimulus on the gate region. The first output voltage level is substantially equivalent to the input voltage source. The second output voltage level is substantially equivalent to the reference voltage terminal. The nanotube switching element includes a nanotube fabric article capable of a high resistance state and a low resistance state. The high resistance state of the nanotube fabric article is substantially higher than the resistance of the resistive element and wherein the low resistance state of the nanotube fabric article is substantially lower than the resistance of the resistive element. The first output voltage level is determined, in part, by the relative resistance of the resistive element and the high resistance state of the nanotube fabric article, and wherein the second output voltage level is determined, in part, by the relative resistance of the resistive element and the low resistance state of the nanotube fabric article.
Under another aspect, a nonvolatile nanotube diode includes a substrate; a semiconductor element disposed over the substrate, the semiconductor element having an anode and a cathode and capable of forming an electrically conductive pathway between the anode and the cathode; a nanotube switching element disposed over the semiconductor element, the nanotube switching element including a conductive contact and a nanotube fabric element capable of a plurality of resistance states; and a conductive terminal disposed in spaced relation to the conductive contact, wherein the nanotube fabric element is interposed between and in electrical communication with the conductive contact and the conductive contact is in electrical communication with the cathode, and wherein in response to electrical stimuli applied to the anode and the conductive terminal, the nonvolatile nanotube diode is capable of forming an electrically conductive pathway between the anode and the conductive terminal.
One or more embodiments include one or more of the following features. The anode includes a conductor material and the cathode includes a semiconductor material. The anode material includes at least one of Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2 and ZrSi2. The semiconductor element includes a Schottky barrier diode. A second conductive terminal interposed between the substrate and the anode, the second conductive terminal in electrical communication with the anode, wherein in response to electrical stimuli at said second conductive terminal and the conductive terminal, the nonvolatile nanotube diode is capable of forming an electrically conductive pathway between said second conductive terminal and the conductive terminal. The anode includes a semiconductor material of a first type and the cathode region includes a semiconductor material of a second type. The semiconductor material of the first type is positively doped, the semiconductor material of the second type is negatively doped, and the semiconductor element forms a PN junction. The nanotube fabric element is substantially vertically disposed. The nanotube fabric element is substantially horizontally disposed. The nanotube fabric element includes a nonwoven multilayered fabric. The nanotube fabric element has a thickness between approximately 20 nm and approximately 200 nm. The conductive contact is disposed substantially coplanar to a lower surface of the nanotube fabric element and the conductive terminal is disposed substantially coplanar to an upper surface of the nanotube fabric element. The semiconductor element is a field effect transistor.
Under another aspect, a nonvolatile nanotube diode includes a substrate; a conductive terminal disposed over the substrate; a semiconductor element disposed over the conductive terminal, the semiconductor element having a cathode and an anode and capable of forming an electrically conductive pathway between the cathode and the anode; and a nanotube switching element disposed over the semiconductor element, the nanotube switching element including a conductive contact and nanotube fabric element capable of a plurality of resistance states, wherein the nanotube fabric element is interposed between and in electrical communication with anode and the conductive contact and cathode is in electrical communication with the conductive terminal, and wherein in response to electrical stimuli applied to the anode and the conductive terminal, the nonvolatile nanotube diode is capable of forming an electrically conductive pathway between the conductive terminal and the conductive contact.
One or more embodiments include one or more of the following features. The anode includes a conductor material and the cathode includes a semiconductor material. The anode material includes at least one of Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn, CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2 and ZrSi2. The semiconductor element includes a Schottky barrier diode. A second conductive terminal interposed between and providing an electrically conductive path between the anode and the patterned region of nonwoven nanotube fabric. The anode includes a semiconductor material of a first type and the cathode region includes a semiconductor material of a second type. The semiconductor material of the first type is positively doped, the semiconductor material of the second type is negatively doped, and the semiconductor element forms a PN junction. The nanotube fabric element is substantially vertically disposed. The nanotube fabric element is substantially horizontally disposed. The nanotube fabric element includes a layer of nonwoven nanotubes having a thickness between approximately 0.5 and approximately 20 nanometers. The nanotube fabric element includes a nonwoven multilayered fabric. The conductive contact is disposed substantially coplanar to a lower surface of the nanotube fabric element and the conductive terminal is disposed substantially coplanar to an upper surface of the nanotube fabric element. The semiconductor element includes a field effect transistor.
Under another aspect, a memory array includes a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell responsive to electrical stimulus on a word line and on a bit line, each memory cell including: a two-terminal non-volatile nanotube switching device including a first and a second terminal, a semiconductor diode element, and a nanotube fabric article, the semiconductor diode and a nanotube article disposed between and in electrical communication with the first and second terminals, wherein the nanotube fabric article is capable of a plurality of resistance states, and wherein the first terminal is coupled to the one word line and the second terminal is coupled to the one bit line, the electrical stimulus applied to the first and second terminals capable of changing the resistance state of the nanotube fabric article; and a memory operation circuit operably coupled to each bit line of the plurality of bit lines and each word line of the plurality of word lines, said operation circuit capable of selecting each of the cells by activating at least one of the bit line and the word line coupled to that cell to apply a selected electrical stimulus to each of the corresponding first and second terminals, and said operation circuit further capable of detecting a resistance state of the nanotube fabric article of a selected memory cell and adjusting the electrical stimulus applied to each of the corresponding first and second terminals in response to the resistance state to controllably induce a selected resistance state in the nanotube fabric article, wherein the selected resistance state of the nanotube fabric article of each memory cell corresponds to an informational state of said memory cell.
One or more embodiments include one or more of the following features. Each memory cell nonvolatily stores the corresponding information state in response to electrical stimulus applied to each of the corresponding first and second terminals. The semiconductor diode element includes a cathode and an anode, the anode in electrical communication with the second terminal and the cathode in electrical communication with the nanotube switching element. The cathode includes a first semiconductor material and the anode includes a second semiconductor material. The semiconductor diode element includes a cathode and an anode, the cathode in electrical communication with the first terminal and the anode in electrical communication with the nanotube switching element. The cathode includes a first semiconductor material and the anode includes a second semiconductor material. The cathode includes a semiconductor material and the anode includes a conductive material and forms a conductive contact to the nanotube fabric article. A conductive contact interposed between the semiconductor diode element and the nanotube fabric article. The nanotube fabric article includes a network of unaligned nanotubes capable of providing at least one electrically conductive pathway between the first conductive contact and one of the first and second terminals. The nanotube fabric article includes a multilayered nanotube fabric. The multilayered nanotube article has a thickness that defines a spacing between the conductive contact and one of the first and second conductive terminals. The plurality of memory cells includes multiple pairs of stacked memory cells, wherein a first memory cell in each pair of stacked memory cells is disposed above and in electrical communication with a first bit line and the word line is disposed above and in electrical communication with the first memory cell; and wherein a second memory cell in each pair of stacked memory cells is disposed above and in electrical communication with the word line and a second bit line is disposed above and in electrical communication with the second memory cell. The resistance state of the nanotube article in the first memory cell is substantially unaffected by the resistance state of the nanotube article in the second memory cell and the resistance state of the nanotube article in the second memory cell is substantially unaffected by the resistance state of the nanotube article in the first memory cell. The resistance state of the nanotube article in the first memory cell is substantially unaffected by said operation circuit selecting the second memory cell and the resistance state of the nanotube article in the second memory cell is substantially unaffected by the resistance state by said operation circuit selecting the first memory cell. The resistance state of the nanotube article in the first memory cell is substantially unaffected by said operation circuit detecting a resistance state of the nanotube fabric article of the second memory cell and the resistance state of the nanotube article in the second memory cell is substantially unaffected by the resistance state by said operation circuit detecting a resistance state of the nanotube fabric article of the first memory cell. The resistance state of the nanotube article in the first memory cell is substantially unaffected by said operation circuit adjusting the electrical stimulus applied to each of the corresponding first and second terminals of the second memory cell and the resistance state of the nanotube article in the second memory cell is substantially unaffected by the resistance state by said operation circuit adjusting the electrical stimulus applied to each of the corresponding first and second terminals of the first memory cell. An insulating region and a plurality of conductive interconnects wherein the insulating region is disposed over the memory operation circuit, the plurality of memory cells are disposed over the insulating region, and the plurality of conductive interconnects operably couple the memory operation circuit to the plurality of bit lines and plurality of word lines. Adjusting the electrical stimulus includes incrementally changing the voltage applied to each of the corresponding first and second terminals. Incrementally changing the voltage includes applying voltage pulses. Amplitudes of subsequent voltage pulses are incrementally increased by approximately 200 mV. Adjusting the electrical stimulus includes changing the current supplied to at least one of the corresponding first and second terminals. Substantially removing electrical stimulus from the corresponding bit line and word line after controllably inducing the selected resistance state in the nanotube fabric article to substantially preserve the selected resistance state of the nanotube fabric article. Detecting the resistance state of the nanotube fabric article further includes detecting a variation over time of electrical stimulus on a corresponding bit line. Detecting the resistance state of the nanotube fabric article further includes detecting a current flow though a corresponding bit line. In each two terminal nonvolatile nanotube switching device, current is capable of flowing from the second terminal to the first terminal and substantially prevented from flowing from the first terminal to the second terminal. Current is capable of flowing from the second terminal to the first terminal when a threshold voltage is reached by applying electrical stimulus to each of the corresponding first and second terminals. The selected resistance state of the nanotube fabric article of each memory cell includes one of a relatively high resistance state corresponding to a first informational state of said memory cell and a relatively low resistance state corresponding to a second informational state of said memory cell. A third information state of each memory cell corresponds to a state in which current is capable of flowing from the second terminal to the first terminal and wherein a fourth information state of each memory cell corresponds to a state in which current is substantially prevented from flowing from the first terminal to the second terminal. The two-terminal non-volatile nanotube switching device is operable independently of the voltage polarity between the first and second terminals. The two-terminal non-volatile nanotube switching device is operable independently of the direction of current flow between the first and second terminals. The plurality of memory cells includes multiple pairs of stacked memory cells, wherein a first memory cell in each pair of stacked memory cells is disposed above and in electrical communication with a first bit line and the word line is disposed above and in electrical communication with the first memory cell; wherein an insulator material is disposed over the first memory cell; wherein a second memory cell in each pair of stacked memory cells is disposed above and in electrical communication with a second word line, the second word line disposed over the insulator material and wherein a second bit line is disposed above and in electrical communication with the second memory cell. The plurality of memory cells includes multiple pairs of stacked memory cells, wherein a first memory cell in each pair of stacked memory cells is disposed above and in electrical communication with a first bit line and the word line is disposed above and in electrical communication with the first memory cell; wherein an insulator material is disposed over the first memory cell; wherein a second memory cell in each pair of stacked memory cells is disposed above and in electrical communication with a second bit line, the second bit line disposed over the insulator material and wherein a second word line is disposed above and in electrical communication with the second memory cell.
Under another aspect, a method of making a nanotube switch includes: providing a substrate having a first conductive terminal; depositing a multilayer nanotube fabric over the first conductive terminal; and depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a thickness, density, and composition selected to prevent direct physical and electrical contact between the first and second conductive terminals.
One or more embodiments include one or more of the following features. Lithographically patterning the first and second conductive terminals and the multilayer nanotube fabric so as to each have substantially the same lateral dimensions. The first and second conductive terminals and the multilayer nanotube fabric each have a substantially circular lateral shape. The first and second conductive terminals and the multilayer nanotube fabric each have a substantially rectangular lateral shape. The first and second conductive terminals and the multilayer nanotube fabric each have lateral dimensions of between about 200 nm×200 nm and about 22 nm×22 nm. The first and second conductive terminals and the multilayer nanotube fabric each have a lateral dimension of between about 22 nm and about 10 nm. The first and second conductive terminals and the multilayer nanotube fabric each have a lateral dimension of less than 10 nm. The multilayer nanotube fabric has a thickness between about 10 nm and about 200 nm. The multilayer nanotube fabric has a thickness between about 10 nm and about 50 nm. The substrate includes a diode under the first conductive terminal, the diode being addressable by control circuitry. Lithographically patterning the first and second conductive terminals, the multilayer nanotube fabric, and the diode so as to each have substantially the same lateral dimensions. Providing a second diode over the second conductive terminal, depositing a third conductive terminal over the second diode, depositing a second multilayer nanotube fabric over the third conductive terminal, and depositing a fourth conductive terminal over the second multilayer nanotube fabric. Lithographically patterning the multilayer nanotube fabrics, the diodes, and the conductive terminals so as to each have substantially the same lateral dimensions. The diode includes a layer of N+ polysilicon, a layer of N polysilicon, and a layer of conductor. The diode includes a layer of N+ polysilicon, a layer of N polysilicon, and a layer of P polysilicon. Providing a diode over the second conductive terminal, the diode being addressable by control circuitry. Annealing the diode at a temperature exceeding 700° C. Lithographically patterning the first and second conductive terminals, the multilayer nanotube fabric, and the diode so as to each have substantially the same lateral dimensions. The substrate includes a semiconductor field effect transistor, at least a portion of which is under the first conductive terminal, the semiconductor field effect transistor being addressable by control circuitry. Depositing the multilayer nanotube fabric includes spraying nanotubes dispersed in a solvent onto the first conductive terminal. Depositing the multilayer nanotube fabric includes spin coating nanotubes dispersed in a solvent onto the first conductive terminal. Depositing the multilayer nanotube fabric includes depositing a mixture of nanotubes and a matrix material dispersed in a solvent onto the first conductive terminal. Removing the matrix material after depositing the second conductive terminal. The matrix material includes polypropylene carbonate. The first and second conductive terminals each include a conductive material independently selected from the group consisting of Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSix, and TiSix. Depositing a porous dielectric material on the multilayer nanotube fabric. The porous dielectric material includes one of a spin-on glass and a spin-on low-κ dielectric. Depositing a nonporous dielectric material on the multilayer nanotube fabric. The nonporous dielectric material includes a high-κ dielectric. The nonporous dielectric material includes hafnium oxide. Providing a word line in electrical communication with the second conductive terminal.
Under another aspect, a method of making a nanotube diode includes: providing a substrate having a first conductive terminal; depositing a multilayer nanotube fabric over the first conductive terminal; depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a thickness, density, and composition selected to prevent direct physical and electrical contact between the first and second conductive terminals; and providing a diode in electrical contact with one of the first and second conductive terminals.
One or more embodiments include one or more of the following features. Providing the diode after depositing the multilayer nanotube fabric. Annealing the diode at a temperature exceeding 700° C. Positioning the diode over and in electrical contact with the second conductive terminal. Positioning the diode under and in electrical contact with the first conductive terminal. Lithographically patterning the first and second conductive terminals, the multilayer nanotube fabric, and the diode so as to each have substantially the same lateral dimensions. The first and second conductive terminals, the multilayer nanotube fabric, and the diode each have a substantially circular lateral shape. The first and second conductive terminals, the multilayer nanotube fabric, and the diode each have a substantially rectangular lateral shape. The first and second conductive terminals and the multilayer nanotube fabric each have lateral dimensions of between about 200 nm×200 nm and about 22 nm×22 nm.
Under another aspect, a non-volatile nanotube switch includes a first conductive terminal; a nanotube block including a multilayer nanotube fabric, at least a portion of the nanotube block being positioned over and in contact with at least a portion of the first conductive terminal; a second conductive terminal, at least a portion of the second conductive terminal being positioned over and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to prevent direct physical and electrical contact between the first and second conductive terminals; and control circuitry in electrical communication with and capable of applying electrical stimulus to the first and second conductive terminals, wherein the nanotube block is capable of switching between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second conductive terminals, and wherein, for each different electronic state of the plurality of electronic states, the nanotube block provides an electrical pathway of corresponding different resistance between the first and second conductive terminals.
One or more embodiments include one or more of the following features. Substantially the entire nanotube block is positioned over substantially the entire first conductive terminal, and wherein substantially the entire second conductive terminal is positioned over substantially the entire nanotube block. The first and second conductive terminals and the nanotube block each have a substantially circular lateral shape. The first and second conductive terminals and the nanotube block each have a substantially rectangular lateral shape. The first and second conductive terminals and the nanotube block each have a lateral dimension between about 200 nm and about 22 nm. The first and second conductive terminals and the nanotube block each have a lateral dimension between about 22 nm and about 10 nm. The first and second conductive terminals and the nanotube block each have lateral dimension of less than about 10 nm. The nanotube block has a thickness between about 10 nm and about 200 nm. The nanotube block has a thickness between about 10 nm and about 50 nm. The control circuitry includes a diode in direct physical contact with the first conductive terminal. The first conductive terminal is positioned over the diode. The diode is positioned over the second conductive terminal. The diode, the nanotube block, and the first and second conductive terminals have substantially the same lateral dimensions. The diode includes a layer of N+ polysilicon, a layer of N polysilicon, and a layer of conductor. The diode includes a layer of N+ polysilicon, a layer of N polysilicon, and a layer of P polysilicon. The control circuitry includes a semiconductor field effect transistor in contact with the first conductive terminal. The first and second conductive terminals each include a conductive material independently selected from the group consisting of Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSix, and TiSix. The nanotube block further includes a porous dielectric material. The porous dielectric material includes one of a spin-on glass and a spin-on low-κ dielectric. The nanotube block further includes a nonporous dielectric material. The nonporous dielectric material includes hafnium oxide.
Under another aspect, a high-density memory array includes: a plurality of word lines and a plurality of bit lines; a plurality of memory cells, each memory cell including: a first conductive terminal; a nanotube block over the first conductive terminal, the nanotube block including a multilayer nanotube fabric; a second conductive terminal over the nanotube block and in electrical communication with a word line of the plurality of word lines; and a diode in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals, wherein the nanotube block has a thickness that defines a spacing between the first and second conductive terminals, and wherein a logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell. The diode is positioned under the first conductive terminal. The diode is positioned over the second conductive terminal. The diode, the first and second conductive terminals, and the nanotube block all have substantially the same lateral dimensions. The diode, the first and second conductive terminals, and the nanotube block each have a substantially circular lateral shape. The diode, the first and second conductive terminals, and the nanotube block each have a substantially rectangular lateral shape. The diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 200 nm and about 22 nm. The memory cells are spaced from each other by between about 200 nm and about 22 nm. The first and second conductive terminals, and the nanotube block each have a lateral dimension between about 22 nm and about 10 nm. The memory cells of the array are spaced from each other by between about 220 nm and about 10 nm. Some memory cells of the array are laterally spaced relative to each other, and other memory cells of the array are stacked on top of each other. Some of the memory cells of the array that are stacked on top of each other share a bit line. Some of the memory cells of the array that are laterally spaced relative to each other share a word line. The plurality of word lines are substantially perpendicular to the plurality of bit lines. The thickness of the nanotube block is between about 10 nm and about 200 nm. The thickness of the nanotube block is between about 10 nm and about 50 nm.
Under another aspect, a high-density memory array includes: a plurality of word lines and a plurality of bit lines; a plurality of memory cells, each memory cell including: a first conductive terminal; a nanotube block over the first conductive terminal, the nanotube block including a multilayer nanotube fabric; a second conductive terminal over the nanotube block and in electrical communication with a bit line of the plurality of bit lines; and a diode in electrical communication with a word line of the plurality of word lines, wherein the nanotube block has a thickness that defines a spacing between the first and second conductive terminals, wherein a logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell. The diode is positioned under the first conductive terminal. The diode is positioned over the second conductive terminal. The diode, the first and second conductive terminals, and the nanotube block all have substantially the same lateral dimensions. The diode, the first and second conductive terminals, and the nanotube block each have a substantially circular lateral shape. The diode, the first and second conductive terminals, and the nanotube block each have a substantially rectangular lateral shape. The diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 200 nm and about 22 nm. The memory cells are spaced from each other by between about 200 nm and about 22 nm. The diode, the first and second conductive terminals, and the nanotube block each have a lateral dimension between about 22 nm and about 10 nm. The memory cells of the array are spaced from each other by between about 220 nm and about 10 nm. Some memory cells of the array are laterally spaced relative to each other, and other memory cells of the array are stacked on top of each other. Some of the memory cells of the array that are stacked on top of each other share a bit line. Some of the memory cell of the array that are laterally spaced relative to each other share a word line. The plurality of word lines are substantially perpendicular to the plurality of bit lines. The thickness of the nanotube block is between about 10 nm and about 200 nm. The thickness of the nanotube block is between about 10 nm and about 50 nm.
Under another aspect, a high-density memory array includes: a plurality of word lines and a plurality of bit lines; a plurality of memory cell pairs, each memory cell pair including: a first memory cell including a first conductive terminal, a first nanotube element over the first conductive terminal, a second conductive terminal over the nanotube element, and a first diode in electrical communication with one of the first and second conductive terminals and with a first bit line of the plurality of bit lines; and a second memory cell including a third conductive terminal, a second nanotube element over the first conductive terminal, a fourth conductive terminal over the nanotube element, and a second diode in electrical communication with one of the third and fourth conductive terminals and with a second bit line of the plurality of bit lines, wherein the second memory cell is positioned over the first memory cell, and wherein the first and second memory cell share a word line of the plurality of word lines; wherein each memory cell pair of the plurality of memory cells is capable of switching between at least four different resistance states corresponding to four different logic states in response to electrical stimuli at the first and second bit lines and the shared word line.
Under another aspect, a high-density memory array includes: a plurality of word lines and a plurality of bit lines; a plurality of memory cell pairs, each memory cell pair including: a first memory cell including a first conductive terminal, a first nanotube element over the first conductive terminal, a second conductive terminal over the nanotube element, and a first diode in electrical communication with one of the first and second conductive terminals and with a first word line of the plurality of word lines; and a second memory cell including a third conductive terminal, a second nanotube element over the first conductive terminal, a fourth conductive terminal over the nanotube element, and a second diode in electrical communication with one of the third and fourth conductive terminals and with a second word line of the plurality of word lines, wherein the second memory cell is positioned over the first memory cell, and wherein the first and second memory cell share a bit line of the plurality of bit lines; wherein each memory cell pair of the plurality of memory cells is capable of switching between at least four different resistance states corresponding to four different logic states in response to electrical stimuli at the first and second word lines and the shared bit line.
Under another aspect, a nanotube diode includes: a cathode formed of a semiconductor material; and an anode formed of nanotubes, wherein the cathode and the anode are in fixed and direct physical contact; and wherein the cathode and anode are constructed and arranged such that sufficient electrical stimulus applied to the cathode and the anode creates a conductive pathway between the cathode and the anode.
One or more embodiments include one or more of the following features. The anode includes a non-woven nanotube fabric having a plurality of unaligned nanotubes. The non-woven nanotube fabric includes a layer of nanotubes having a thickness between approximately 0.5 and approximately 20 nanometers. The non-woven nanotube fabric includes a block of nanotubes. The nanotubes include metallic nanotubes and semiconducting nanotubes. The cathode includes an n-type semiconductor material. A Schottky barrier is formed between the n-type semiconductor material and the metallic nanotubes. A PN junction is formed between the n-type semiconductor material and the semiconducting nanotubes. A PN junction is formed between the n-type semiconductor material and the semiconducting nanotubes. The Schottky barrier and the PN junction provide electrically parallel communication pathways between the cathode and the anode. Further in electrical communication with a nonvolatile memory cell, the nanotube diode capable of controlling electrical stimulus to the nonvolatile memory cell. Further in electrical communication with a nonvolatile nanotube switch, the nanotube diode capable of controlling electrical stimulus to the nonvolatile nanotube switch. Further in electrical communication with an electrical network of switching elements, the nanotube diode capable of controlling electrical stimulus to the electrical network of switching elements. Further in communication with a storage element, the nanotube diode capable of selecting the storage element in response to electrical stimulus. The storage element is nonvolatile. Further in communication with an integrated circuit, the nanotube diode operable as a rectifier for the integrated circuit.
Under another aspect, a nanotube diode includes: a conductive terminal; a semiconductor element disposed over and in electrical communication with the conductive terminal, wherein the semiconductor element forms a cathode; and a nanotube switching element disposed over and in fixed electrical communication with the semiconductor element, wherein the nanotube switching element forms an anode, wherein the nanotube switching element includes a conductive contact and nanotube fabric element capable of a plurality of resistance states, and wherein the cathode and the anode are constructed and arranged such that in response to sufficient electrical stimuli applied to the conductive contact and the conductive terminal, the nonvolatile nanotube diode is capable of forming an electrically conductive pathway between the conductive terminal and the conductive contact.
One or more embodiments include one or more of the following features. The nanotube fabric element includes a patterned region of nanotubes and the semiconductor element includes an n-type semiconductor material. The patterned region of nanotubes includes metallic nanotubes and semiconducting nanotubes. A Schottky barrier is formed between the n-type semiconductor material and the metallic nanotubes including the patterned region of nanotubes. A PN junction is formed between the n-type semiconductor material and the semiconducting nanotubes including the patterned region of nanotubes. The Schottky barrier and the PN junction provide electrically parallel communication pathways between the conducting terminal and the nanotube fabric element. Further in electrical communication with a nonvolatile memory cell, the nanotube diode capable of controlling electrical stimulus to the nonvolatile memory cell. Further in electrical communication with a nonvolatile nanotube switch, the nanotube diode capable of controlling electrical stimulus to the nonvolatile nanotube switch. Further in electrical communication with an electrical network of switching elements, the nanotube diode capable of controlling electrical stimulus to the electrical network of switching elements. Further in communication with a storage element, the nanotube diode capable of selecting the storage element in response to electrical stimulus. The storage element is nonvolatile. Further in communication with an integrated circuit, the nanotube diode operable as a rectifier for the integrated circuit.
Under another aspect of the invention, a composite non-volatile nanotube switch includes a first conductive terminal and a composite article comprising a plurality of nanoscopic particles, at least a portion of the article in electrical contact with at least a portion of the first conductive terminal. The switch includes a second conductive terminal, at least a portion of the second conductive terminal being in contact with at least a portion of the article, such that the article is physically and electrically interposed between the first and second conductive terminals and control circuitry in electrical communication with and capable of applying electrical stimulus to the first and second conductive terminals. The article is capable of switching among a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second conductive terminals. For each different electronic state of the plurality of electronic states, the article provides an electrical pathway of corresponding different resistance between the first and second conductive terminals.
One or more embodiments include one or more of the following features. The plurality of nanoscopic particles has a predefined composition comprising a first quanity of nanotubes and a second quantity of additional nanoscopic particles, a ratio between the first quantity and the second quantity being predefined. The ratio of the first quantity to the second quantity is predefined in accordance with the type of nanotubes, the type of nanotubes including one or more of single-walled, multi-walled, semiconducting, and metallic. The ratio of the first quantity to the second quantity is predefined in accordance with at least one attribute of the additional nanoscopic particles, the at least one attribute including one or more of physical dimensions, material type, and uniformity among particles. The ratio of the first quantity to the second quantity is predefined to tune the switching among a plurality of electronic states in response to the corresponding plurality of electrical stimuli applied by the control circuitry.
One or more embodiments include one or more of the following features. Substantially the entire article is positioned over substantially the entire first conductive terminal, and substantially the entire second conductive terminal is positioned over substantially the entire article. The article comprises a substantially thin layer of the plurality of nanoscopic particles, the plurality of nanoscopic particles including carbon nanotubes. The plurality of nanoscopic particles further includes amorphous carbon and wherein the article comprises a mixture of said plurality of nanoscopic particles. The first conductive terminal comprises a portion of a first conductive trace and the second conductive terminal comprises a portion of a second conductive trace. The first conductive trace and the second conductive trace are aligned in an orientation substantially perpendicular to one another. The first and second conductive terminals and the nanotube article each have a lateral dimension between about 200 nm and about 10 nm. The first and second conductive terminals and the article each have lateral dimension of less than about 10 nm. The article has a thickness between about 10 nm and about 200 nm. The control circuitry includes a diode in direct physical contact with the first conductive terminal. The control circuitry includes a diode in direct physical contact with the second conductive terminal. The plurality of electronic states comprises a low resistance state and a high resistance state. The plurality of electronic states comprises three or more resistance states. The diode comprises a layer of N+ polysilicon, a layer of N polysilicon, and a layer of conductor. The diode comprises a layer of N+ polysilicon, a layer of N polysilicon, and a layer of P polysilicon. The control circuitry includes a semiconductor field effect transistor in contact with the first conductive terminal. The plurality of nanoscopic particles comprises an electrically conductive, active carbon material. The plurality of nanoscopic particles comprises an electrically non-conductive, active carbon material. The plurality of nanoscopic particles comprises an electrically non-conductive, inert additional material. The plurality of nanoscopic particles forming the article vary between electrically conductive and electrically non-conductive states in response to plurality of electrical stimuli applied by the control circuitry to the first and second conductive terminals. The plurality of nanoscopic particles comprise carbon having one or more allotropic forms. The one or more allotropic forms include amorphous carbon, graphite, graphene, Buckminster-fullerenes such as but not limited to C20, C26, C28, C36, C50, C60, C70, C72, C76, C84, C540, carbon nanotubes, diamond and combinations thereof. The article comprising the plurality of nanoscopic particles includes silicon oxide, silicon nitride, and mixtures thereof. The plurality of nanoscopic particles and the silicon oxide, silicon nitride, or mixtures thereof form either a substantially homogeneous mixture. The article is capable of switching among a plurality of electronic states is responsive to a corresponding plurality of electrical stimuli less than approximately 5V.
Under another aspect of the invention, a high-density composite memory array includes a plurality of word lines and a plurality of bit lines and a plurality of memory cells. Each memory cell includes: a first conductive terminal, a composite article in physical and electrical contact with the first conductive terminal, the article comprising a plurality of nanoscopic particles, a second conductive terminal in physical and electrical contact with the article and in electrical communication with a word line of the plurality of word lines and select circuitry in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals. The article has a physical dimension that defines a spacing between the first and second conductive terminals such that the nanotube article is interposed between the first and second conducive terminals. A logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell.
One or more embodiments include one or more of the following features. The plurality of nanoscopic particles comprises an electrically conductive, active carbon material. The plurality of nanoscopic particles comprises an electrically non-conductive, active carbon material. The plurality of nanoscopic particles comprises an electrically non-conductive, inert additional material. The plurality of nanoscopic particles vary between electrically conductive and electrically non-conductive in response to plurality of electrical stimuli applied by the control circuitry to the first and second conductive terminals. The first and second conductive terminals, and the article comprising a plurality of nanoscopic particles each have a lateral dimension between about 200 nm and about 10 nm. The select circuitry comprises one of a diode and a semiconductor field-effect transistor. Adjacent memory cells comprising the array are spaced from each other by between about 220 nm and about 10 nm. The plurality of nanoscopic particles include carbon having one or more allotropic forms. The one or more allotropic forms of carbon include amorphous carbon, graphite, graphene, Buckminster-fullerenes such as but not limited to C20, C26, C28, C36, C50, C60, C70, C72, C76, C84, C540, carbon nanotubes, diamond and combinations thereof. The article further comprises an additional material including at least one of silicon oxide, silicon nitride, and mixtures thereof. At least some memory cells of the array are laterally spaced relative to each other, and wherein other memory cells of the array are vertically stacked on top of each other. Some of the memory cells of the array that are vertically stacked on top of each other share a bit line. Some of the memory cells of the array that are laterally spaced relative to each other share a word line. The plurality of word lines are substantially perpendicular to the plurality of bit lines. The geometric dimension comprises a thickness of the composite nanotube article between about 10 nm and about 200 nm. For each memory cell, the article is capable of switching among a plurality of electronic states is responsive to a corresponding plurality of electrical stimuli less than approximately 5V.
Under another aspect of the invention, a method of making a composite nanoscopic particle switch, includes providing a substrate having a first conductive terminal and depositing a layer of nanoscopic particles over the conductive terminal. The method includes depositing a second conductive terminal over the layer of nanoscopic particles, the layer having a thickness, density, and composition of nanoscopic particles selected to prevent direct physical and electrical contact between the first and second conductive terminals.
One or more embodiments include one or more of the following features. The layer of nanoscopic particles has a predefined composition comprises a first quantity of nanotubes and a second quantity of additional nanoscopic particles, a ratio between the first quantity and the second quantity being predefined. The ratio of the first quantity to the second quantity is predefined in accordance with the type of nanotubes, the type of nanotubes including one or more of single-walled, multi-walled, semiconducting, and metallic. The ratio of the first quantity to the second quantity is predefined in accordance with at least one attribute of the additional nanoscopic particles, the at least one attribute including one or more of physical dimensions, material type, and uniformity among particles. The ratio of the first quantity to the second quantity is predefined to tune the composite nanoscopic particle switch to have an electrically controllable resistance between the first and second conductive terminals. Depositing a composite layer of nanoscopic particles comprises a single deposition step and wherein the composite layer of nanoscopic particles is a substantially thick layer.
One or more embodiments include one or more of the following features. The layer of nanoscopic particles comprises a substantially thin layer of nanotubes. The first conductive terminal comprises a portion of a first conductive trace and the second conductive terminal comprises a portion of a second conductive trace. The first conductive trace and the second conductive trace are aligned in an orientation substantially perpendicular to one another. The method includes patterning the second conductive terminal and the layer of nanoscopic particles such that the second conductive terminal and the layer of nanoscopic particles each have a lateral dimension between about 200 nm and about 10 nm. The method includes patterning the second conductive terminal and the layer of nanoscopic particles such that the second conductive terminal and the layer of nanoscopic particles each have a lateral dimension of less than about 10 nm. Depositing the layer of nanoscopic particles comprises providing one or more layers of composite nanotube fabric having a cumulative thickness between about 10 nm and about 200 nm.
One or more embodiments include one or more of the following features. The method includes providing control circuitry to access said nanoscopic particle switch, the control circuitry including a diode in direct physical contact with one of the first and second conductive terminals. The method includes providing stimulus circuitry to apply electrical stimulus to at least one of the first and second conductive terminals, the electrical stimulus selected to induce a plurality of electronic states in the nanoscopic particle switch. The plurality of electronic states comprises a low resistance state and a high resistance state. The electrical stimulus selected to induce a plurality of electronic states in the nanoscopic particle switch comprises an electrical stimuli of less than approximately 5V. The diode comprises a layer of N+ polysilicon, a layer of N polysilicon, and a layer of conductor. The diode comprises a layer of N+ polysilicon, a layer of N polysilicon, and a layer of P polysilicon. The method providing control circuitry to access said nanoscopic particle switch, the control circuitry including a field effect transistor in direct physical contact with one of the first and second conductive terminals. The layer of nanoscopic particles comprises an electrically conductive, active material. The layer of nanoscopic particles comprises an electrically non-conductive, active material. The layer of nanoscopic particles comprises an electrically non-conductive, inert additional material. The layer of nanoscopic particles varies in resistance between electrically conductive and electrically non-conductive in response to plurality of electrical stimuli applied by the control circuitry to the first and second conductive terminals. The layer of nanoscopic particles comprises carbon having one or more allotropic forms. The one or more allotropic forms include amorphous carbon, graphite, graphene, Buckminster-fullerenes such as but not limited to C20, C26, C28, C36, C50, C60, C70, C72, C76, C84, C540, carbon nanotubes, diamond and combinations thereof. The layer of nanoscopic particles further comprises nanoscopic elements having at least one of silicon oxide, silicon nitride, and mixtures thereof. Depositing the layer of nanoscopic particles comprises providing an additional material and subsequently providing a plurality of carbon nanotubes in the additional material to form a matrix. Depositing the layer of nanoscopic particles comprises providing a plurality of carbon nanotubes and subsequently providing an additional material around the carbon nanotubes to form a matrix.
Under another aspect of the invention, a non-volatile composite nanotube switch includes a first conductive terminal and a composite article comprising a first plurality of nanotubes and a second plurality of nanoscopic particles, the first plurality and the second plurality selected according to a predefined ratio, at least a portion of the article in electrical contact with the first conductive terminal. The switch includes a second conductive terminal in contact with at least a portion of the article, wherein the article is physically and electrically interposed between the first and second conductive terminals and control circuitry in electrical communication with and capable of applying electrical stimulus to the first and second conductive terminals. The article is capable of switching among a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second conductive terminals. For each electronic state, the article provides an electrical pathway of corresponding resistance between the first and second conductive terminals.
One or more embodiments includes one or more of the following features. The predefined ratio is selected in accordance with at least one of the characteristics of the nanoscopic particles, the characteristics of the nanotubes characteristics of the plurality of electronic states, and the physical attributes of the composite article. The characteristics of the nanoscopic particles include at least one of uniformity among particles, material composition of particles, and physical dimensions of particles. The characteristics of the nanotubes include at least one of multi-walled characteristics, single-walled characteristics, semiconducting characteristics, and metallic characteristics. The characteristics of the plurality of electronic states includes at least one of a substantially low operating voltage, a substantially high resistance and a substantially low resistance. The physical attributes of the composite article includes a thickness of the composite article.
In the Drawing:
FIGS. 33B and 33B′ illustrate cross sectional views of two embodiments of stacked 3D memory array structures with a shared word line.
FIGS. 34A-34FF illustrate methods of fabrication for cathode-on-nanotube memory cross sectional structures with vertically oriented nonvolatile nanotube switches within vertical cell boundaries illustrated in
FIGS. 36A-36FF illustrate methods of fabrication for anode-on-nanotube memory cross sectional structures with vertically oriented nonvolatile nanotube switches within vertical cell boundaries illustrated in
FIGS. 48A-48BB illustrate a method of fabrication of the structure in
Embodiments of the present invention provide nonvolatile diodes and nonvolatile nanotube blocks and systems using same and methods of making same.
Some embodiments of the present invention provide 3-D cell structures that enable dense nonvolatile memory arrays that include nanotube switches and diodes, can write logic 1 and 0 states for multiple cycles, and are integrated on a single semiconductor (or other) substrate. It should be noted that such nonvolatile memory arrays may also be conFigured as NAND and NOR arrays in PLA, FPGA, and PLD configurations for performing stand-alone and embedded logic functions as well.
Some embodiments of the present invention provide diode devices having nonvolatile behavior as a result of diodes combined with nonvolatile nanotube components, and methods of forming such devices.
Some embodiments of the present invention also provide nanotube-based nonvolatile random access memories that include nonvolatile nanotube diode device cells having a relatively high density, and methods of forming such memory devices.
Some embodiments of the invention provide nonvolatile devices that combine nonvolatile nanotube switches (NV NT Switches), such as those described in U.S. patent application Ser. No. 11/280,786, with diodes in a nonvolatile nanotube diode (NV NT Diode) device. Suitable diodes include Schottky, PN, PIN, PDB (planar-doped-barrier), Esaki, LED (light emitting), laser and other diodes and FET diodes. Combinations of NV NT switches with PDB and Esaki diodes may be used in fast switching applications, while combinations of NV NT switches and LED and Laser diodes may be used in light (photon) sources for communications and display applications, as well as photon-based logic and memory applications. Nonvolatile nanotube diodes (NV NT Diodes) formed using various diode and NV NT Switch combinations, such as cathode-to-nanotube and anode-to-nanotube interconnections, are described. NV NT Diode operation is also described. Devices fabricated using NV NT Diodes are also described.
While in some embodiments, NV NT diodes are formed by combining NV NT switches and various diodes formed using silicon and metallurgies typical of CMOS processes, a wide variety of semiconductor materials and conductors may be used to form a variety of diodes in combination with a wide variety of conductors. Examples of semiconductor materials are Si, Ge, SiC, GaP, GaAs, GaSb, InP, InAs, InSb, ZnS, ZnSe, CdS, CdSe, CdTe for example. Schottky diodes may be formed by combining various semiconductor material with compatible conductors such as Al, Ag, Au, Au/Ti, Bi, Ca, Co, CoSi2, Cr, Cu, Fe, In, Ir, Mg, Mo, MoSi2, Na, Ni, NiSi2, Os, Pb, Pd, Pd2Si, Pt, PtSi, Rh, RhSi, Ru, Sb, Sn, Ti, TiSi2, W, WSi2, Zn, ZrSi2, and others for example. LED and laser diodes may be formed using such semiconductor material as GaInAsPt, GaAsSb, InAsP, InGaAs, and many other combinations of materials that determine light emission wavelength.
Alternatively, FET diodes may be formed by combining a NV NT Switch and a three terminal FET with gate electrically connected to one of the two diffusion terminals to form a two terminal FET diode device. When combining a NV NT Switch and an FET diode, a nonvolatile nanotube diode may also be referred to as a nonvolatile nanotube FET-diode, abbreviated as NV NT FET-Diode, to highlight this difference with respect to Schottky, PN, PIN, and other diodes. However, differences between combinations of NV NT Switches and FET diodes and Schottky, PN, PIN and other diodes may not be highlighted and all may be referred to a NV NT Diode.
Embodiments of 2-D nonvolatile memories, both stand-alone and embedded in logic (processors for example), that use nonvolatile nanotube diodes (NV NT Diodes) as storage elements, are also described. These NV NT Diodes may be formed in and/or on a semiconductor substrate with memory support circuits and logic function and integrated on a single substrate such as a semiconductor chip or wafer to form 2-D memory and 2-D memory and logic functions.
Embodiments of 3-D architectures of nonvolatile memories, both stand-alone and embedded in logic, that use NV NT Diodes as 3-D cells for 3-D memory arrays that can write logic 1 and 0 states for multiple cycles, are also described. It should be noted that some embodiments of 3-D memories using arrays of NV NT diode cells are described with respect to memory arrays that are not fabricated in or on a semiconductor substrate, but are instead formed on an insulating layer above support circuits formed in and on a semiconductor substrate with interconnections between support circuits and the 3-D memory array.
NV NT Diode arrays can also be formed on a planar insulating surface, above support circuits with array interconnections through and on the insulating layer, in which the NV NT Diode arrays are formed using methods of fabrication in which array features are self-aligned in both X and Y directions such that array features are not increased in size to accommodate alignment requirements.
It should also be noted that presently available planarization techniques (chemical-mechanical planarization (CMP), for example) combined with Silicon-on-Insulator (SOI) technology and thin film transistor (TFT) technology enable 3-D memory arrays using NV NT Diodes as 3-D cells to be fabricated in planar dense stacked structures above a single substrate in which the substrate is not a semiconductor substrate. Combined planarization techniques and display-application-driven enhanced TFT technology enable non-semiconductor substrates such as glass, ceramic, or organic substrate as alternatives to using semiconductor substrates.
Methods of fabrication of various 3-D memories are described.
Although NV NT Diode-based nonvolatile memories are described, it should be noted that such nonvolatile memory arrays may also be conFigured as NAND and NOR arrays in PLA, FPGA, and PLD functions for performing stand-alone and embedded logic as well.
Two Terminal Nonvolatile Nanotube Diode Devices
Some embodiments provide a nonvolatile nanotube diode device that acts like a diode in its ability to direct electronic communication in a forward biased direction, and prevent communication in a reverse direction, if the nanotube diode is in a conductive (ON) mode (or state). However, if a nonvolatile nanotube diode device is in a nonconductive (OFF) mode (or state), then direct communication is prevented in either forward or reverse direction. The nonvolatile nanotube diode device conductive (ON) mode or nonconductive (OFF) mode is nonvolatile and is maintained without power supplied to the device. The mode of the nonvolatile nanotube diode device may be changed from ON to OFF or from OFF to ON by applying suitable voltage and current levels using a stimulus circuit.
Some embodiments of the nonvolatile device are formed by combining nonvolatile nanotube switches (NV NT Switches) described in U.S. patent application Ser. No. 11/280,786, U.S. patent application Ser. No. 11/835,612, entitled “Nonvolatile Resistive Memories Having Scalable Two-Terminal Nanotube Switches,” filed on even date herewith, and/or U.S. patent application Ser. No. 11/835,613, entitled “Memory Elements and Cross Point Switches and Arrays of Same Using Nonvolatile Nanotube Blocks,” filed on even date herewith, and diodes such as Schottky, PN, PIN, and other diodes and FET diodes to form a nonvolatile nanotube diode (NV NT Diode) device. In some embodiments, nonvolatile nanotube diodes (NV NT Diodes) are two terminal devices having one terminal in contact with one terminal of a nonvolatile nanotube switch and another terminal in contact with the anode or cathode of a diode. In some embodiments, a shared internal contact connects a second terminal of a nonvolatile nanotube switch with the cathode or anode of a diode to form the nonvolatile nanotube diode device.
Some embodiments of NV NT diodes are scalable to large nonvolatile array structures. Some embodiments use processes that are compatible with CMOS circuit manufacture. It should be noted that based on the principle of duality in semiconductor devices, P and N regions in the examples illustrated may be interchanged with corresponding changes in the polarity of applied voltages.
Nonvolatile Nanotube Diode Devices having the Cathode of the Diode Connected to one Terminal of the Nonvolatile Nanotube Switch; and other Nonvolatile Nanotube Diode Devices having the Anode of the Diode Connected to one Terminal of the Nonvolatile Nanotube Switch
Nonvolatile nanotube switches (NV NT Switches) are described in detail in U.S. patent application Ser. No. 11/280,786, and are summarized briefly below. NV NT Switches include a patterned nanotube element and two terminals in contact with the patterned nanotube (nanofabric) element. Methods of forming nanotube fabrics and elements, and characteristics thereof, are described in greater detail in the incorporated patent references. Nonvolatile nanotube switch operation does not depend on voltage polarity, positive or negative voltages may be used. A first terminal may be at a higher or lower voltage with respect to a second terminal. There is no preferential current flow direction. Current may flow from a first to a second terminal or from a second to a first terminal.
In some embodiments, NV NT Switch 500 may be modified (not shown) to include a gap region in insulator 535 between a portion of nanotube element 530 and insulator 540 as described further in U.S. patent application Ser. No. (TBA), entitled “Nonvolatile Resistive Memories Having Scalable Two-Terminal Nanotube Switches,” and/or U.S. patent application Ser. No. (TBA), entitled “Memory Elements and Cross Point Switches and Arrays of Same Using Nonvolatile Nanotube Blocks,” filed on even date herewith. Without wishing to be bound by theory, it is believed that in the suspended region a reduced amount of heat is lost to the surrounding substrate, so smaller values of voltage and current may be required to heat the nanotubes to a temperature sufficient for switching to occur. Other mechanisms are possible.
Nonvolatile nanotube switch embodiment 600 illustrated in
Laboratory testing results of individual fabricated nonvolatile nanotube switches, represented schematically by nonvolatile nanotube switch 800 illustrated in
Nonvolatile nanotube switches may be fabricated to exhibit a wide range of ON Resistance values depending on switch channel length, and the number of individual nanotubes in the patterned nanotube (channel) element. Nonvolatile nanotube switches may exhibit ON Resistances in the 1 kOhm to 10 MOhm range, while OFF resistance is typically 100 MOhm or 1 GOhm or greater
Nonvolatile nanotube diode devices are a series combination of a two terminal semiconductor diodes and two terminal nonvolatile nanotube switches similar to nonvolatile nanotube switches described further above with respect to
NV NT Diode embodiments described further below typically use Schottky diodes, PN diodes and FET-diodes. However, other diode types such as PIN diodes may be combined with nonvolatile nanotube switches to form nonvolatile nanotube PIN-diodes that may enable or disable RF switching, attenuation and modulation, signal limiting, phase shifting, power rectification, and photodetection for example. Also, nonvolatile LED diodes may be combined with nonvolatile switches to form nonvolatile nanotube LED-diodes that enable or disable LED diodes and provide light output patterns stored as nonvolatile states in a nonvolatile nanotube LED-diode.
Schottky diodes typically have low forward-voltage drops, which is an advantage, and good high frequency characteristics. These characteristic plus ease of fabrication make Schottky diodes useful in a wide range of applications. A critical step in the fabrication is to prepare a clean surface for intimate contact of the metal to the semiconductor surface. Metal-on-silicon or metal silicides-on-silicon may also be used. Schottky diodes 142 illustrated in
Operation of Nonvolatile Nanotube Diode Devices
In an exemplary write 0 (erase) operation, referring to circuit 1800 in
An exemplary write 0 operation 2000-1 during a mode setting time interval such as illustrated in
In an exemplary write 1 (program) operation, referring to circuit 1800 in
An exemplary write 1 operation 2000-2 during a mode setting time interval such as illustrated in
In an exemplary write 0 operation, referring to circuit 1900 in
An exemplary write 0 operation 2000-3 during a mode setting time interval such as illustrated in
In an exemplary write 1 operation, referring to circuit 1900 in
An exemplary write 1 operation 2000-4 during a mode setting time interval such as illustrated in
One alternative to using a stimulus circuit with current limiting is to design FET diode 1505 to limit current. That is, NV NT Diode 1500 has a built-in current limit determined by the design of sub-component FET Diode 1505. FET diode examples are shown in the reference Baker, R. et al., “CMOS Circuit Design, Layout, and Simulation”, IEEE Press, 1998, pp. 165-171.
In an exemplary read operation, referring to circuit 2100 in
In an exemplary read operation in which NV NT Diode 1200 is in an OFF state, the OFF resistance of NV NT Diode 1200 is much greater than resistance R and when applying read voltage waveforms 2200-1 illustrated in
In an exemplary read operation in which NV NT Diode 1200 is in an ON state, the ON resistance of NV NT Diode 1200 is much less than resistance R and when applying read voltage waveforms 2200-2 illustrated in
In a read operation, referring to circuit 2300 in
In an exemplary read operation in which NV NT Diode 1500 is in an OFF state, the OFF resistance of NV NT Diode 1500 is much greater than resistance R and when applying read voltage waveforms 2300-1 illustrated in
In an exemplary read operation in which NV NT Diode 1500 is in an ON state, the ON resistance of NV NT Diode 1500 is much less than resistance R and when applying read voltage waveforms 2300-2 illustrated in
In an exemplary signal transfer operation, referring to circuit 2400 in
In an exemplary signal transfer operation in which NV NT Diode 1200 is in an OFF state, the OFF resistance of NV NT Diode 1200 is much greater than resistance R and applying signal transfer voltage waveforms 2500-1 illustrated in
In an exemplary signal transfer operation in which NV NT Diode 1200 is in an ON state, the ON resistance of NV NT Diode 1200 is much less than resistance R and applying read voltage waveforms 2500-2 illustrated in
Nonvolatile Memories using Nonvolatile Nanotube Diode (NV NT Diode) Devices as Cells
A bit-selectable nonvolatile nanotube-based memory array described further below includes a plurality of memory cells, each cell receiving a bit line and a word line. Each memory cell includes a selection diode with anode and cathode terminals (nodes). Each cell further includes a two terminal nonvolatile nanotube switch device, the state of which manifests the logical state of the cell. The combined diode and nonvolatile nanotube switch is referred to as a nonvolatile nanotube diode (NT Diode) as described further above. Each memory cell is formed using one nonvolatile nanotube diode. The state of the nonvolatile nanotube switch-portion of the nonvolatile nanotube diode may be changed (cycled) between an ON resistance state and an OFF resistance state separated by at least one order of magnitude, but typically separated by two to five orders of magnitude. There is no practical limit to the number of times nonvolatile nanotube switches may be cycled between ON and OFF states.
Each memory cell may be formed using a nonvolatile nanotube diode with an internal cathode-to-nonvolatile nanotube switch connection, or a nonvolatile nanotube diode with an internal anode-to-nonvolatile nanotube switch connection, with a horizontal orientation, or with a vertical (three dimensional) orientation to maximize density. In order to further maximize density, memory arrays are integrated above support circuits and interconnections that are integrated in and on an underlying semiconductor substrate.
Nonvolatile Memories using NV NT Diode Devices with Cathode-to-NT Switch Connection
In some embodiments, a nonvolatile nanotube diode (NV NT diode) is a two terminal nonvolatile device formed by two series devices, a diode (e.g., a two terminal Schottky or PN diode) in series with a two terminal nonvolatile nanotube switch (NV NT switch). Each of the two said series devices has one shared series electrical connection. A cathode-to-nanotube NV NT diode has the cathode terminal electrically connected to one of said two nonvolatile nanotube switch terminals. Said NV NT diode two terminal nonvolatile device has one available terminal connected to the anode of the Schottky or PN diode and the second available terminal connected to the free terminal of the NV NT switch. A schematic of an embodiment of a cathode-to-NT nonvolatile nanotube diode is illustrated in
In some embodiments, dense 3D memories may be formed using one NV NT diode per cell. Embodiments of memories using NV NT diodes with cathode-to-NT connections are illustrated schematically and memory operation is described further below. 3-D cell structures are illustrated including fabrication methods. Cells with NV NT diodes formed with NV NT switches with both vertical and horizontal orientations are illustrated further below.
Nonvolatile Systems and Circuits, with Same
One embodiment of a nonvolatile memory 2600 is illustrated in
Nonvolatile memory 2600 illustrated in
In the illustrated embodiment, memory array 2610 is a 4-word line by 4-bit line 16 bit memory array that includes word lines WL0, WL1, WL2, and WL3 and bit lines BL0, BL1, BL2, and BL3. Word line driver circuits 2630 connected to word lines WL0 through WL3 and selected by word decoder and WL select logic 2620 provide stimulus during write 0, write 1, and read operations. BL driver and sense circuits 2640 provide data multiplexers (MUXs), BL drivers and sense amplifier/latches and are connected to bit lines BL0 through BL3 and selected by bit decoder and BL select logic 2650 provide stimulus during write 0, write 1, and read operation; that is receive data from memory array 2610 and transmit data to memory array 2610. Data in memory array 2610 is stored in a nonvolatile state such that power (voltage) supply to memory 2600 may be removed without loss of data. BL driver and sense circuits 2640 are also connected to read/write buffer 2660. Read/write buffer 2660 transmits data from memory array 2610 to read/write buffer 2660 which in turn transmits this data off-chip. Read/write buffer 2660 also accepts data from off-chip and transmits this data to BL driver and sense circuits 2640 that in turn transmit data to array 2610 for nonvolatile storage. Address buffer 2670 provides address location information.
For an exemplary write 0 operation along word line WL0, simultaneously erasing cells C00, C01, C02, and C03, data stored in cells C00-C03 may optionally be read prior to erase and data stored in corresponding sense amplifier/latches. Write 0 operations along word line WL0 proceeds with bit lines BL0, BL1, BL2, and B3 transitioning from zero to 5 volts, with bit line drivers controlled by corresponding BL drivers in BL driver and sense circuits 2640. Next, WL driver circuits 2630 drive word line WL0 from 5 volts to zero volts thus forward biasing NV NT Diodes C00, C01, C02, and C03 that form cells C00, C01, C02, and C03, respectively. A write 0 voltage of approximately 4.5 volts (erase voltage 5 volts minus NV NT diode turn on voltage of less than 0.5 volts as illustrated in
Note that while
The exemplary write 0 and write 1 operations illustrated in
In this example, an exemplary write operation is preceded by a write 0 operation as described further above. In other words, NV NT Diodes C00-C03 of respective corresponding cells C00-C03 begin the write operation in the OFF state. For an exemplary write 0 operation to cell C00 for example, in which a logic 0 state is to be stored, NV NT Diode C00 is to remain in the logic 0 high resistance state. Therefore, bit line BL0 is held at zero volts by corresponding BL driver and sense circuits 2640. Next, word line WL0 transitions from 4 volts to zero volts, with stimulus from WL drivers 2630. NV NT Diode C00 remains back biased during the write 0 operation and cell C00 remains in an OFF (high resistance) logic 0 state.
If NV NT Diode C00 is to transition from an OFF (high resistance state) to an ON (low resistance state) in a write 1 operation representing a logic 1, then bit line BL0 transitions from zero volts to 4 volts, with stimulus provided by corresponding BL drivers in BL driver and sense circuits 2640. Next, word line WL0 transitions from 4 volts to zero volts. A write 1 voltage of approximately 4 volts results in a voltage of 3.5 volts across the terminals of a corresponding NV NT switch sub-component of NV NT diode C00 (4 volts minus NV NT diode turn on voltage of less than 0.5 volts as illustrated in
For an exemplary read operation, from cells C00-C03 for example, the bit line drivers in BL driver and sense circuits 2640 precharge bit lines BL0-BL3 to a high voltage such as a read voltage of 2 volts, for example. The read bit line voltage is selected to be less than both write 0 and write 1 voltages to ensure that stored logic states (bits) are not disturbed (changed) during a read operation. Word line driver circuits 2630 drives word line WL0 from 2 volts to zero volts. If NV NT Diode C00 in cell C00 is in an OFF state (storing a logic 0) then bit lines BL0 is not discharged and remains at 2 volts. A corresponding sense amplifier/latch in BL driver and sense circuits 2640 stores a logic 0. However, if NV NT Diode C00 in cell C00 is in an ON state, then bit line BL0 is discharged. A corresponding sense amplifier/latch in BL driver and sense circuits 2640 detects the reduced voltage and latches a logic 1.
In this example, a write operation is preceded by a write 0 operation as described further above with respect to
Therefore, at the beginning of the write cycle, bit lines BL0 and BL3 remain at zero volts. Next, word line WL0 transitions from 4 volts to zero volts. NV NT Diodes C00 and C03 remain back biased during the write 0 operation, and therefore NV NT Diodes remain in the OFF state storing a logic 0 state.
Continuing the exemplary write cycle, cells C01 and C02 transition from an OFF to an ON state. Bit lines BL1 and BL2 transition from zero to 4 volts. Next, word line WL0 transitions from 4 volts to zero volts. NV NT Diodes C01 and C02 are forward biased during the write 1 operation and approximately 3.5 volts appear across NV NT Switches corresponding to NV NT Diodes C01 and C02. NV NT Diodes C01 and C02 transition from an OFF to an ON state storing a logic 1 state.
For an exemplary read operation as illustrated by waveforms 2600′ in
An Overview of 3-Dimensional Cell Structure Methods of Fabrication of Nonvolatile Memory Cells using NV NT Devices
Nonvolatile nanotube diodes 1200 and 1300 (NV NT Diodes 1200, 1300), and nonvolatile nanotube diodes formed with FET diodes, referred to as NV NT Diodes 1400, 1500, 1600, and 1700 or also as NV NT FET-Diodes 1400, 1500, 1600, and 1700, may be used as cells and interconnected into arrays to form nonvolatile nanotube random access memory systems. Such arrays may also be used to fabricate nonvolatile array-based logic such as PLAs, FPGAs, PLDs and other such logic devices.
In general, methods 2710 fabricate support circuits and interconnections in and on a semiconductor substrate. This includes NFET and PFET devices having drain, source, and gate that are interconnected to form memory support circuits such as, for example, circuits 2620, 2630, 2640, 2650, 2660, and 2670 illustrated in
Methods 2720 depicted in
Word lines and bit lines can be used in 3D array structures as described further below to interconnect 3-D cells and form 3-D memories, and can be approximately orthogonal in an X-Y plane approximately parallel to underlying memory support circuits. Word line direction has been arbitrarily assigned as along the X axis and bit line direction has arbitrarily assigned as along the Y axis in Figures illustrating 3D array structures and 3D array structure methods of fabrication as described further below. The Z axis, approximately orthogonal to the X-Y plane, indicates the vertical direction of 3D cell orientation, in “vertical cell” embodiments such as those described in greater detail below.
Methods 2750 use industry standard fabrication techniques to complete fabrication of the semiconductor chip by adding additional wiring layers as needed, and passivating the chip and adding package interconnect means.
3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Vertically Oriented NT Switches with Cathode-to-NT Switch Connection
Once support circuits and interconnections in and on the semiconductor substrate are defined, methods can then be used to fabricate a nonvolatile nanotube diode array such as that illustrated in cross section 2800 above the support circuit and interconnect region as illustrated in
Methods 2710 described further above can be used to define support circuits and interconnections 2801.
Next, methods 2730 illustrated in
Methods 2740 illustrated in
Vertically oriented nanotube element placement R at approximately F/2 assumes nanotube film thickness that is much less than cell dimension F. For a 45 nm technology node, for example, a nanotube element in the thickness range of 0.5 nm to 10 nm, for example. Nanotube elements may be formed using a single nanotube layer, or may be formed using multiple layers. Such nanotube element layers may be deposited e.g., using spin-on coating techniques or spray-on coating techniques, as described in greater detail in the incorporated patent references.
In one possible variation, vertically oriented nanotube elements thickness may be too thick for placement at F/2 for cells with dimension F. For example, for a cell dimension F of 35 nm, for example, and a nanotube film thickness of 10-20 nm, placement of vertically oriented nanotube elements may be at F/3 for example, to accommodate both the nanotube element and a protective insulator as illustrated further below with respect to
In another possible variation, a nanotube element thickness may be equal to the overall cell dimension F. For example, for a cell dimension F of 35 nm, a nanotube film thickness of 35 nm may be used. Or, for example, for a cell dimension F of 22 nm, a nanotube film thickness of 22 nm may be used. In this case the nanotube element contact structure may be modified such that the sidewall contact is eliminated and replaced by lower and upper contacts only as illustrated further below in
In addition to the simultaneous definition of overall cell dimensions without multiple alignment steps, minimized memory cell size (area) also requires the self-aligned placement of device elements within said memory cell boundaries using sub-minimum dimensions, in this example, cell boundaries defined by isolation trenches. Cross sections 2800 and 2800′ in
In some embodiments, methods fill trenches with an insulator and then planarize the surface. Then, methods deposit and pattern word lines on the planarized surface.
The fabrication of vertically-oriented 3D cells proceeds as follows, in some embodiments. Referring to
Alternatively, more optimum Schottky diode junctions 2818-1 and 2818-2 may be formed using metal or silicide contacts 2815-1 and 2815-2 in contact with N polysilicon regions 2820-1 and 2820-2, while also forming ohmic contacts with bit lines 2810-1 and 2810-2 as described further below with respect to FIGS. 34A-34FF. N polysilicon regions 2820-1 and 2820-2 may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3 for example, and may have a thickness range of 20 nm to 400 nm, for example. Contacts 2815-1 and 2815-2 may be in the thickness range of 10 nm to 500 nm, for example.
In some embodiments, the electrical characteristics of Schottky (and PN) diodes may be improved (low leakage, for example) by controlling the material properties of polysilicon, for example polysilicon deposited and patterned to form polysilicon regions 2820-1 and 2820-2. Polysilicon regions may have relatively large or relatively small grain boundary size that are determined by methods used in the semiconductor regions. SOI deposition methods used in the semiconductor industry may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline, for further electrical property enhancement such as low diode leakage currents.
Examples of contact and conductors materials are elemental metals such as, Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix. Insulators may be SiO2, SiNx, Al2O3, BeO, polyimide, Mylar or other suitable insulating material.
In some cases conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as both contact and conductors materials as well as anodes for Schottky Diodes, in which case separate optional Schottky anodes contacts such as 2815-1 and 2815-2 are not required and may be omitted. However, in other cases, optimizing anode material for lower forward voltage drop and lower diode leakage is advantageous. Schottky diode anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn and other elemental metals. Also, silicides such as CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2, and ZrSi2 may be used. Schottky diodes formed using such metals and silicides are illustrated in the reference by NG, K. K. “Complete Guide to Semiconductor Devices”, Second Edition, John Wiley and Sons, 2002m pp. 31-41, the entire contents of which are incorporated herein by reference.
Next, having completed Schottky diode select devices, methods form N+ polysilicon regions 2825-1 and 2825-2 to contact N polysilicon regions 2820-1 and 2820-2, respectively, and also to form contact regions for ohmic contacts to contacts 2830-1 and 2830-2. N+ polysilicon is typically doped with arsenic or phosphorous to 1020 dopant atoms/cm3, for example, and has a thickness of 20 to 400 nm, for example.
Next, methods form a nonvolatile nanotube switch in each cell having one terminal common with cathode contacts 2830-1 and 2830-2 for example. In order to enhance the density of cells C00 and C01, the nanotube elements illustrated in
Methods of forming nanotube elements 2845-1 and 2845-2 can include first forming insulators 2835-1 and 2835-2 and sidewall contacts 2840-1 and 2840-2, in contact with corresponding insulators 2835-1 and 2835-2, by directionally etching an opening through both metal and insulator regions to form vertical sidewalls. The thickness of insulators 2835-1 and 2835-2 determine the nanotube element channel length as illustrated in
Next, methods form conformal nanotube elements 2845-1 and 2845-2 as described in greater detail in the incorporated patent references.
Then, methods form protective conformal insulator 2850-1 and 2850-2 on the surface of conformal nanotube elements 2845-1 and 2845-2, respectively.
Next, methods form an opening having an X dimension of approximately F and methods fill that opening with a conductor material forming upper level contacts 2865-1 and 2865-2 in contact with sidewall contacts 2840-1 and 2840-2, respectively. Methods to form upper level contacts 2865-1 and 2865-2 may be similar to methods disclosed in U.S. Pat. No. 4,944,836 and described further below with respect to FIGS. 34A-34FF.
Contacts 2865-1 and 2865-2 provide a conductive path between sidewall contacts 2840-1 and 2840-2, respectively, and word line 2871 (WL0) to be formed after completing the formation of cells C00 and C01.
Next, prior to the formation of word line 2871 (WL0), cell C00 and cell C01 dimensions can be defined by a trench etch through all layers in cell structure 2800, down to the top surface of insulator 2803.
Next, methods fill trench regions with an insulator 2860 and planarize the structure just prior to word line 2871 (WL0) deposition.
Then, methods deposit and pattern word line 2871 (WL0).
Nonvolatile nanotube diode 2880 schematic superimposed on cross section 2800 in
Cross sectional view 2800′ illustrated in
P polysilicon regions 2817-1 and 2817-2 form a diode-anode and N polysilicon regions 2820-10′ and 2820-20′ form a diode cathode that together (combined) form PN diodes with PN diode junctions 2819-1 and 2819-2. P polysilicon regions 2817-1 and 2817-2 also form ohmic or near-ohmic contacts with bit lines 2810-1′ (BL0) and 2810-2′ (BL1), respectively. N polysilicon regions 2820-1′ and 2820-2′ also form ohmic contact regions with N+ polysilicon regions 2825-1 and 2825-2. Other structures of cells C00′ and C01′ are similar to those illustrated and described with respect to cells C00 and C01, respectively.
Memory array support structure 2805-2 illustrated in
3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Horizontally Oriented NT Switches with Cathode-to-NT Switch Connection
Methods 2720 illustrated in
Cell C00″ in the embodiment of
Individual outer cell dimensions can be formed in a single etch step, each cell having a single NV NT Diode defined by a single trench etch step after layers, except the WL0 layer, have been deposited and planarized, in order to eliminate accumulation of individual layer alignment tolerances that may substantially increase cell area. Individual cell dimensions in the X direction are 2-3F (1F is minimum feature) as illustrated in
Cross section 2800″ illustrated in
In
Methods can be used fabricate a nonvolatile nanotube switch having a horizontal (instead of a vertical) orientation and having one side of the nonvolatile nanotube switch in electrical (not physical) contact with N+ polysilicon region 2825″ and the other side of the nonvolatile nanotube switch in electrical (not physical) contact with word line 2875.
First, methods deposit insulator 2830″ and contact 2835″. Then methods form an opening through both contact 2835″ and insulator 2830″ to expose the surface of N+ polysilicon region 2825″.
Next, methods deposit a conformal insulating layer on the top, sidewall, and bottom of the underlying opening. Then, methods directional etch the conformal insulating layer thereby forming sidewall spacer 2840, whose thickness determines the channel length LSW-CH of the nonvolatile nanotube switch in cell C00″. Cross section 2800″ shows two LSW-CH regions. These two LSW-CH regions are electrically in parallel (not shown by cross section 2800″). Exemplary methods of fabrication are described further below with respect to
Next, methods fill the opening with contact metal, followed by planarization, to form contact 2845, which forms an Ohmic contact to N+ polysilicon region 2825″ and is isolated from contact 2835″ regions by sidewall spacer 2840.
Next, methods deposit nanotube element 2850 on and in physical and electrical contact with contact 2845, spacers 2840, and sidewall contact 2835″. The separation between contact 2845 and contact 2835″, which is formed by the thickness of sidewall spacer 2840, determines the nonvolatile nanotube switch channel length LSW-CH. Nanotube element 2850 may optionally be patterned as illustrated in
Next, methods deposit insulator 2855.
Next, methods etch insulator 2855 forming an opening. Then, methods etch (remove) the exposed portion of nanotube element 2850, e.g., as described in greater detail in the incorporated patent references.
Next, the opening is filled with contact metal 2865. Methods form contact metal 2865 by metal deposition followed by planarization. Contact 2865 physically and electrically contacts both contact 2835″ and nanotube element 2850.
Next, methods etch a trench through all layers, stopping on the surface of insulator 2803″, thereby defining the dimensions of cell C00″.
Next, methods deposit and planarize an insulating layer forming insulator 2874.
Then, methods deposit and pattern word line 2875 (WL0) completing cell C00″. Exemplary methods of fabrication are described further below with respect to
Nonvolatile nanotube diode embodiment 2885 in
Nonvolatile Memories using NV NT Diode Devices with Anode-to-NT Switch Connection
In some embodiments, a nonvolatile nanotube diode (NV NT diode) is a two terminal nonvolatile device formed by two series devices, a diode (e.g., a two terminal Schottky or PN diode) in series with a two terminal nonvolatile nanotube switch (NV NT switch). Each of the two said series devices has one shared series electrical connection. An anode-to-nanotube NV NT diode has the anode terminal electrically connected to one of said two nonvolatile nanotube switch terminals. Said NV NT diode two terminal nonvolatile device has one available terminal connected to the cathode of the Schottky or PN diode and the second available terminal connected to the free terminal of the NV NT switch. A schematic of an anode-to-NT nonvolatile nanotube diode is illustrated in
In some embodiments, dense 3D memories may be formed using one NV NT diode per cell. Embodiments of memories using NV NT diodes with anode-to-NT connections are illustrated schematically and memory operation is described further below. Exemplary 3-D cell structures are illustrated including fabrication methods. Exemplary cells with NV NT diodes formed with NV NT switches with vertically orientated switches are illustrated further below.
Nonvolatile Systems and Circuits, with Same
One embodiment of a nonvolatile memory 2900 is illustrated in
Nonvolatile memory 2900 illustrated in
In the illustrated embodiment, memory array 2910 is a 4-word line by 4-bit line 16 bit memory array that includes word lines WL0, WL1, WL2, and WL3 and bit lines BL0, BL1, BL2, and BL3. Word line driver circuits 2930 connected to word lines WL0 through WL3 and selected by word decoder and WL select logic 2920 provide stimulus during write 0, write 1, and read operations. BL driver and sense circuits 2940 that provide data MUXs, BL drivers and sense amplifier/latches are connected to bit lines BL0 through BL3 and selected by bit decoder and BL select logic 2950 provide stimulus during write 0, write 1, and read operation; that is receive data from memory array 2910 and transmit data to memory array 2910. Data in memory array 2910 is stored in a nonvolatile state such that power (voltage) supply to memory 2900 may be removed without loss of data. BL driver and sense circuits 2940 are also connected to read/write buffer 2960. Read/write buffer 2960 transmits data from memory array 2910 to read/write buffer 2960 which in turn transmits this data off-chip. Read/write buffer 2960 also accepts data from off-chip and transmits this data to BL driver and sense circuits 2940 that in turn transmit data to array 2910 for nonvolatile storage. Address buffer 2970 provides address location information.
Note that while
For an exemplary write 0 operation along word line WL0, simultaneously erasing cells C00, C01, C02, and C03, data stored in cells C00-C03 may optionally be read prior to erase and data stored in corresponding sense amplifier/latches. Write 0 operation along word line WL0 proceeds with bit lines BL0, BL1, BL2, and B3 transitioning from zero to 5 volts, with bit line drivers controlled by corresponding BL drivers in BL driver and sense circuits 2940. Next, WL driver circuits 2930 drive word line WL0 from 5 volts to zero volts thus forward biasing NV NT Diodes C00, C01, C02, and C03 that form cells C00, C01, C02, and C03, respectively. A write 0 voltage of approximately 4.5 volts (write 0 voltage 5 volts minus NV NT diode turn on voltage of less than 0.5 volts) results in a transition from an ON state to an OFF state for NV NT Diodes in an ON state; NV NT Diodes in an OFF state remain in an OFF state. Thus after a write 0 operation along word line WL0, NV NT Diodes C00-C03 are all in an OFF state. Unselected word lines WL1, WL2, and WL3 all remain unselected and at 5 volts, and nonvolatile data stored in corresponding cells remains unchanged.
In this example, a write operation is preceded by a write 0 operation as described further above. In other words, NV NT Diodes C00-C03 of respective corresponding cells C00-C03 begin the write operation in the OFF state. For an exemplary write 0 operation to cell C00 for example, in which a logic 0 state is to be stored, NV NT Diode C00 is to remain in the logic 0 high resistance state. Therefore, bit line BL0 is held at zero volts by corresponding BL driver and sense circuits 2940. Next, word line WL0 transitions from 4 volts to zero volts, with stimulus from WL drivers 2930. NV NT Diode C00 remains back biased during the write 0 operation and cell C00 remains in an OFF (high resistance) logic 0 state.
If NV NT Diode C00 is to transition from an OFF (high resistance state) to an ON (low resistance state) in a write 1 operation representing a logic 1, then bit line BL0 transitions from zero volts to 4 volts, with stimulus provided by corresponding BL drivers in BL driver and sense circuits 2940. Next, word line WL0 transitions from 4 volts to zero volts. A write 1 voltage of approximately 4 volts results in a voltage of 3.5 volts across the terminals of a corresponding NV NT switch sub-component of NV NT diode C00 (4 volts minus NV NT diode turn on voltage of less than 0.5 volts) results in a transition from an OFF state to an ON state for NV NT Diode C00.
For an exemplary read operation, from cells C00-C03 for example, the bit line drivers in BL driver and sense circuits 2940 precharge bit lines BL0-BL3 to a high voltage such as a read voltage of 2 volts, for example. The read bit line voltage is selected to be less than both write 0 and write 1 voltages to ensure that stored logic states (bits) are not disturbed (changed) during a read operation. Word line driver circuits 2930 drives word line WL0 from 2 volts to zero volts. If NV NT Diode C00 in cell C00 is in an OFF state (storing a logic 0), then bit lines BL0 is not discharged and remains at 2 volts. A corresponding sense amplifier/latch in BL driver and sense circuits 2940 stores a logic 0. However, if NV NT Diode C00 in cell C00 is in an ON state, then bit line BL0 is discharged. A corresponding sense amplifier/latch in BL driver and sense circuits 2940 detects the reduced voltage and latches a logic 1.
In this example, a write operation is preceded by a write 0 operation as described further above with respect to
Therefore, at the beginning of the write (program) cycle, bit lines BL0 and BL3 remain at zero volts. Next, word line WL0 transitions from 4 volts to zero volts. NV NT Diodes COO and C03 remain back biased during the write 0 operation, and therefore NV NT Diodes remain in the OFF state storing a logic 0 state.
Continuing the exemplary write cycle, cells C01 and C02 transition from an OFF to an ON state. Bit lines BL1 and BL2 transition from zero to 4 volts. Next, word line WL0 transitions from 4 volts to zero volts. NV NT Diodes C01 and C02 are forward biased during the write 1 operation and approximately 3.5 volts appear across NV NT Switches corresponding to NV NT Diodes C01 and C02. NV NT Diodes C01 and C02 transition from an OFF to an ON state storing a logic 1 state.
For an exemplary read operation as illustrated by waveforms 2900′ in
3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Vertically Oriented NT Switches with Anode-to-NT Switch Connection
In general, methods 3010 fabricate support circuits and interconnections in and/or on a semiconductor substrate. This includes NFET and PFET devices having drain, source, and gate that are interconnected to form memory support circuits such as, for example, circuits 2920, 2930, 2940, 2950, 2960, and 2970 illustrated in
Methods 3020 fabricate an intermediate structure including a planarized insulator with interconnect means and nonvolatile nanotube array structures on the planarized insulator surface. Interconnect means include vertically-oriented filled contacts, or studs, for interconnecting memory support circuits in and on a semiconductor substrate below the planarized insulator with nonvolatile nanotube diode arrays above and on the planarized insulator surface.
Word lines and bit lines can be used in 3D array structures as described further below to interconnect 3-D cells and form 3-D memories, and can be approximately orthogonal in an X-Y plane approximately parallel to underlying memory support circuits. Word line direction has been arbitrarily assigned as along the X axis and bit line direction has arbitrarily assigned as along the Y axis in Figures illustrating exemplary 3D array structures and 3D array structure methods of fabrication as described further below. The Z axis, approximately orthogonal to the X-Y plane, indicates the direction of 3D cell orientation.
Methods 3050 use industry standard fabrication techniques to complete fabrication of the semiconductor chip by adding additional wiring layers as needed, and passivating the chip and adding package interconnect means.
Once support circuits and interconnections in and on the semiconductor substrate are defined, methods then fabricate nonvolatile nanotube diode array such as that illustrated in cross section 3100 above the support circuit and interconnect region as illustrated in
Methods 3010 described further above are used to define support circuits and interconnections 3101.
Next, methods 3030 illustrated in
Methods 3040 illustrated in
In addition to the simultaneous definition of overall cell dimensions without multiple alignment steps, in some embodiments reduced memory cell size (area) also requires the self-aligned placement of device elements within said memory cell boundaries.
Methods fill trenches with an insulator and then methods planarize the surface. Methods deposit and pattern bit lines on the planarized surface.
The fabrication of some embodiments of vertically-oriented 3D cells proceeds as follows. Methods deposit a word line wiring layer on the surface of insulator 3103 having a thickness of 50 to 500 nm, for example, as described further below with respect to FIGS. 36A-36FF. Methods etch the word line wiring layer and define individual word lines such as word lines 3110-1 (WL0) and 3110-2 (WL1). Word lines such as 3110-1 and 3110-2 are used as array wiring conductors and may also be used as individual cell contacts to N+ polysilicon regions 3120-1 and 3120-2. N+ polysilicon regions 3120-1 and 3120-2 contact cathodes formed by N polysilicon regions 3125-1 and 3125-2. Schottky diode junctions 3133-1 and 3133-2 may be formed using metal or silicide 3130-1 and 3130-2 regions in contact with N Polysilicon regions 3125-1 and 3125-2. N Polysilicon regions 3125-1 and 3125-2 may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3 for example, and may have a thickness range of 20 nm to 400 nm, for example. N+ polysilicon is typically doped with arsenic or phosphorous to 1020 dopant atoms/cm3, for example, and has a thickness of 20 to 400 nm, for example.
Examples of contact and conductors materials are elemental metals such as, Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix. Insulators may be SiO2, SiNx, Al2O3, BeO, polyimide, Mylar or other suitable insulating material.
In some cases conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as anodes 3130-1 and 3130-2 for Schottky Diodes. However, in other cases, optimizing anode 3130-1 and 3130-2 material for lower forward voltage drop and lower diode leakage is advantageous. Schottky diode anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn and other elemental metals. Also, silicides such as CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2, and ZrSi2 may be used. Schottky diodes formed using such metals and silicides are illustrated in the reference by NG, K. K. “Complete Guide to Semiconductor Devices”, Second Edition, John Wiley and Sons, 2002m pp. 31-41, the entire contents of which are incorporated herein by reference.
At this point in the exemplary process Schottky diode select devices have been formed. Next, one nonvolatile nanotube switch is formed in each cell having one terminal common with anode metal 3130-1 and 3130-2 for example. In order to enhance the density of cells C00 and C10, the nanotube element in the corresponding nonvolatile nanotube switch is vertically oriented as illustrated in
Methods of forming nanotube elements 3145-1 and 3145-2 include first forming insulators 3135-1 and 3135-2 and contacts 3140-1 and 3140-2, in contact with corresponding insulators 3135-1 and 3135-2, by directionally etching an opening through both metal and insulator regions to form vertical sidewalls. Vertical sidewalls of insulators 3135-1 and 3135-2 and sidewall contacts 3140-1 and 3140-2 are self aligned with respect to trench sidewalls that are etched later in the process using methods of fabrication described further below with respect to FIGS. 36A-36FF. The thickness of insulators 3135-1 and 3135-2 determine the channel length LSW-CH as illustrated in
Next, methods form conformal nanotube elements 3145-1 and 3145-2 as described in greater detail in the incorporated patent references.
Then, methods form protective conformal insulator 3150-1 and 3150-2 on the surface of conformal nanotube elements 3145-1 and 3145-2, respectively.
Next, methods fill the opening with an insulating material and methods planarize the surface exposing the top surface of sidewall contacts 3140-1 and 3140-2.
Then, methods form contacts 3165-1 and 3165-2. Contacts 3165-1 and contacts 3165-2 provide a conductive path between sidewall contacts 3140-1 and 3140-2, respectively, and bit line 3171 (BL0) to be formed after completing the formation of cells C00 and C10. Contacts 3165-1 and 3165-2 correspond to the dimensions of a sacrificial layer used as a trench-etch masking layer of minimum dimension F prior to contacts 3165-1 and 3165-2 formation, as described further below with respect to FIG. 36A-36FF, that is self aligned to NV NT switch elements 3145-1 and 3145.
Then, methods etch trench regions, fill trenches with an insulator, and then planarize the surface to form insulator 3160 prior to contacts 3165-1 and 3165-2 formation described further below with respect to FIG. 36A-36FF.
Then, methods deposit and pattern bit line 3171 (BL0).
Nonvolatile nanotube diode 3190 schematic superimposed on cross section 3100 in
Cross section 3100′ illustrated in
P polysilicon regions 3127-1 and 3127-2 form an anode and N polysilicon regions 3125-10′ and 3125-2′ form a cathode that together form PN diodes with PN diode junctions 3128-1 and 3128-2. P polysilicon regions 3127-1 and 3127-2 also form ohmic or near-ohmic contacts with contact 3130-1′ and 3130-2′. N polysilicon regions 3125-1′ and 3125-2′ also form ohmic contact regions with corresponding N+ polysilicon regions. Other structures of cells C00′ and C10′ are similar to those illustrated and described with respect to cells C00 and C10, respectively.
Memory array support structure 3105 of the embodiment illustrated in
Nonvolatile nanotube diode 3190′ is an equivalent circuit that corresponds to nonvolatile nanotube diode 1300 in
Cross section 3100″ illustrated in
P-type semiconductor nanotube elements, a subset of NT elements 3145-1″ and 3145-2″, in physical and electrical contact with N polysilicon regions 3125-1″ and 3125-2″ form a PN diode-anode and N polysilicon regions 3125-1″ and 3125-2″ form a cathode that together form PN diodes having PN diodes as part of combined PN and Schottky diode junctions 3147-1 and 3147-2. Metallic type nanotube elements, also a subset of NT elements 3145-1″ and 3145-2″, in physical and electrical contact with N polysilicon regions 3125-1″ and 3125-2″, form a Schottky diode-anode and N polysilicon regions 3125-1″ and 3125-2″ form a cathode for Schottky diodes having Schottky diode junctions as part of combined PN and Schottky diode junctions 3147-1 and 3147-2. Therefore, combined PN and Schottky diode junctions 3147-1 and 3147-2 are composed of PN-type diodes and Schottky-type diodes in parallel and are formed by nanotube elements 3145-1″ and 3145-2″ in contact with N polysilicon regions 3125-1″ and 3125-2″, respectively.
N polysilicon regions 3125-1″ and 3125-2″ also form ohmic contact regions with corresponding N+ polysilicon regions 3120-1″ and 3120-2″, respectively. Nanotube element 3145-1″ and 3145-2″ are also in physical and electrical contact with sidewall contacts 3140-1″ and 3140-2″. Sidewall contacts 3140-1″ and 3140-2″ are in contact with upper level contacts 3165-1″ and 3165-2″, respectively, which are in contact with bit line bit line 3171″ (BL0). Formation of upper level contacts is briefly described further above with respect to
Memory array support structure 3105-3 illustrated in the embodiment of
Nonvolatile nanotube diode 3190″ is an equivalent circuit that corresponds to nonvolatile nanotube diode 1300 in
Nonvolatile Memories using NV NT Diode Device Stacks with both Anode-to-NT Switch Connections and Cathode-to-NT Switch Connections
In general, methods 3210 fabricate support circuits and interconnections in and/or on a semiconductor substrate. This includes NFET and PFET devices having drain, source, and gate that can be interconnected to form memory (or logic) support (or select) circuits. Such structures and circuits may be formed using known techniques that are not described in this application. Methods 3210 are used to form a support circuits and interconnections 3301 layer as part of cross section 3305 illustrated in
Next, methods 3210 are also used to fabricate an intermediate structure including a planarized insulator with interconnect means and nonvolatile nanotube array structures on the planarized insulator surface such as insulator 3303 illustrated in cross section 3305 in
Next, methods 3220, similar to methods 2740, are used to fabricate a first memory array 3310 using diode cathode-to-nanotube switches based on a nonvolatile nanotube diode array similar to a nonvolatile nanotube diode array cross section 2800 illustrated in
Next, methods 3230 similar to methods 3040 illustrated in
FIG. 33B′ illustrates cross section 3305′ including first memory array 3310′ and second memory array 3320′ with both arrays sharing word lines 3330′ and 3332 in common, according to some embodiments. Word line 3330′ is a cross sectional view of word line 3330. Word lines such as 3330′ and 3332 can be defined (etched) during a trench etch that defines memory array (cells) when forming array 3320′. Cross section 3305′ illustrates combined first memory array 3310′ and second memory array 3320′ in the bit line, or Y direction, with shared word lines 3330′ (WL0) and 3332 (WL1), two bit lines BL0 and BL2, and corresponding cells COO, C10, C02, and C12. The array periodicity in the Y direction is 2F, where F is a minimum dimension for a technology node (generation).
The memory array cell area of 1 bit for array 3310 can be down to 4F2 because of the 2F periodicity in the X and Y directions. The memory array cell area of 1 bit for array 3320 can be down to 4F2 because of the 2F periodicity in the X and Y directions. Because memory arrays 3320 and 3310 are stacked, the memory array cell area per bit can be down to 2F2. If four memory arrays (not shown) are stacked, then the memory array cell area per bit can be down to 1F2.
Referring again to
Cross section 3305 illustrated in
In operation, the four stacked cells illustrated in
For an exemplary write 0 operation along word line WL0, simultaneously erasing cells C00, C01, C02, and C03, data stored in cells C00-C03 may optionally be read prior to erase and data stored in corresponding sense amplifier/latches. Write 0 operation along word line WL0 proceeds with bit lines BL0, BL1, BL2, and B3 transitioning from zero to 5 volts, with bit line voltages controlled by corresponding BL drivers. Next, WL driver circuits drive word line WL0 from 5 volts to zero volts thus forward biasing NV NT Diodes C00, C01, C02, and C03 that form cells C00, C01, C02, and C03, respectively. A write 0 voltage of approximately 4.5 volts (erase voltage 5 volts minus NV NT diode turn on voltage of less than 0.5 volts as illustrated in
In this example, a write operation is preceded by a write 0 operation as described further above. In other words, NV NT Diodes C00-C03 of respective corresponding cells C00-C03 begin the write operation in the OFF state. For an exemplary write 0 operation to cells C00 and C03 for example, in which a logic 0 state is to be stored, NV NT Diodes C00 and C03 are to remain in the logic 0 high resistance state. Therefore, bit lines BL0 and BL3 are held at zero volts by corresponding BL driver and sense circuits. Next, word line WL0 transitions from 4 volts to zero volts, with stimulus from corresponding WL drivers. NV NT Diodes C00 and C03 remain back biased during the write 0 operation and cells C00 and C03 remain in an OFF (high resistance) logic 0 state.
If NV NT Diodes C01 and C02 are to transition from an OFF (high resistance state) to an ON (low resistance state) in a write 1 operation representing a logic 1, then bit lines BL1 and BL2 transition from zero volts to 4 volts, with stimulus provided by corresponding BL drivers. Next, word line WL0 transitions from 4 volts to zero volts. A write 1 voltage of approximately 4 volts results in a voltage of 3.5 volts across the terminals of corresponding NV NT switch sub-components of NV NT diode C01 and C02 (4 volts minus NV NT diode turn on voltage of less than 0.5 volts as illustrated in
For an exemplary read operation, from cells C00-C03 for example, corresponding bit line drivers in corresponding BL driver and sense circuits precharge bit lines BL0-BL3 to a high voltage such as a read voltage of 2 volts, for example. The read bit line voltage is selected to be less than both write 0 and write 1 voltages to ensure that stored logic states (bits) are not disturbed (changed) during a read operation. Word line drivers drive word line WL0 from 2 volts to zero volts. NV NT Diodes C00 and C03 in corresponding cells C01 and C03 are in an OFF state (storing a logic 0) and bit lines BL0 and BL3 are not discharged and remains at 2 volts. Corresponding sense amplifier/latches store corresponding logic 0 states. However, since NV NT
Diode C01 and C02 in corresponding cells C01 and C02 are in an ON state, then bit lines BL1 and BL2 are discharged. Corresponding sense amplifier/latches detect a reduced voltage and latches store corresponding logic 1 states.
Note that the memory array illustrated in cross section 3350″ of
Methods of Fabricating Nonvolatile Memories using Nonvolatile Nanotube Diode (NV NT Diode) Devices as Cells
Exemplary methods of fabricating embodiments of 3-dimensional cell structures of nonvolatile cells using NV NT devices having vertically oriented diodes and vertically oriented NV NT switches with cathode-to-NT switch connections such as illustrated by cross section 2800 illustrated in
Exemplary methods of fabricating embodiments of 3-dimensional cell structure of nonvolatile cells using NV NT Devices having vertically oriented diodes and horizontally oriented NV NT switches with cathode-to-NT switch connections such as illustrated by cross section 2800″ illustrated in
Exemplary methods of fabricating 3-dimensional cell structure embodiments of nonvolatile cells using NV NT devices having vertically oriented diodes and vertically oriented NV NT switches with anode-to-NT switch connections such as illustrated by cross section 3100 illustrated in
Exemplary methods of fabrication of embodiments of stacked arrays based on 3-dimensional cell structures of nonvolatile cells using NV NT Devices having vertically oriented diodes and vertically oriented NV NT switches using both cathode-to-NT Switch and anode-to-NT switch connected cell types, such as those shown in cross section 3300 illustrated in
Methods of Fabricating Nonvolatile Memories using NV NT Diode Devices with Cathode-to-NT Switch Connection
Methods 2700 illustrated in
Methods of fabricating cross sections 2800 and 2800′ typically require critical alignments in X direction process steps. There are no critical alignments in the Y direction because in this example distance between trenches determines the width of the nanotube element. However, the width of the nanotube element may be formed to be less than the trench-to-trench spacing by using methods similar to those described further below with respect to the X direction. In the X direction, critical alignment requirements are eliminated by using methods that form self-aligned internal cell vertical sidewalls that define vertical nanotube channel element location, vertical channel element length (LSW-CH), and form nanotube channel element contacts with respect to trench sidewalls that are etched later in the process to define outer cell dimensions using methods of fabrication described further below with respect to FIGS. 34A-34FF. In this example, NV NT diode cell structures occupy a minimum dimension F in the X and Y directions, where F is a minimum photolithographic dimension. In this example, the internal cell vertical sidewall is positioned (by self alignment techniques) at approximately R distance from trench sidewalls that are separated by distance F and that define outer cell dimensions as illustrated further below with respect to FIGS. 34A-34FF. FIGS. 34A-34FF is illustrated with a spacing R of approximately F/2. However, methods using self alignment techniques described further below with respect to FIGS. 34A-34FF may position a vertical sidewall at any location R within the cell region of width F using R values of F/4, F/3, F/2, 3F/4, etc for example.
Methods 2700 illustrated in
Methods of Fabricating 3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Vertically Oriented NT Switches with Cathode-to-NT Switch Connection
Methods 2710 illustrated in
Next, methods 2730 illustrated in
Next, methods deposit a conductor layer 3410 on the planarized surface of insulator 3403 as illustrated in
Next, methods deposit a an optional conductive Schottky anode contact layer 3415 having a thickness range of 10 to 500 nm, for example, on the surface of conductor layer 3410. Anode contact layer 3415 may use similar materials to those used in forming conductor layer 3410 (or contact layer 3415 may be omitted entirely and conductor layer 3410 may be used to form a Schottky anode), or anode contact layer 3415 material may be chosen to optimize anode material for enhanced Schottky diode properties such lower forward voltage drop and/or lower diode leakage. Anode contact layer 3415 may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn and other elemental metals. Also, silicides such as CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2, and ZrSi2 may be used.
Next, methods deposit an N polysilicon layer 3420 of thickness 10 nm to 500 nm on the surface of anode contact layer 3415. N polysilicon layer 3420 may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3, for example. N polysilicon layer 3420 may be used to form cathodes of Schottky diodes. In addition to doping levels, the polysilicon crystalline size (or grain structure) of N Polysilicon layer 3420 may also be controlled by known industry methods of deposition. Also, known industry SOI methods of deposition may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline.
Next, having completed memory support structure 3405, then deposited conductor layer 3410 which may be used as an array wiring layer, and then completed the deposition of Schottky diode forming layers 3415 and 3420, methods deposit N+ polysilicon layer 3425 on the surface of N polysilicon layer 3420 as illustrated in
At this point in the process, remaining methods may be used to fabricate NV NT diode using Schottky diode-based cathode-to-NT switch structures such as those illustrated in
Methods 2700 described further above, and with respect to
Next, methods deposit planarized insulator 3403′ on the surface of support circuits and interconnections 3401′ as illustrated in FIG. 34A′. Planarized insulator 3403′ corresponds to planarized insulator 3403 except for possible small changes that may be introduced in insulator 3403′ to accommodate differences in diode characteristics. Memory support structure 3405′ is therefore similar to support structures 3405 except for small changes that may be introduced in support circuits and interconnections 3401′ and planarized insulator 3403′ as described further above with respect to FIG. 34A′.
Next, methods deposit conductor layer 3410′ in contact with the surface of planarized insulator 3403′ as illustrated in FIG. 34A′ which is similar in thickness and materials to conductor layer 3410 described further above with respect to
Next, methods deposit a P polysilicon layer 3417 of thickness 10 nm to 500 nm on the surface of conductor layer 3410′ as illustrated in FIG. 34A′. P polysilicon layer 3417 may be doped with boron in the range of 1014 to 1017 dopant atoms/cm3, for example. P polysilicon layer 3417 may be used to form anodes of PN diodes. In addition to doping levels, the polysilicon crystalline size of P Polysilicon layer 3417 may also be controlled by known industry methods of deposition. Also, known industry SOI methods of deposition may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline.
Next, methods deposit an N polysilicon layer 3420′ of thickness 10 nm to 500 nm on the surface of P polysilicon layer 3417 that may be used to form cathodes of PN diodes. N polysilicon layer 3420′ may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3, for example. In addition to doping levels, the polysilicon crystalline size (grain structure) of N Polysilicon layer 3420′ may also be controlled by known industry methods of deposition. Also, known industry SOI methods of deposition may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline.
Next, having completed memory support structure 3405′, then deposited conductor layer 3410′ which may be used as an array wiring layer, and then completed the deposition PN diode forming layers 3417 and 3420′, N+ polysilicon layer 3425′ is deposited on N polysilicon layer 3420′ in order to form an ohmic contact layer as illustrated in FIG. 34A′. N+ polysilicon layer 3425′ is typically doped with arsenic or phosphorous to 1020 dopant atoms/cm3, for example, and has a thickness of 20 to 400 nm, for example.
Descriptions of methods of fabrication continue with respect to Schottky-diode based structures described with respect to
At this point in the fabrication process, methods deposit contact layer 3430 on the surface of N+ polysilicon layer 3425 as illustrated in
Next, methods deposit an insulator layer 3435 on contact layer 3430 as illustrated in
Next, methods deposit contact layer 3440 on insulator layer 3435 as illustrated in
Next methods deposit sacrificial layer 3441 on contact layer 3440 as illustrated in
Next, methods deposit and pattern a masking layer such as masking layer 3442 deposited on the top surface of sacrificial layer 3441 as illustrated in
Then, methods directionally etch sacrificial layer 3441 to form an opening of dimension DOPEN-1 in the X direction through sacrificial layer 3441 stopping at the surface of contact layer 3440 using known industry methods as illustrated in
Next, methods deposit a conformal sacrificial layer 3443 as illustrated in
Next, methods directionally etch conformal sacrificial layer 3443 using reactive ion etch (RIE) for example, using known industry methods, forming opening 3444 of dimension DOPEN-2 and sacrificial regions 3443′ and 3443″, both having vertical sidewalls self-aligned and separated from inner vertical sidewall of sacrificial regions 3441′ and 3441″, respectively, by a distance R in the X direction as illustrated in
Next, methods directionally etch an opening through contact layer 3440 to the top surface of insulator layer 3435. Directional etching using RIE, for example, forms an opening of size DOPEN-2 of approximately 2F (130 nm in this example) in contact layer 3440, and forms sidewall contact regions 3440′ and 3440″ as illustrated in
Next, methods directionally etch an opening through insulator layer 3435 to the top surface of contact layer 3430. Directional etching using RIE, for example, forms an opening 3444′ of size DOPEN-2 of approximately 2F (130 nm in this example) in insulator layer 3435, and forms insulator regions 3435′ and 3435″ as illustrated in
Next, methods deposit conformal nanotube element 3445 with vertical (Z) orientation on the sidewalls of opening 3444′ as illustrated in
Since nanotube element 3445 is in contact with contact layer 3430 and the sidewalls of sidewall contact regions 3440′ and 3440″, separated by the thickness of insulator region 3435′ and 3435″, respectively, two nonvolatile nanotube switch channel regions are partially formed (channel width is not yet defined) having channel length LSW-CH in the Z direction corresponding to the thickness of insulator regions 3435′ and 3435″ in the range of 5 nm to 250 nm as illustrated in
Next methods deposit conformal insulator layer 3450 on nanotube element 3445 as an insulating and protective layer and reduces opening 3444′ to opening 3451 as illustrated in
At this point in the process, it is desirable to partially fill opening 3451 by increasing the thickness of the bottom portion of insulator 3450 in the vertical (Z direction) on horizontal surfaces with little or no thickness increase on the sidewalls (vertical surfaces) of insulator 3450, forming insulator 3450′. Exemplary industry methods of using HDP deposition to fill openings with a dielectric layer are disclosed in U.S. Pat. No. 4,916,087, the entire contents of which are incorporated herein by reference, for example. However, U.S. Pat. No. 4,916,087 fills openings by depositing dielectric material on horizontal and vertical surfaces. Other methods of directional HDP insulator deposition may be used instead, e.g., by directionally depositing a dielectric material such that more than 90% of the insulator material is deposited on horizontal surfaces and less than 10% of the insulator material is deposited on vertical surfaces with good thickness control. A short isotropic etch may be used to remove insulator material deposited on vertical surfaces. The thickness of the additional dielectric material is not critical. The additional dielectric material may be the same as that of conformal insulator 3450 or may be a different dielectric material. Dielectric material selection with respect to nanotube elements is described in greater detail in U.S. patent application Ser. No. 11/280,786.
Next, methods directionally deposit an insulator material in opening 3451 using known industry methods such as selective HDP insulator deposition and increase insulator thickness primarily on horizontal surfaces as illustrated by insulator 3450′ in opening 3451′ and on top surfaces in
Next, methods deposit and planarize an insulator 3452 such as TEOS filling opening 3451′ as illustrated in
Next, methods planarize the structure illustrated in
Next, methods etch (remove) sacrificial regions 3443′ and 3443″ and insulator 3452′. Exposed vertical sidewalls of nanotube element 3445′ and conformal insulator 3450″ remain as illustrated in
Next, methods etch (remove) the exposed portion of nanotube element 3445′ forming nanotube element 3445″ as illustrated in
Then, methods such as isotropic etch remove exposed portions of insulator 3450′ to form insulator 3450′″.
At this point in the process, sidewall spacer methods are applied as illustrated further below to form self aligned sacrificial regions to be replaced further along in the fabrication process as illustrated further below by a conductor material to form the upper portion of nanotube element contacts and also to define self aligned trench regions to be used to define self-aligned cell dimensions along the X direction as also illustrated further below. Using sidewall spacer methods to form self aligned structures without requiring masking and alignment results in minimum cell areas.
In this example, with respect to
Next, methods directionally etch conformal sacrificial layer 3455 using reactive ion etch (RIE) for example, using known industry methods, forming opening 3451″ of dimension approximately F, which in this example is approximately 65 nm as illustrated in
Next, methods deposit and planarize a sacrificial layer to form sacrificial region 3456 coplanar with sacrificial regions 3455′, 3455″, 3441′, and 3441″ as illustrated in
Next, methods apply CMP etching to reduce the thickness of sacrificial region 3456 to form sacrificial region 3458; the thickness of sacrificial regions 3455′ and 3455″ to form sacrificial regions 3455-1 and 3455-2, respectively; and the thickness of sacrificial regions 3441′ and 3441″ to form sacrificial regions 3458′ and 3458″, respectively as illustrated in
At this point in the process, sacrificial regions 3455-1 and 3455-2 may be used as masking layers for directional etching of trenches using methods that define outer cell dimensions along the X direction for 3D cells using one NV NT diode with cathode-to-nanotube connection. U.S. Pat. No. 5,670,803 to co-inventor Bertin discloses a 3-D array (in this example, 3D-SRAM) structure with simultaneously trench-defined sidewall dimensions. This structure includes vertical sidewalls simultaneously defined by trenches cutting through multiple layers of doped silicon and insulated regions in order avoid multiple alignment steps. Such trench directional selective etch methods may cut through multiple conductor, semiconductor, and oxide layers and stop on the top surface of a supporting insulator (SiO2) layer between the 3D array structure and an underlying semiconductor substrate. Trench 3459 is formed first and then filled with an insulator and planarized. Then, trenches 3459′, and 3459″ are formed simultaneously and then filled and planarized as illustrated further below. Other corresponding trenches (not shown) are also etched when forming the memory array structure. Exemplary method steps that may be used to form trench regions 3459, 3459′, and 3459″ and then fill the trenches to form insulating trench regions are described further below.
Sacrificial regions 3458′ and 3458″ that define the location of trench regions 3459′ and 3459″ that are formed as described further below may be blocked with a sacrificial noncritical masking layer (not shown), while methods form trench 3469 using known directional selective etch methods such as reactive ion etch (RIE). Trench 3459 forms a first of two opposite vertical sidewalls in the X direction defining one side of NV NT diode cells. Alternatively, sacrificial region 3458 that defines the location of trench region 3459 that is formed further below may be etched selective to sacrificial regions 3458′ and 3458″ without requiring a noncritical masking layer.
First, methods directionally selectively etch (remove) exposed regions (portions) of sacrificial region 3458 using known industry methods as illustrated in
Next, methods selectively etch exposed regions (portions) of conformal insulator 3450′″ using known industry methods and form conformal insulators 3450-1 and c3450-2 as illustrated in
Next, methods selectively etch exposed regions of nanotube element 3445″ and form nanotube elements 3445-1 and 3445-2 as illustrated in
Next, methods selectively etch exposed regions of contact layer 3430 using known industry methods.
Next, methods selectively etch exposed regions of N+ polysilicon layer 3425 using known industry methods.
Next, methods selectively etch exposed regions of N polysilicon layer 3420 using known industry methods.
Next, methods selectively etch exposed regions of contact layer 3415 using known industry methods.
Then, methods etch exposed regions of conductor layer 3410 using known industry methods, forming trench 3459. Directional etching stops at the surface of planar insulator 3403.
Next, methods fill and planarize trench 3459 with an insulator such as TEOS for example forming insulator 3460 using known industry methods as illustrated in
Next, methods form a noncritical mask region (not shown) over insulator 3460.
Next, sacrificial regions 3458′ and 3458″ are selectively etched (removed) as illustrated in
First, methods directionally selectively etch (remove) exposed portions of contact 3440′ and 3440″ using known industry methods and expose a portion of the top surface of semiconductor layers 3435′ and 3435″ and define contact 3440-1 and 3440-2 regions as illustrated in
Next, methods selectively etch exposed portions of insulator regions 3435′ and 3435″ using known industry methods and form insulator regions 3435-1 and 3435-2.
Next, methods selectively etch exposed portions of contact regions 3430′ and 3430″ using known industry methods and form contact regions 3430-1 and 3430-2.
Next, methods selectively etch exposed portions of N+ polysilicon layer 3425′ and 3425″ using known industry methods and form N+ polysilicon regions 3425-1 and 3425-2.
Next, methods selectively etch exposed portions of N polysilicon layer 3420′ and 3420″ using known industry methods and form N polysilicon regions 3420-1 and 3420-2 as illustrated in
Next, methods selectively etch exposed regions of contact layer 3415′ and 3415″ using known industry methods and form contact regions 3415-1 and 3415-2.
Then, methods selectively etch exposed portions of conductor layer 3410′ and 3410″ using known industry methods and form bit lines 3410-1 (BL0) and 3410-2 (BL1). Directional etching stops at the surface of planar insulator 3403 as illustrated in
Next, methods deposit and planarize an insulator such as TEOS and fill trench openings 3459′ and 3459″ with insulators 3460′ and 3460″, respectively, as illustrated in
Next, methods etch (remove) sacrificial regions 3455-1 and 3455-2.
Next, methods deposit and planarize conductor 3465′ to form upper layer contacts 3465-1 and 3465-2 as illustrated in FIGS. 34Z and 34AA.
Next, methods deposit and planarize conductive layer 3471 using known industry methods to form cross section 3470 as illustrated in FIG. 34BB. Cross section 3470 corresponds to cross section 2800 illustrated in
At this point in the process, cross section 3470 illustrated in FIG. 34BB has been fabricated, and includes NV NT diode cell dimensions of 1F (where F is a minimum feature size) defined in the X direction as well as corresponding array bit lines. Next, cell dimensions used to define dimensions in the Y direction are formed by directional trench etch processes similar to those described further above with respect to cross section 3470 illustrated in FIG. 34BB. Trenches used to define dimensions in the Y direction are approximately orthogonal to trenches used to define dimensions in the X direction. In this example, cell characteristics in the Y direction do not require self alignment techniques described further above with respect to X direction dimensions. Cross sections of structures in the Y direction are illustrated with respect to cross section A-A′ illustrated in FIG. 34BB.
Next, methods deposit and pattern a masking layer such as masking layer 3473 on the surface of word line layer 3471 as illustrated in FIG. 34CC. Masking layer 3473 may be non-critically aligned to alignment marks in planar insulator 3403. Openings 3474, 3474′, and 3474″ in mask layer 3473 determine the location of trench directional etch regions, in this case trenches are approximately orthogonal to bit lines such as bit line 3410-1 (BL0).
Next, methods form trenches 3475, 3475′, and 3475″ corresponding to openings 3474, 3474′, and 3474″, respectively, in masking layer 3473. Trenches 3475, 3475′, and 3475″ form two sides of vertical sidewalls in the Y direction defining two opposing sides of NV NT diode cells as illustrated in FIG. 34DD.
Then, methods directionally selectively etch (remove) exposed portions of word line layer 3471 illustrated in FIG. 34DD using known industry methods to form word lines 3471-1 (WL0) and 3471-2 (WL1) illustrated in FIG. 34DD.
Next, methods selectively etch exposed portions of contact region 3465-1 illustrated in FIG. 34CC using known industry methods to form contacts 3465-1′ and 3465-1″ as illustrated in FIG. 34DD.
Next, methods selectively etch exposed portions of contact region 3440-1, nanotube element 3455-1, and conformal insulator 3450-1 illustrated in FIG. 34BB using known industry methods to form contacts 3440-1′ and 3440-1″, conformal insulator regions (not shown in FIG. 34DD cross section A-A′), and nanotube elements 3445-1′ and 3445-1″ as illustrated in FIG. 34DD.
Next, methods selectively etch exposed regions of insulators 3435-1, nanotube element 3455-1, and conformal insulator 3450-1 illustrated in FIG. 34BB using known industry methods to form insulator regions and conformal insulator regions (not shown in FIG. 34DD cross section A-A′) and nanotube elements 3445-1′ and 3445-1″ illustrated in FIG. 34DD.
Next, methods selectively etch exposed portions of contact regions 3430-1 and 3430-2 illustrated in FIGS. 34BB and 34CC using known industry methods and form contacts 3430-1′ and 3430-1″ illustrated in FIG. 34DD (cross section A-A′).
Next, methods selectively etch exposed portions of N+ polysilicon regions 3425-1 and 3425-2 illustrated in FIG. 34BB using known industry methods and form N+ polysilicon regions 3425-1′ and 3425-1″ illustrated in FIG. 34DD (cross section A-A′).
Next, methods selectively etch exposed portions of N polysilicon regions 3420-1 and 3420-2 illustrated in FIG. 34BB using known industry methods and form N polysilicon regions 3420-1′ and 3420-1″ illustrated in FIG. 34DD (cross section A-A′).
Then, methods selectively etch exposed portions of contact regions 3415-1 and 3415-2 illustrated in FIG. 34BB using known industry methods and form insulators 3415-1′ and 3415-1″ illustrated in FIG. 34DD (cross section A-A′). Directional etching stops at the surface of bit line 3410-1.
Next, methods deposit insulator 3476 using known industry methods as illustrated in FIG. 34EE. Insulator 3476 may be TEOS, for example.
Then, methods planarize insulator 3476 to form insulator 3476′ using known industry methods and form cross section 3470′ illustrated in FIG. 34FF. Cross section 3470′ illustrated in FIG. 34FF and cross section 3470 illustrated in FIG. 34BB are two cross sectional representations of the same passivated NV NT diode vertically oriented cell. Cross section 3470 illustrated in FIG. 34BB corresponds to cross section 2800 illustrated in
At this point in the process, cross sections 3470 and 3470′ illustrated in FIGS. 34BB and 34FF, respectively, have been fabricated, nonvolatile nanotube element vertically-oriented channel length LSW-CH and horizontally-oriented channel width WSW-CH are defined, including overall NV NT diode cell dimensions of 1F in the X direction and 1F in the Y direction, as well as corresponding bit and word array lines. Cross section 3470 is a cross section of two adjacent vertically oriented cathode-to-nanotube type nonvolatile nanotube diode-based cells in the X direction and cross section 3470′ is a cross section of two adjacent vertically oriented cathode-to-nanotube type nonvolatile nanotube diode-based cells in the cells in the Y direction. Cross sections 3470 and 3470′ include corresponding word line and bit line array lines. The nonvolatile nanotube diodes form the steering and storage elements in each cell illustrated in cross sections 3470 and 3470′ each occupy a 1F by 1F area. The spacing between adjacent cells is 1F so the cell periodicity can be as low as 2F in both the X and Y directions. Therefore one bit can occupy an area of as low as 4F2. At the 65 nm technology node, for example, the cell area is less than 0.02 um2.
Methods of Fabricating 3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Horizontally Oriented NT Switches with Cathode-to-NT Switch Connection
Methods 2710 illustrated in
Next, methods 2730 illustrated in
Next, methods form interconnect contact 3507 through planar insulator 3503 as illustrated in
Next, methods deposit a conductor layer 3510 on the planarized surface of insulator 3503 as illustrated in
Next, methods deposit an N polysilicon layer 3520 of thickness 10 nm to 500 nm on the surface of conductor 3510. N polysilicon layer 3520 may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3, for example. N polysilicon layer 3520 may be used to form cathodes of Schottky diodes. In addition to doping levels, the polysilicon crystalline size (or grain structure) of N Polysilicon layer 3420 may also be controlled by known industry methods of deposition. Also, known industry SOI methods of deposition may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline.
Next, methods deposit N+ polysilicon layer 3525 on the surface of N polysilicon layer 3520 as illustrated in
Next, methods deposit an insulator layer 3530 on N+ layer 3525 as illustrated in
At this point in the fabrication process, methods deposit contact layer 3535 on the surface of insulator layer 3530 as illustrated in
Next, methods directionally etch opening 3537 through contact layer 3535 and insulator layer 3530 to the top surface of N+ polysilicon layer 3525 as illustrated in
Next methods deposit conformal insulator layer 3540′ in contact with surface regions of contact 3535 and N+ polysilicon layer 3525 and on exposed sidewall surface regions of contact 3535 and insulator 3530 as illustrated in
Next, methods directionally etch insulator 3540′ using known industry methods such as RIE and form sidewall spacer regions 3540 illustrated in
Next, methods deposit and planarize conductor 3545′ to form contact 3545 as illustrated in
Next, methods deposit conformal nanotube element 3550 on a coplanar surface formed by contact 3535, sidewalls 3540, and contact 3545 as illustrated in
Next, methods deposit insulator layer 3555 on nanotube element 3550 as an insulating and protective layer as illustrated in
Next, methods pattern and etch opening 3560 as illustrated in
Next, methods deposit and planarize conductor 3565′ to form contact 3565 as illustrated in
Next, masking layer 3570 is patterned in the X direction as illustrated in
Next, methods selectively etch exposed portions of insulator 3555 using known industry methods and form insulator region 3555′.
Next, methods selectively etch exposed regions of nanotube element 3550 and form nanotube element 3550′ as illustrated in
Next, methods selectively etch exposed portions of contact 3535 using know industry methods and form contact region 3535′.
Next, methods selectively etch exposed portions of insulator 3530 and form insulator region 3530′.
Next, methods selectively etch exposed portions of N+ polysilicon layer 3525 using known industry methods and form N+ polysilicon region 3525′.
Next, methods selectively etch exposed portions of N polysilicon layer 3520 using known industry methods and form N polysilicon region 3520′ as illustrated in
Then, methods selectively etch exposed portions of conductor layer 3510 using known industry methods and forms bit line 3510′ (BL0). Directional etching stops at the surface of planar insulator 3503 as illustrated in
Next, methods deposit an insulator 3574 such as TEOS, for example, to fill trench openings 3572 and 3572′ and then methods planarize insulator 3574 to form insulator 3574′ as illustrated in
Next, methods deposit and planarize conductive layer 3575 corresponding to array word line WL0 using known industry methods to form cross section 3580 as illustrated in
At this point in the process, cross section 3580 illustrated in
Next, methods deposit and pattern a masking layer such as masking layer 3581 on the surface of word line layer 3575′ as illustrated in
Next, methods form trenches 3582 and 3582′ corresponding to openings in masking layer 3581. Trenches 3582 and 3582′ form two sides of vertical sidewalls in the Y direction defining two opposing sides of NV NT diode cells as illustrated in
Next, methods directionally selectively etch (remove) exposed portions of word line layer 3575 illustrated in
Next, methods selectively etch exposed portions of insulator 3555′ as illustrated in
Next, methods selectively etch (remove) exposed portions of nanotube element 3550′ forming nanotube element 3550″ as illustrated in
Next, methods selectively etch exposed portions of contact 3545 forming contact 3545′ as illustrated in
Next, methods selectively etch exposed portions of insulator 3530′ to form a modified insulator 3530′ not illustrated in
Next, methods selectively etch exposed portions of N+ polysilicon regions 3525′ illustrated using known industry methods and form N+ polysilicon region 3525″ illustrated in
Next, methods selectively etch exposed portions of N polysilicon regions 3520′ illustrated using known industry methods and form N+ polysilicon region 3520″ illustrated in
Next, methods deposit insulator 3585 using known industry methods as illustrated in
Then, methods planarize insulator 3585 to form insulator 3585′ using known industry methods and form cross section 3580′ illustrated in
Methods of Fabricating Nonvolatile Memories using NV NT Diode Devices with Anode-to-NT Switch Connection
Exemplary methods 3000 illustrated in
Exemplary methods of fabricating cross sections 3000, 3000′, and 3000″ can be performed using critical alignments in Y direction process steps. There are no critical alignments in the X direction because in this example distance between trenches determines the width of the nanotube element. However, the width of the nanotube element may be formed to be less than the trench-to-trench spacing by using methods similar to those described further below with respect to the Y direction. In the Y direction, critical alignment requirements can be eliminated by using methods that form self-aligned internal cell vertical sidewalls that define vertical nanotube channel element location, vertical channel element length (LSW
Methods of Fabricating 3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Vertically Oriented NT Switches with Anode-to-NT Switch Connection
Exemplary methods 3010 illustrated in
Next, methods 3030 illustrated in
Next, methods deposit a conductor layer 3610 on the planarized surface of insulator 3603 as illustrated in
Next, methods deposit N+ polysilicon layer 3620 on the surface of conductor layer 3610 as illustrated in
Next, methods deposit an N polysilicon layer 3625 of thickness 10 nm to 500 nm on the surface of N+ polysilicon layer 3620. N polysilicon layer 3625 may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3, for example. N polysilicon layer 3625 may be used to form cathodes of Schottky diodes. In addition to doping levels, the polysilicon crystalline size (or grain structure) of N polysilicon layer 3625 may also be controlled by known industry methods of deposition. Also, known industry SOI methods of deposition may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline.
Next, methods deposit contact layer 3630 on the surface of N polysilicon layer 3625 forming a Schottky diode anode layer. Contact layer 3630 may also be used to form lower level contacts for nanotube elements as illustrated further below with respect to
At this point in the process, remaining methods may be used to fabricate NV NT diode using Schottky diode-based anode-to-NT switch structures such as those illustrated in
Methods 3000 described further above, and with respect to
Next, methods deposit planarized insulator 3603′ on the surface of support circuits and interconnections 3601′ as illustrated in FIG. 36A′. Planarized insulator 3603′ corresponds to planarized insulator 3603 except for possible small changes that may be introduced in insulator 3603′ to accommodate differences in diode characteristics. Memory support structure 3605′ is therefore similar to support structures 3605 except for small changes that may be introduced in support circuits and interconnections 3601′ and planarized insulator 3603′ as described further above with respect to FIG. 36A′.
Next, methods deposit conductor layer 3610′ in contact with the surface of planarized insulator 3603′ as illustrated in FIG. 36A′ which can be similar in thickness and materials to conductor layer 3610 described further above with respect to
Next, methods deposit N+ polysilicon layer 3620′ on the surface of conductor layer 3610′ as illustrated in FIG. 36A′ in order to form an ohmic contact layer. N+ polysilicon layer 3620′ is typically doped with arsenic or phosphorous to 1020 dopant atoms/cm3, for example, and has a thickness of 20 to 400 nm, for example.
Next, methods deposit an N polysilicon layer 3625′ of thickness 10 nm to 500 nm on the surface of N+ polysilicon layer 3620′. N polysilicon layer 3625′ may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3, for example. N polysilicon layer 3625′ may be used to form cathodes of Schottky diodes. In addition to doping levels, the polysilicon crystalline size (or grain structure) of N polysilicon layer 3625′ may also be controlled by known industry methods of deposition. Also, known industry SOI methods of deposition may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline.
Next, methods deposit a P polysilicon layer 3627 of thickness 10 nm to 500 nm on the surface of N polysilicon layer 3625′ as illustrated in FIG. 36A′. P polysilicon layer 3627 may be doped with boron in the range of 1014 to 1017 dopant atoms/cm3, for example. P polysilicon layer 3627 may be used to form anodes of PN diodes. In addition to doping levels, the polysilicon crystalline size of P Polysilicon layer 3627 may also be controlled by known industry methods of deposition. Also, known industry SOI methods of deposition may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline.
Next, methods deposit contact layer 3630′ on the surface of P polysilicon layer 3627 forming an ohmic contact between contact layer 3630′ and P polysilicon layer 3627. Contact layer 3630′ may also be used to form lower level contacts for nanotube elements as illustrated further below with respect to
At this point in the process, remaining methods may be used to fabricate NV NT diode using PN diode-based anode-to-NT switch structures such as those illustrated in
Methods 3000 described further above, and with respect to
Next, methods deposit conductor layer 3610″ in contact with the surface of planarized insulator 3603″ as illustrated in FIG. 36A″ which is similar in thickness and materials to conductor layer 3610 described further above with respect to
Next, methods deposit N+ polysilicon layer 3620″ on the surface of conductor layer 3610″ as illustrated in FIG. 36A″ in order to form an ohmic contact layer. N+ polysilicon layer 3620″ is typically doped with arsenic or phosphorous to 1020 dopant atoms/cm3, for example, and has a thickness of 20 to 400 nm, for example.
Next, methods deposit an N polysilicon layer 3625″ of thickness 10 nm to 500 nm on the surface of N+ polysilicon layer 3620″. N polysilicon layer 3625″ may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3, for example. N polysilicon layer 3625″ may be used to form cathodes of both Schottky diodes and PN diodes in parallel. In addition to doping levels, the polysilicon crystalline size (or grain structure) of N polysilicon layer 3625″ may also be controlled by known industry methods of deposition. Also, known industry SOI methods of deposition may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline.
At this point in the process, remaining methods may be used to fabricate NV NT diodes using Schottky diodes and PN diode in parallel to form anode-to-NT switch structures such as those illustrated in
Schottky diodes and PN diodes in parallel are formed because a nanotube element such as nanotube element 3645 illustrated further below with respect to
Descriptions of methods of fabrication continue with respect to Schottky-diode based structures described with respect to
At this point in process, fabrication continues by using methods to deposit an insulator layer 3635 on contact layer 3630 as illustrated in
Next, methods deposit contact layer 3640 on insulator layer 3635 as illustrated in
Next methods deposit sacrificial layer 3641 on contact layer 3640 as illustrated in
Next, methods deposit and pattern a masking layer such as masking layer 3642 deposited on the top surface of sacrificial layer 3641 as illustrated in
Then, methods directionally etch sacrificial layer 3641 to form an opening of dimension DOPEN-1′ in the Y direction through sacrificial layer 3641 stopping at the surface of contact layer 3640 using known industry methods as illustrated in
Next, methods deposit a conformal sacrificial layer 3643 as illustrated in
Next, methods directionally etch conformal sacrificial layer 3643 using reactive ion etch (RIE) for example, using known industry methods, forming opening 3644 of dimension DOPEN-2′ and sacrificial regions 3643′ and 3643″, both having vertical sidewalls self-aligned and separated from inner vertical sidewall of sacrificial regions 3641′ and 3641″, respectively, by a distance R in the Y direction as illustrated in
Next, methods directionally etch an opening through contact layer 3640 to the top surface of insulator layer 3635. Directional etching using RIE, for example, forms an opening of size DOPEN-2′ of approximately 2F (130 nm in this example) in contact layer 3640, and forms sidewall contact regions 3640′ and 3640″ as illustrated in
Next, methods directionally etch an opening through insulator layer 3635 to the top surface of contact layer 3630. Directional etching using RIE, for example, forms an opening 3644′ of size DOPEN-2′ of approximately 2F (130 nm in this example) in insulator layer 3635, and forms insulator regions 3635′ and 3635″ as illustrated in
Next, methods deposit conformal nanotube element 3645 with vertical (Z) orientation on the sidewalls of opening 3644′ as illustrated in
Since nanotube element 3645 is in contact with contact layer 3630 and the sidewalls of sidewall contact regions 3640′ and 3640″, separated by the thickness of insulator region 3635′ and 3635″, respectively, two nonvolatile nanotube switch channel regions are partially formed (channel width is not yet defined) having channel length LSW-CH in the Z direction corresponding to the thickness of insulator regions 3635′ and 3635″ in the range of 5 nm to 250 nm as illustrated in
Next methods deposit conformal insulator layer 3650 on nanotube element 3645 as an insulating and protective layer and reduces opening 3644′ to opening 3651 as illustrated in
At this point in the process, it is desirable to partially fill opening 3651 by increasing the thickness of the bottom portion of insulator 3650 in the vertical (Z direction) on horizontal surfaces with little or no thickness increase on the sidewalls (vertical surfaces) of insulator 3650 as described above. The thickness of the additional dielectric material is not critical. The additional dielectric material may be the same as that of conformal insulator 3650 or may be a different dielectric material. Dielectric material selection with respect to nanotube elements is described in greater detail in U.S. patent application Ser. No. 11/280,786.
Next, methods directionally deposit an insulator material in opening 3651 using known industry methods such as directional HDP insulator deposition and increase insulator thickness primarily on horizontal surfaces as illustrated by insulator 3650′ in opening 3651 and on top surfaces in
Next, methods deposit and planarize an insulator 3652 such as TEOS filling opening 3651′ as illustrated in
Next, methods planarize the structure illustrated in
Next, methods etch (remove) sacrificial regions 3643′ and 3643″ and insulator 3652′. Exposed vertical sidewalls of nanotube element 3645′ and conformal insulator 3650″ remain as illustrated in
Next, methods etch (remove) the exposed portion of nanotube element 3645′ forming nanotube element 3645″ as illustrated in
Then, methods such as isotropic etch remove exposed portions of insulator 3650′ to form insulator 3650′″ as illustrated in
At this point in the process, sidewall spacer methods are applied as illustrated further below to form self aligned sacrificial regions to be replaced further along in the fabrication process as illustrated further below by a conductor material to form the upper portion of nanotube element contacts and also to define self aligned trench regions to be used to define self-aligned cell dimensions along the Y direction as also illustrated further below. Using sidewall spacer methods to form self aligned structures without requiring masking and alignment can result in cell areas of reduced size.
In this example, with respect to
Next, methods directionally etch conformal sacrificial layer 3655 using reactive ion etch (RIE) for example, using known industry methods, forming opening 3651″ of dimension approximately F, which in this example is approximately 65 nm as illustrated in
Next, methods deposit and planarized a sacrificial layer to form sacrificial region 3656 coplanar with sacrificial regions 3655′, 3655″, 3641′, and 3641″ as illustrated in
Next, methods apply CMP etching to reduce the thickness of sacrificial region 3656 to form sacrificial region 3658; the thickness of sacrificial regions 3655′ and 3655″ to form sacrificial regions 3655-1 and 3655-2, respectively; and the thickness of sacrificial regions 3641′ and 3641″ to form sacrificial regions 3658′ and 3658″, respectively as illustrated in
At this point in the process, sacrificial regions 3655-1 and 3655-2 may be used as masking layers for directional etching of trenches using methods that define outer cell dimensions along the Y direction for 3D cells using one NV NT diode with cathode-to-nanotube connection. Trench 3659 is formed first and then filled with an insulator and planarized. Then, trenches 3659′, and 3659″ are formed simultaneously and then filled and planarized as illustrated further below. Other corresponding trenches (not shown) are also etched when forming the memory array structure. Exemplary method steps that may be used to form trench regions 3659, 3659′, and 3659″ and then fill the trenches to form insulating trench regions are described further below.
Sacrificial regions 3658′ and 3658″ that define the location of trench regions 3659′ and 3659″ that are formed as described further below may be blocked with a sacrificial noncritical masking layer (not shown), while methods form trench 3659 using known directional selective etch methods such as reactive ion etch (RIE). Trench 3659 forms a first of two opposite vertical sidewalls in the Y direction defining one side of NV NT diode cells. Alternatively, sacrificial region 3658 that defines the location of trench region 3659 that is formed further below may be etched selective to sacrificial regions 3658′ and 3658″ without requiring a noncritical masking layer.
First, methods directionally selectively etch (remove) exposed regions (portions) of sacrificial region 3658 using known industry methods as illustrated in
Next, methods selectively etch exposed regions (portions) of conformal insulator 3650′″ using known industry methods and form conformal insulators 3650-1 and 3650-2 as illustrated in
Next, methods selectively etch exposed regions of nanotube element 3645″ and form nanotube elements 3645-1 and 3645-2 as illustrated in
Next, methods selectively etch exposed regions of contact layer 3630 using known industry methods forming contact layer regions 3630′ and 3630″.
Next, methods selectively etch exposed regions of N polysilicon layer 3625 forming regions 3625′ and 3625″ using known industry methods.
Next, methods selectively etch exposed regions of N+ polysilicon layer 3620 forming regions 3620′ and 3620″ using known industry methods.
Then, methods etch exposed regions of conductor layer 3610 using known industry methods forming conductor regions 3610′ and 3610″. Directional etching stops at the surface of planar insulator 3603.
Next, methods fill and planarize trench 3659 with an insulator such as TEOS for example and forming insulator 3660 using known industry methods as illustrated in
Next, methods form a noncritical mask region (not shown) over insulator 3660.
Next, sacrificial regions 3658′ and 3658″ are selectively etched as illustrated in
To form trenches 3659′ and 3659″, methods directionally selectively etch (remove) exposed portions of contact 3640′ and 3640″ using known industry methods and expose a portion of the top surface of insulator layers 3635′ and 3635″ and define contact 3640-1 and 3640-2 regions as illustrated in
Next, methods selectively etch exposed portions of insulator regions 3635′ and 3635″ using known industry methods and form insulator regions 3635-1 and 3635-2.
Next, methods selectively etch exposed portions of contact regions 3630′ and 3630″ using know industry methods and form contact regions 3630-1 and 3630-2.
Next, methods selectively etch exposed portions of N polysilicon layer 3625′ and 3625″ using known industry methods and form N polysilicon regions 3625-1 and 3625-2.
Next, methods selectively etch exposed portions of N+ polysilicon layer 3620′ and 3620″ using known industry methods and form N+ polysilicon regions 3620-1 and 3620-2 as illustrated in
Then, methods selectively etch exposed portions of conductor layer 3410′ and 3410″ using known industry methods and form word lines 3610-1 (WL0) and 3610-2 (WL1). Directional etching stops at the surface of planar insulator 3603 as illustrated in
Next, methods deposit and planarize an insulator such as TEOS and fill trench openings 3659′ and 3659″ with insulators 3660′ and 3660″, respectively, as illustrated in
Next, methods etch (remove) sacrificial regions 3655-1 and 3655-2.
Next, methods deposit and planarize conductor 3665′ to form upper layer contacts 3665-1 and 3665-2 as illustrated in FIGS. 36Z and 36AA and 36CC.
Next, methods deposit and planarize conductive layer 3671 using known industry methods to form cross section 3670 as illustrated in FIG. 36BB. Cross section 3670 corresponds to cross section 3100 illustrated in
At this point in the process, cross section 3670 illustrated in FIG. 36BB has been fabricated, and includes NV NT diode cell dimensions of 1F (where F is a minimum feature size) defined in the Y direction as well as corresponding array bit lines. Next, cell dimensions used to define dimensions in the X direction are formed by directional trench etch processes similar to those described further above with respect to cross section 3670 illustrated in FIG. 36BB. Trenches used to define dimensions in the X direction are approximately orthogonal to trenches used to define dimensions in the Y direction. In this example, cell characteristics in the X direction do not require self alignment techniques described further above with respect to Y direction dimensions. Cross sections of structures in the X direction are illustrated with respect to cross section B-B′ illustrated in FIG. 36BB.
Next, methods deposit and pattern a masking layer such as masking layer 3673 on the surface of bit line conductor layer 3671 as illustrated in FIG. 36CC. Masking layer 3673 may be non-critically aligned to alignment marks in planar insulator 3603. Openings 3674, 3674′, and 3674″ in mask layer 3673 determine the location of trench directional etch regions, in this case trenches are approximately orthogonal to bit lines such as word line 3410-1 (WL0).
Next, methods form trenches 3675, 3675′, and 3675″ corresponding to openings 3674, 3674′, and 3674″, respectively, in masking layer 3673. Trenches 3675, 3675′, and 3675″ form two sides of vertical sidewalls in the X direction defining two opposing sides of NV NT diode cells as illustrated in FIG. 36DD.
Methods directionally selectively etch (remove) exposed portions of bit line conductive layer 3671 illustrated in FIG. 36DD using known industry methods to form bit lines 3671-1 (BL0) and 3671-2 (BL1) illustrated in FIG. 36DD.
Next, methods selectively etch exposed portions of contact regions 3665-1 and 3665-2 illustrated in FIG. 36CC using known industry methods to form contacts 3665-1′ and 3665-1″ as illustrated in FIG. 36DD.
Next, methods selectively etch exposed portions of contact regions 3640-1 and 3640-2, nanotube elements 3645-1 and 3645-2, and conformal insulators 3650-1 and 3650-2 illustrated in FIG. 36BB using known industry methods to form contacts 3640-1′ and 3640-1″, conformal insulator regions (not shown in FIG. 36DD cross section B-B′), and nanotube elements 3645-1′ and 3645-1″ as illustrated in FIG. 36DD.
Next, methods selectively etch exposed regions of insulators 3635-1 and 3635-2 using known industry methods to form insulator regions 3635-1′ and 3635-1″ illustrated in FIG. 36DD.
Next, methods selectively etch exposed portions of contact regions 3630-1 and 3630-2 illustrated in FIGS. 36BB and 36CC using known industry methods and form contacts 3630-1′ and 3630-1″ illustrated in FIG. 36DD (cross section B-B′)
Next, methods selectively etch exposed portions of N polysilicon regions 3625-1 and 3625-2 illustrated in FIG. 36BB using known industry methods and form N polysilicon regions 3625-1′ and 3625-1″ illustrated in FIG. 36DD (cross section B-B′).
Next, methods selectively etch exposed portions of N+ polysilicon regions 3620-1 and 3620-2 illustrated in FIG. 36BB using known industry methods and form N+ polysilicon regions 3620-1′ and 3620-1″ illustrated in FIG. 36DD (cross section B-B′). Directional etching stops at the surface of word line 3610-1 (WL0).
Next, methods deposit insulator 3676 using known industry methods as illustrated in FIG. 36EE. Insulator 3676 may be TEOS, for example.
Then, methods planarize insulator 3676 to form insulator 3676′ using known industry methods and form cross section 3670′ illustrated in FIG. 36FF. Cross section 3670′ illustrated in FIG. 36FF and cross section 3670 illustrated in FIG. 36BB are two cross sectional representation of the same embodiment of a passivated NV NT diode vertically oriented cell. Cross section 3670 illustrated in FIG. 36BB corresponds to cross section 3100 illustrated in
At this point in the process, cross sections 3670 and 3670′ illustrated in FIGS. 36BB and 36FF, respectively, have been fabricated, nonvolatile nanotube element vertically-oriented channel length LSW-CH and horizontally-oriented channel width WSW-CH are defined, including overall NV NT diode cell dimensions of 1F in the Y direction and 1F in the X direction, as well as corresponding bit and word array lines. Cross section 3670 is a cross section of two adjacent vertically oriented anode-to-nanotube type nonvolatile nanotube diode-based cells in the Y direction and cross section 3670′ is a cross section of two adjacent vertically oriented anode-to-nanotube type nonvolatile nanotube diode-based cells in the cells in the X direction. Cross sections 3670 and 3670′ include corresponding word line and bit line array lines. The nonvolatile nanotube diodes form the steering and storage elements in each cell illustrated in cross sections 3670 and 3670′ and each occupy a 1F by 1F area. The spacing between adjacent cells is 1F so the cell periodicity is 2F in both the X and Y directions. Therefore one bit occupies an area of 4F2. At the 65 nm technology node, the cell area is less than 0.02 um2.
Methods of Fabricating Nonvolatile Memories using NV NT Diode Device Stacks with both Anode-to-NT Switch Connections and Cathode-to-NT Switch Connections
Some embodiments of methods of fabricating stacked memory arrays are shown in methods 3200 illustrated in
Next, cathode-on-nanotube methods of fabrication to form lower array 3310 illustrated
Next, anode-on-nanotube methods of fabrication to form upper array 3320 illustrated in
Nonvolatile 3D Memories using Vertically-Oriented Nonvolatile Nanotube Switches having Nanotube Elements of Varying Configurations for Enhanced Performance and Density
Vertically-oriented cathode-to-NT and anode-to-NT nonvolatile nanotube diode-based 3D structures described further above illustrate a thin nanotube element, where these thin nanotube elements are typically less than 10 nm thick (1-5 nm, for example), and thin relative to horizontal dimensions of the nonvolatile nanotube diode cell boundaries. Cathode-to-nanotube nonvolatile nanotube diode examples are illustrated in cross section 2800 in
Structural (geometrical) details described further below illustrate various options for nonvolatile nanotube switches. Nonvolatile nanotube switches of various thicknesses may be formed within isolation trench-defined cell boundaries using nanotube elements of varying thickness in order to optimized nonvolatile nanotube switch properties as illustrated further below with respect to
Nonvolatile nanotube switches of various thicknesses may also be formed within isolation trench regions, outside isolation trench-defined cell boundaries, using nanotube elements of varying thickness as illustrated further below with respect to
Nonvolatile nanotube switches of various thicknesses may also be formed both within isolation trench-defined cell boundaries and within isolation trench regions as illustrated further below with respect to
Twice (2×) the storage density may be achieved without stacking arrays, as described further above with respect to
Nonvolatile 3D Memories using Vertically-Oriented Nonvolatile Nanotube Switches having Nanotube Elements of Varying a Thicknesses
Cross section 3700 illustrated in
For cell 1 formed using diode D1-1, array line 3710 illustrated in cross section 3700 corresponds to array bit line 2810-1 shown in cross section 2800 illustrated in
For cell 1 formed using diode D1-2, array line 3710 illustrated in cross section 3700 corresponds to array word line 3110-1 shown in cross section 3100 illustrated in
Networks of nanotubes forming relatively thin nanotube (nanofabric) layers and corresponding nanotube elements typically have a nanotube density of approximately 500 nanotubes per square micrometer (um2). Nanotube layers and corresponding nanotube element typically include voids, regions between nanotubes. Void areas may be relatively large, greater than 0.0192 um2 for example, or may be relatively small, less than 0.0192 um2 for example. As cell dimensions are reduced, nanotube density is increased with a corresponding decrease in void area and an increase in nanotube layer and corresponding nanotube element thickness.
For a technology node (generation) with F approximately 45 nm and a nanotube element thickness of approximately 10 nm for example, the location R of a vertical sidewall may be at approximately F/2 or approximately 22 nm as illustrated by nanotube element 3745 of nonvolatile nanotube switch 3705 in cross section 3700 illustrated in
Nonvolatile 3D Memories using Vertically-Oriented Nonvolatile Nanotube Switches having Nanotube Elements within Trench Isolation Regions
First, methods fill trench opening 4205 with an insulator 4225, TEOS for example as illustrated in
Next, methods selectively etch insulator 4225 using a selective and controlled RIE etch to a depth D1 from a surface reference as illustrated in
Next, methods deposit conformal nanotube layer 4235 using methods described in greater detail in the incorporated patent references. At this point in the process, channel length LSW-CH is defined as illustrated in
Then, methods deposit a protective conformal insulator layer 4240 as illustrated in
Next, methods directly etch conformal insulator 4240 and nanotube layer 4235 using RIE and remove conformal layer material on top horizontal surfaces and bottom horizontal surfaces at the bottom of trench opening 4241, leaving partially completed vertical elements 4240′, 4240″, 4235′, and 4235″ as illustrated in
Next methods fill trench opening 4241 with insulator 4242 such as TEOS for example as illustrated in
Next, methods selectively etch insulator 4242, conformal insulators 4240′ and 4240″, and nanotube elements 4235′ and 4235″ using a selective and controlled RIE etch to a depth D2 from a surface reference as illustrated in
Then, methods fill trench opening 4255 with an insulator such as TEOS and methods planarize to form insulator 4260. At this point in the process cross section 4275 is formed, including nanotube channel elements 4270 and 4270′. Nanotube channel element 4270 includes nanotube element 4245 and conformal insulator 4250, and nanotube channel element 4270′ includes nanotube element 4245′ and conformal insulator 4250′. Nanotube channel elements 4270 and 4270′ are in contact with a portion of vertical sidewalls of an upper level contact and a lower level contact, and are also in contact with an insulating layer that defines LSW-CH. For example, nanotube channel element 4270 is in contact with upper level contact 4220, lower level contact 4210, and insulator 4215, and nanotube channel element 4270′ is in contact with upper level contact 4220′, lower contact 4210′, and insulator 4215′.
Nantotube channel elements 4270 and 4270′ may be used instead of nanotube element 3745 illustrated in
Non volatile 3D Memories using Vertically-Oriented Nonvolatile Nanotube Switches having Nanotube Elements Stacked Above Steering (Select) Diodes and within Trench Isolation Regions
Nanotube elements included in nonvolatile nanotube switches may be incorporated within cell boundaries defined by isolation trenches as described further above with respect to
Nanotube elements included in nonvolatile nanotube switches may be incorporated within cell boundaries defined by isolation trenches as described further above with respect to
Nonvolatile 3D Memories Storing Two Bits per Cell using Two Vertically-Oriented Nonvolatile Nanotube Switches Sharing a Single Steering (Select) Diode
Memory array cross section 4500 illustrated in
Nanotube channel element 4570-1 is formed within trench A and is similar to nanotube channel element 4370-3 illustrated in
Nanotube channel element 4570-2 is formed within trench B. Nanotube element 4545-2 is in contact with shared lower level contact 4530 and upper level contact 4565-2. Upper level contact 4565-2 is in contact with via 4567 which is in contact with bit line BL0-B. Nanotube element 4545-2 may also store information via its resistance state.
Cell 1 includes nonvolatile nanotube switch 4505-1 storing one bit, for example, and nonvolatile nanotube switch 4505-2 also storing one bit, for example such that cell 1 stores two bits, for example. Cross section 4500 illustrated in
Memory array cross section 4600 illustrated in
Nanotube channel element 4670-1 is formed within trench A and is similar to nanotube channel element 4470 illustrated in
Nanotube element 4645-2 is part of nonvolatile nanotube switch 4605-2 which is formed inside cell 1 boundaries as described further above with respect to nonvolatile nanotube 4468 illustrated in
Cell 1 includes nonvolatile nanotube switch 4605-1 storing one bit, for example, and nonvolatile nanotube switch 4605-2 also storing one bit, for example, such that cell 1 stores two bits, for example. Cross section 4600 illustrated in
Nonvolatile 3D Memory using Horizontally-Oriented Self-Aligned End-Contacted Nanotube Elements Stacked Above Steering (Select) Diodes
Cross section 4785 illustrated in
3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Horizontally Oriented Self Aligned NT Switches using Conductor Trench-Fill for Cathode-on-NT Switch Connections
Methods 2710 described further above with respect to
Next, methods 2730 illustrated in
Methods 2740 illustrated in
Vertically-oriented (Z direction) trench sidewall cell wiring on a first cell sidewall connects a vertically-oriented diode and one end of a horizontally-oriented nanotube element; and vertically-oriented trench sidewall cell wiring on a second cell sidewall connects the other end of the horizontally-oriented nanotube element with array wiring. Exemplary methods of forming vertically-oriented trench sidewall cell wiring may be adapted from methods of patterning shapes on trench sidewalls such as methods disclosed in U.S. Pat. No. 5,096,849, the entire contents of which are incorporated herein by reference. Horizontally-oriented NV NT switch element (nanotube element) dimensions in the X and Y direction are defined by trench etching. There are no alignment requirements for the nanotube elements in the X or Y direction. Nanotube element thickness (Z direction) is typically in the 5 to 40 nm range. However, nanotube element thickness may be any desired thickness, less than 5 nm or greater than 40 nm for example.
Horizontally-oriented nanotube elements may be formed using a single nanotube layer, or may be formed using multiple layers. Such nanotube element layers may be deposited e.g., using spin-on coating techniques or spray-on coating techniques, as described in greater detail in the incorporated patent references.
Methods fill trenches with an insulator; and then methods planarize the surface. Then, methods deposit and pattern word lines on the planarized surface.
The fabrication of vertically-oriented 3D cells illustrated in
The electrical characteristics of Schottky (and PN, PIN) diodes may be improved (low leakage, for example) by controlling the material properties of polysilicon, for example polysilicon deposited and patterned to form polysilicon regions 3420-1 and 3420-2. Polysilicon regions may have relatively large or relatively small grain boundary sizes that are determined by methods used in the semiconductor regions. For example, SOI deposition methods used in the semiconductor industry may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline, for further electrical property enhancement such as low diode leakage currents.
Examples of contact and conductors materials include elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix. Insulators may be SiO2, SiNx, Al2O3, BeO, polyimide, Mylar or other suitable insulating material.
In some cases conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as both contact and conductors materials as well as anodes for Schottky Diodes. However, in other cases, optimizing anode material for lower forward voltage drop and lower diode leakage is advantageous. Schottky diode anode materials may be added (not shown) between conductors 3410-1 and 3410-2 and polysilicon regions 3420-1 and 3420-2, respectively. Such anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn and other elemental metals. Also, silicides such as CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2, and ZrSi2 may be used. Schottky diodes formed using such metals and silicides are illustrated in the reference by NG, K. K. “Complete Guide to Semiconductor Devices”, Second Edition, John Wiley and Sons, 2002m pp. 31-41, the entire contents of which are incorporated herein by reference.
Next, having completed Schottky diode select devices, methods form N+ polysilicon regions 3425-1 and 3425-2 to contact N polysilicon regions 3420-1 and 3420-2, respectively, and also to form contact regions for ohmic contacts to contacts 3430-1 and 3430-2. N+ polysilicon is typically doped with arsenic or phosphorous to 1020 dopant atoms/cm3, for example, and has a thickness of 20 to 400 nm, for example. N and N+ polysilicon region dimensions are defined by trench etching near the end of the process flow.
Next, methods form planar insulating regions 4735-1 and 4735-2 on the surface of lower level contact (contact) 3430-1 and 3430-2, respectively, typically SiO2 for example, with a thickness of 20 to 500 nm for example and X and Y dimensions defined by trench etching near the end of the process flow.
Next, methods form horizontally-oriented nanotube elements 4740-1 and 4740-2 on the surface of insulator regions 4735-1 and 4735-2, respectively, having nanotube element length and width defined by trench etching near the end of the process flow and insulated from direct contact with lower level contacts 3430-1 and 3430-2, respectively. In order to improve the density of cells C00 and C01, nanotube elements 4740-1 and 4740-2 illustrated in
Then, methods form protective insulators 4745-1 and 4745-2 on the surface of conformal nanotube elements 4740-1 and 4740-2, respectively, with X and Y dimensions defined by trench etching near the end of the process flow. Exemplary methods of forming protective insulator 4745-1 and 4745-2 are described further below with respect to
Next, methods form upper level contacts 4750-1 and 4750-2 on the surface of protective insulators 4745-1 and 4745-2, respectively, with X and Y dimensions defined by trench etching near the end of the process flow.
Next, methods form (etch) trench openings of width F form inner sidewalls of cells COO and C01 and corresponding upper and lower level contacts, nanotube elements, and insulators described further above.
Next, methods form sidewall vertical wiring 4762 and 4762′. Vertical sidewall wiring 4762 forms and connects end-contact 4764 of nanotube element 4740-1 with end-contact 4766 of lower level contact 3430-1; vertical sidewall wiring 4762′ forms and connects end-contact 4764′ of nanotube element 4740-2 with end-contact 4766′ of lower level contact 3430-2.
Next, methods complete trench formation (etching) to the surface of insulator 3403.
Next, methods fill trench opening with an insulator such as TEOS and planarize the surface to complete trench fill 4769.
Next, methods form (etch) trench openings of width F that form outer sidewalls of cells C00 and C01 and corresponding upper and lower level contacts, nanotube elements, and insulators described further above.
Next, methods form sidewall vertical wiring 4776 and 4776′. Vertical sidewall wiring 4776 forms and connects end-contact 4778 of nanotube element 4740-1 with the end-contact region of upper level contact 4750-1; vertical sidewall wiring 4776′ forms and connects end-contact 4778′ of nanotube element 4740-2 with the end-contact region of upper level contact 4850-2.
Next, methods complete trench formation (etching) to the surface of insulator 3403.
Next, methods fill trench openings with an insulator such as TEOS and planarize the surface to complete trench fill 4882 and 4882′.
Next, methods directionally etch and form word line contacts 4784C-1 and 4784C-2 on the surface of upper level contacts 4750-1 and 4750-2, respectively, by depositing and planarizing a word line layer.
Next, methods pattern word line 4784.
Nonvolatile nanotube diodes forming cells C00 and C01 correspond to nonvolatile nanotube diode 1200 in
Methods 2700 illustrated in
Methods of Fabricating 3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Horizontally-Oriented Self Aligned NT Switches Using Conductive Trench-Fill for Cathode-to-NT Switch Connection
Methods 2710 illustrated in
Methods of fabrication for elements and structures for support circuits and interconnections 3401, insulator 3403, memory array support structure 3405, conductor layer 3410, N polysilicon layer 3420, N+ polysilicon layer 3425, and lower level contact layer 3430 illustrated in
Next, methods of fabrication deposit insulator layer 4835 as illustrated in
Next, methods deposit a horizontally-oriented nanotube layer 4840 on the planar surface of insulator layer 4835 as illustrated in
Next, methods form protective insulator layer 4845 on the surface on nanotube layer 4840 as illustrated in
At this point in the fabrication process, methods deposit upper level contact layer 4850 on the surface of insulator layer 4845 as illustrated in
Next methods deposit sacrificial layer 4852 (sacrificial layer 1) on upper level contact layer 4850 as illustrated in
Next, methods deposit and pattern a masking layer (not shown) deposited on the top surface of sacrificial layer 4852 using known industry methods. The mask opening may be aligned to alignment marks in planar insulating layer 3403 for example; the alignment is not critical.
Then, methods directionally etch sacrificial layer 4852 to form an opening of dimension DX1 through sacrificial layer 4852 stopping at the surface of upper level contact layer 4850 using known industry methods as illustrated in
Next, methods deposit a second conformal sacrificial layer 4853 (sacrificial layer 2) as illustrated in
Next, methods directionally etch conformal sacrificial layer 4853 using reactive ion etch (RIE) for example, using known industry methods, forming opening 4855 of dimension approximately F, which in this example may be in a range of 22 to 45 nm as illustrated in
At this point in the process, sacrificial regions 4853′ and 4853″ may be used as masking layers for directional etching of trenches using methods that define a cell boundary along the X direction for 3D cells using one NV NT diode with an internal cathode-to-nanotube connection per cell. U.S. Pat. No. 5,670,803, the entire contents of which are incorporated herein by reference, to co-inventor Bertin, discloses a 3-D array (in this example, 3D-SRAM) structure with simultaneously trench-defined sidewall dimensions. This structure includes vertical sidewalls simultaneously defined by trenches cutting through multiple layers of doped silicon and insulated regions in order avoid multiple alignment steps. Such trench directional selective etch methods may cut through multiple conductor, semiconductor, and oxide layers as described further above with respect to trench formation in FIGS. 34A-34FF and 36A-36FF. In this example, selective directional trench etch (RIE) removes exposed areas of upper level contact layer 4850 to form upper level contact regions 4850′ and 4850″; removes exposed areas of protective insulator layer 4845 to form protective insulator regions 4845′ and 4845″; removes exposed areas of nanotube layer 4840 to form nanotube regions 4840′ and 4840″; removes exposed areas of insulating layer 4835 to form insulating regions 4835′ and 4835″; removes exposed areas of lower level contact layer 3430 to form lower level contact regions 3430′ and 3430″; and selective directional etch stops on the top surface of N+ polysilicon layer 3425, forming trench opening 4857 as illustrated in
Next, methods such as evaporation or sputtering fill trench 4857 with conductor material 4858 as illustrated in
Next, methods selectively directionally etch conductor 4858 to a depth DZ1 below the top surface of sacrificial cap 2 regions 4853′ and 4853″ as illustrated in
Next, methods deposit a conformal insulator layer 4860 as illustrated in
Next, methods directly etch conformal insulator 4860 using RIE and remove conformal layer material on top horizontal surfaces and bottom horizontal surfaces at the bottom of trench opening to form trench opening 4861 with sidewall insulators 4860′ and 4860″ and conductor 4858′ as illustrated in
Next, methods directionally etch conductor 4858′ using sidewall insulators 4860′ and 4860″ as masking regions and stop at the top surface of N+ polysilicon layer 3425 as illustrated in
Next, methods directionally etch exposed areas of N+ polysilicon layer 3425 to form N+ polysilicon regions 3425′ and 3425″; exposed areas of polysilicon layer 3420 to form N polysilicon regions 3420′ and 3420″; and exposed areas of conductor layer 3410 to form conductor regions 3410′ and 3410″, stopping at the surface of insulator 3403. Sidewall insulators 4860′ and 4860″ and trench sidewall conductors 4862 and 4862′ are used for masking. Directional etching stops at the top surface of insulator 3403 forming trench opening 4867′ as illustrated in
Next methods fill trench opening 4867′ with insulator 4869 such as TEOS for example and planarize as illustrated in
At this point in the process, a second cell boundary is formed along the X direction for 3D memory cells. Methods remove (etch) sacrificial cap layer 1 regions 4852′ and 4852″ exposing a portion of the surfaces of upper level contact region 4850′ and 4850″ as illustrated in
At this point in the process, sacrificial regions 4853′ and 4853″ may be used as masking layers for directional etching of trenches using methods that define another cell boundary along the X direction for 3D cells using one NV NT diode with an internal cathode-to-nanotube connection per cell as described further above with respect to
Next, methods such as evaporation or sputtering fill trenches 4871 and 4871′ with conductor material 4872 as illustrated in
Next, methods selectively directionally etch conductor 4872 to a depth DZ2 below the top surface of sacrificial cap 2 regions 4853′ and 4853″ as illustrated in
Next, methods deposit a conformal insulator layer 4874 as illustrated in
Next, methods directly etch conformal insulator 4874 using RIE and remove conformal layer material on top horizontal surfaces and bottom horizontal surfaces at the bottom of trench opening to form trench openings with sidewall insulators 4874′ and 4874″ and conductors 4872′ and 4872″ as illustrated in
Next, methods directionally etch conductors 4872′ and 4872″ using sidewall insulators 4874′ and 4874″, respectively, and corresponding insulators on other sides of trenches 4880A and 4880B, respectively, (not shown) as masking regions and stop at the top surface of insulator regions 4835′ and 4835″, respectively, as illustrated in
Next, methods directionally etch exposed areas of insulator regions 4835′ and 4835″ to form insulators 4835-1 and 4835-2, respectively; lower level contact regions 3430′ and 3430″ to form lower level contacts 3430-1 and 3430-2, respectively; N+ polysilicon regions 3425′ and 3425″ to form N+ polysilicon regions 3425-1 and 3425-2, respectively; exposed areas of polysilicon regions 3420′ and 3420″ to form N polysilicon regions 3420-1 and 3420-2; and exposed areas of conductor regions 3410′ and 3410″ to form conductors 3410-1 and 3410-2, respectively, stopping at the surface of insulator 3403. Sidewall insulators 4874′ and 4874″ and trench sidewall conductors 4876 and 4876′ are used for masking. Directional etching stops at the top surface of insulator 3403 forming trench openings 4880A′ and 4880B′ as illustrated in
Next methods fill trench openings 4880A′ and 4880B′ with insulator 4882 such as TEOS for example and planarize as illustrated in
Next, methods remove (etch) sacrificial cap 2 regions 4853′ and 4853″ to form openings 4883 and 4883′, respectively, exposing the top surfaces of upper level contacts 5850-1 and 5850-2, respectively, as illustrated in
Next, methods deposit and planarize a conductor layer 4884 that also forms contacts 4884C-1 and 4884C-2 that contact upper level contacts 4850-1 and 4850-2, respectively, as illustrated in
Next, conductor layer 4884 is patterned to form word lines orthogonal to conductors (bit lines) 3410-1 and 3410-2 as illustrated further below.
At this point in the process, cross section 4885 illustrated in
Next, methods deposit and pattern a masking layer such as masking layer 4884A on the surface of word line layer 4884 as illustrated in
At this point in the process, openings in masking layer 4884A may be used for directional etching of trenches using methods that define new cell boundaries along the Y direction for 3D cells using one NV NT diode with an internal cathode-to-nanotube connection per cell. All trenches and corresponding cell boundaries may be formed simultaneously. This structure includes vertical sidewalls simultaneously defined by trenches. Such trench directional selective etch methods may cut through multiple conductor, semiconductor, and oxide layers as described further below and also described further above with respect to trench formation in
Then methods fill trenches 4886 with an insulator 4888 such as TEOS, for example, and planarize the surface as illustrated by cross section 4885′ in FIG. 48BB. Cross section 4885′ illustrated in FIG. 48BB and cross section 4885 illustrated in
At this point in the process, cross sections 4885 and 4885′ illustrated in FIGS. 48Y and 48BB, respectively, have been fabricated, nonvolatile nanotube element horizontally-oriented channel length LSW-CH are defined, including overall NV NT diode cell dimensions of 1F in the X direction and 1F in the Y direction, as well as corresponding bit and word array lines. Cross section 4885 is a cross section of two adjacent cathode-to-nanotube type nonvolatile nanotube diode-based cells in the X direction and cross section 4885′ is a cross section of two adjacent cathode-to-nanotube type nonvolatile nanotube diode-based cells in the Y direction. Cross sections 4885 and 4885′ include corresponding word line and bit line array lines. The nonvolatile nanotube diodes form the steering and storage elements in each cell illustrated in cross sections 4885 and 4885′, and each cell having 1F by 1F dimensions. The spacing between adjacent cells is 1F so the cell periodicity is 2F in both the X and Y directions. Therefore one bit occupies an area of 4F2. At the 45 nm technology node, the cell area is less than 0.01 um2.
Nonvolatile Nanotube Switch with Channel-Region End-Contacted Nanotube Elements
Laboratory testing results of individual nonvolatile nanotube switch 4900 with nanotube element 4910 channel length of approximately 250 nm and terminals (conductive elements) 4940 and 4950 formed of TiPd are illustrated by graph 5000 in
If a 3D memory array is used in a nonvolatile Flash memory application, Flash architecture could be used to detect cases 5030 of ON resistance values that are greater than OFF resistance values 5010 and apply one or several additional cycles as needed to ensure ON resistance values of less than 1 MOhm as illustrated by graph 5000.
Nonvolatile nanotube switch 4900 ON/OFF resistance values demonstrate a lowering of the spread of ON resistance values and a tighter ON resistance value distribution after several tens (or hundreds) of cycles. Graphs 5010 and 5020 in the 80 to 100 ON/OFF cycle range show ON resistance values between 10 kOhms and less than 1 MOhms, for example, and OFF resistance values greater than 80 MOhms. Such nonvolatile nanotube switches may be used in any memory architecture. Applying tens or hundreds of cycles to as-fabricated nonvolatile nanotube switches 4900 may be used as part of a memory array burn-in operation. Examples of applied voltages and currents resulting in cycling between ON and OFF resistance values is described further above with respect to
3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Horizontally Oriented Self Aligned NT Switches using Conductor Trench-Fill for Anode-on-NT Switch Connections
Methods 3010 described further above with respect to
Next, methods 3030 illustrated in
Exemplary methods 3040 illustrated in
Vertically-oriented (Z direction) trench sidewall cell wiring on a first cell sidewall connects a vertically-oriented diode and one end of a horizontally-oriented nanotube element; and vertically-oriented trench sidewall cell wiring on a second cell sidewall connects the other end of the horizontally-oriented nanotube element with array wiring. Exemplary methods of forming vertically-oriented trench sidewall cell wiring may be adapted from methods of patterning shapes on trench sidewalls such as methods disclosed in U.S. Pat. No. 5,096,849. Horizontally-oriented NV NT switch element (nanotube element) dimensions in the X and Y direction are defined by trench etching. There are no alignment requirements for the nanotube elements in the X or Y direction. Nanotube element thickness (Z direction) is typically in the 5 to 40 nm range. However, nanotube element thickness may be any desired thickness, less than 5 nm or greater than 40 nm for example.
Horizontally-oriented nanotube elements may be formed using a single nanotube layer, or may be formed using multiple layers. Such nanotube element layers may be deposited e.g., using spin-on coating techniques or spray-on coating techniques, as described in greater detail in the incorporated patent references.
Methods fill trenches with an insulator; and then methods planarize the surface. Then, methods deposit and pattern bit lines on the planarized surface.
The fabrication of vertically-oriented 3D cells illustrated in
The electrical characteristics of Schottky (and PN, PIN) diodes may be improved (low leakage, for example) by controlling the material properties of polysilicon, for example polysilicon deposited and patterned to form polysilicon regions 3625-1 and 3625-2. Polysilicon regions may have relatively large or relatively small grain boundary sizes that are determined by methods used in the semiconductor regions. For example, SOI deposition methods used in the semiconductor industry may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline, for further electrical property enhancement such as low diode leakage currents.
Methods form lower level contacts 3630-1 and 3630-2. Examples of contact conductor materials include elemental metals such as Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix. Insulators may be SiO2, SiNx, Al2O3, BeO, polyimide, Mylar or other suitable insulating material.
Lower level contacts 3630-1 and 3630-2 also form anodes of Schottky diodes having Schottky diode junctions 3618-1 and 3618-2. In some cases conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as both contact conductor materials as well as anodes for Schottky Diodes. However, in other cases, optimizing anode material for lower forward voltage drop and lower diode leakage is advantageous. Schottky diode anode materials may be added (not shown) between lower level contacts (and Schottky diode anodes) 3630-1 and 3630-2 and polysilicon regions 3625-1 and 3625-2, respectively. Such anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Zn and other elemental metals. Also, silicides such as CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2, and ZrSi2 may be used. Schottky diodes formed using such metals and silicides are illustrated in the reference by NG, K. K. “Complete Guide to Semiconductor Devices”, Second Edition, John Wiley and Sons, 2002m pp. 31-41, the entire contents of which are incorporated herein by reference.
Next, methods form planar insulating regions 4735-1 and 4735-2 on the surface of lower level contact (contact) 3630-1 and 3630-2, respectively, typically SiO2 for example, with a thickness of 20 to 500 nm for example and X and Y dimensions defined by trench etching near the end of the process flow.
Next, methods form horizontally-oriented nanotube elements 4740-1 and 4740-2 on the surface of insulator regions 4735-1 and 4735-2, respectively, having nanotube element length and width defined by trench etching near the end of the process flow and insulated from direct contact with lower level contacts 3430-1 and 3430-2, respectively. In order to maximize the density of cells C00 and C10, nanotube elements 4740-1 and 4740-2 illustrated in
Then, methods form protective insulators 4745-1 and 4745-2 on the surface of conformal nanotube elements 4740-1 and 4740-2, respectively, with X and Y dimensions defined by trench etching near the end of the process flow. Exemplary methods of forming protective insulator 4745-1 and 4745-2 are described further above with respect to
Next, methods form upper level contacts 4750-1 and 4750-2 on the surface of protective insulators 4745-1 and 4745-2, respectively, with X and Y dimensions defined by trench etching near the end of the process flow.
Next, methods form (etch) trench openings of width F form inner sidewalls of cells C00 and C10 and corresponding upper and lower level contacts, nanotube elements, and insulators described further above.
Next, methods form sidewall vertical wiring 4762 and 4762′. Vertical sidewall wiring 4762 forms and connects end-contact 4764 of nanotube element 4740-1 with end-contact 4766 of lower level contact 3630-1; vertical sidewall wiring 4762′ forms and connects end-contact 4764′ of nanotube element 4740-2 with end-contact 4766′ of lower level contact 3630-2.
Next, methods complete trench formation (etching) to the surface of insulator 3403.
Next, methods fill trench opening with an insulator such as TEOS and planarize the surface to complete trench fill 4769.
Next, methods form (etch) trench openings of width F that form outer sidewalls of cells C00 and C10 and corresponding upper and lower level contacts, nanotube elements, and insulators described further above.
Next, methods form sidewall vertical wiring 4776 and 4776′. Vertical sidewall wiring 4776 forms and connects end-contact 4779 of nanotube element 4740-1 with the end-contact region 4778 of upper level contact 4750-1; vertical sidewall wiring 4776′ forms and connects end-contact 4779′ of nanotube element 4740-2 with the end-contact region 4778′ of upper level contact 4850-2.
Next, methods complete trench formation (etching) to the surface of insulator 3403.
Next, methods fill trench openings with an insulator such as TEOS and planarize the surface to complete trench fill 4882 and 4882′.
Next, methods directionally etch and form bit line contacts 5184C-1 and 5184C-2 on the surface of upper level contacts 4750-1 and 4750-2, respectively, by depositing and planarizing a bit line layer.
Next, methods pattern bit line 5184.
Nonvolatile nanotube diodes forming cells C00 and C10 correspond to nonvolatile nanotube diode 1300 in
After the fabrication of cross section 5185 illustrated in
Cross section 5185′ illustrated in
N+ polysilicon regions 3620-1′ and 3620-1″ form contacts between word line 3610-1 (WL0) and N polysilicon 3625-1′ and 3625-1″, respectively, that form diode cathode regions. Lower level contacts 3430-1′ and 3430-1″ act as anodes to form Schottky diode junctions 3618-1′ and 3618-1″ as well as contacts to nanotube elements 4840-1′ and 4840-1″, respectively. Contacts between nanotube elements and lower level contacts are illustrated in corresponding cross section 5185 in
Insulator 4835-1′ and 4835-1″ is used to separate nanotube elements 4840-1′ and 4840-1″ from electrical contact with lower level contacts 3630-1′ and 3630-1″, respectively.
Protective insulators 4845-1′ and 4845-1″ provide a protecting region above the nanotube elements, and also electrically separate nanotubes elements 4840-1′ and 4840-1″ from electrical contact with upper level contacts 4850-1′ and 4850-1″, respectively. Contacts between nanotube elements and upper level contacts are illustrated in corresponding cross sections 5185.
Bit line contacts 5184C-1′ and 5184C-1″ connect upper level contacts 4850-1′ and 4850-1″, respectively, to bit lines 5184-1 (BL0) and 5184-2 (BL1), respectively.
Corresponding cross sections 5185 and 5185′ illustrated in
Corresponding cross sections 5185 and 5185′ illustrated in
Nonvolatile Memories using NV NT Diode Device Stacks with both Anode-to-NT Switch Connections and Cathode-to-NT Switch Connections and Horizontally-Oriented Self Alighted End-Contacted NV NT Switches
In general, methods 3210 fabricate support circuits and interconnections in and on a semiconductor substrate. This includes NFET and PFET devices having drain, source, and gate that are interconnected to form memory (or logic) support circuits. Such structures and circuits may be formed using known techniques that are not described in this application. Some embodiments of methods 3210 are used to form a support circuits and interconnections 5401 layer as part of cross sections 5400 and 5400′ illustrated in
Next, methods 3210 are also used to fabricate an intermediate structure including a planarized insulator with interconnect means and nonvolatile nanotube array structures on the planarized insulator surface such as insulator 5403 illustrated in cross sections 5400 and 5400′ in
Next, methods 3220, similar to methods 2740, are used to fabricate a first memory array 5410 using diode cathode-to-nanotube switches based on a nonvolatile nanotube diode array similar to a nonvolatile nanotube diode array cross section 4785 illustrated in
Next, methods 3230 similar to methods 3040 illustrated in
The memory array cell area of 1 bit for array 5410 is 4F2 because of the 2F periodicity in the X and Y directions. The memory array cell area of 1 bit for array 5420 is 4F2 because of the 2F periodicity in the X and Y directions. Because memory arrays 5420 and 5410 are stacked, the memory array cell area per bit is 2F2. If four memory arrays (not shown) are stacked, then the memory array cell area per bit is 1F2.
In some embodiments, methods 3240 using industry standard fabrication techniques complete fabrication of the semiconductor chip by adding additional wiring layers as needed, and passivating the chip and adding package interconnect means.
In operation, memory cross section 5400 illustrated in
Method of Forming Trench Sidewall Wiring Using Conformal Conductor Deposition as an Alternative to Trench Fill
Conformal conductor deposition may be used instead of a trench fill conductor to create trench sidewall wiring as illustrated in
Some methods deposit a conformal conductor layer 5510 in opening 4857 (
Next, methods fill trench opening 5515 with sacrificial material 5520 as illustrated in
Next, methods etch (RIE) sacrificial material 5520 to a depth DZ10 below the bottom of upper level contacts 4850′ and 4850″ as illustrated in
Next, methods remove (etch) exposed regions of the conformal trench sidewall conductor using known industry methods as illustrated in
Next, methods remove (etch) remaining sacrificial material 5520′ using known industry methods as illustrated in
Next, methods RIE remaining conformal conductor forming trench sidewall wiring 5535 and 5535′. Then, methods directionally etch remaining semiconductor and metal layers to form trench sidewall wiring 5535 and 5535′ corresponding to sidewall wiring 4862 and 4862′ in
Methods of fabrication using conformal conductor deposition instead of conductor trench fill as described with respect to
Methods of fabrication using conformal conductor deposition as described with respect to
Nonvolatile Nanotube Blocks
Nonvolatile nanotube switches (NV NT Switches) are described in detail in U.S. patent application Ser. No. 11/280,786, and switch examples and operation are summarized briefly in this application as illustrated in
However, even with vertically-oriented nanotubes, scaling to small dimensions such as technology node F=22 nm (or smaller) may in some embodiments be limited by the nanotube fabric density of the nanotube element, that is the number of individual nanotubes available in the width direction of the device. Another way to express nanotube fabric density is to measure the size of void regions as illustrated in
Nonvolatile nanotube blocks (“NV NT blocks”) can be thought of as nanotube elements that include 3-D volumes of nanotube fabric. The term NV NT blocks is used to distinguish relatively thick nanotube elements from relatively thin nanotube elements, e.g., those illustrated in
In many embodiments, NV NT blocks are shaped, sized, and/or are sufficiently dense such that terminals may contact the blocks on any surface(s), including the bottom, top, side, and end, or in any combination of surfaces. The size and/or density of the fabric that forms the block substantially prevents the terminals from contacting each other through the fabric and shorting. In other words, the size and/or density of the fabric physically separates the terminals from one another. As discussed above relative to
In many embodiments, many of the nanotubes within the nanotube fabric forming the NV NT block lie substantially parallel to the surface on which they are disposed. In some embodiments, for example if the nanotubes are spin-coated onto a surface, at least some of the nanotubes may also generally extend laterally in a given direction, although their orientation is not constrained to that direction. If another layer of nanotubes is spin-coated on top of that layer, the nanotubes may generally extend in the same direction as the previous layer, or in a different direction. Additionally, while many the nanotubes of the additional layer will also be generally parallel to the surface, some of the nanotubes may curve downwards to fill voids in the previous nanotube layer. In other embodiments, for example if the nanotubes are spray-coated onto a surface, the nanotubes will still lie generally parallel to the surface on which they are disposed, although they may have generally random orientations relative to each other in the lateral direction. In other embodiments, the nanotubes may extend randomly in all directions.
In many embodiments, NV NT blocks have a thickness or height that is on the order of one or more of its lateral dimensions. For example, as described in greater detail below, one or more dimensions of the NV NT block can be defined lithographically, and one dimension defined by the as-deposited thickness of the nanotube fabric forming the NV NT block. The lithographically defined dimension(s) scale with the technology node (F), enabling the fabrication of devices with minimum lateral dimensions of approximately F. e.g., of about 65 nm for F=65 nm, of about 45 nm for F=45 nm, of about 32 nm for F=32 nm, of about 22 nm for F=22 nm, or below. For example, for F=22 nm, an NV NT block could have dimensions of about 22 nm×22 nm×35 nm, assuming that the nanotube fabric forming the NV NT block is about 35 nm thick. Other dimensions and thicknesses are possible. Depending on the arrangement of the terminals, and the thickness and as-deposited characteristics of the nanotube fabric forming the NV NT block, the distance between the terminals (i.e., the switch channel length) may be defined either by a lithographically defined dimension of the NV NT block. Alternately, the distance between the terminals may be defined by the thickness of the fabric forming the NV NT block, which in some circumstances may be sub-lithographic. Alternately, the switch channel length may be defined by providing the terminals in an arrangement that is not directly related to a dimension of the NV NT block itself, but rather by patterning the terminals to have features that are separated from each other by a particular distance. In general, as illustrated in greater detail below, NV NT blocks enable the fabrication of switching elements with areas at least down to about 1F2.
Note that a “NV NT block” need not be cube-shaped, e.g., a volume having all dimensions approximately equal, or even have parallel sides, although some embodiments will have those features. For example, in certain embodiments, shapes defined in masking layers at minimum dimensions may have rounded corners such that square shapes as-drawn may be approximately circular as-fabricated, or may be generally square but with rounded features. An approximately circular masking layer results in an approximately cylindrical nonvolatile nanotube element that is also referred to as a NV NT block in this invention. Therefore, nanotube element 4050 illustrated by cross section 4000 in
Individual NT-to-NT overlap regions are estimated to be between 0.5×0.5 nm to 10×10 nm in size, which is below available SEM resolution limitations.
In operation, as illustrated further above in
FIGS. 67 and 68A-68I illustrate structures and methods of fabricating the memory cell described further above with respect to cross section 4000 illustrated in
FIGS. 71 and 72A-72B illustrate 2-high stacked arrays of 3-D NV NT diode-based cells that include shared array lines such as shared word lines.
FIGS. 75 and 76A-76D illustrate 3-D NV NT diode-based structures and corresponding simplified methods of fabrication. Simplified methods of fabrication enable multi-level arrays of 4, 8, 16 and higher number of levels as illustrated in a perspective drawing illustrated in
NV NT Switches Fabricated with Nonvolatile Nanotube Blocks, Various Terminal Locations, and Switching Characteristics Thereof
NV NT switch 5600A illustrated in 3-D perspective drawing in
NV NT switch 5600B illustrated in 3-D perspective drawing in
NV NT switch 5600C illustrated in 3-D perspective drawing in
NV NT switch 5600D illustrated in 3-D perspective drawing in
NV NT switch 5600E illustrated in 3-D perspective drawing in
NV NT switch 5600F illustrated in 3-D perspective drawing in
NV NT switch 5700A illustrated in 3-D perspective drawing in
NV NT switch 5700A also corresponds to nanotube element 4050 illustrated in
Void regions sufficiently small in size and number as described further above with respect to nanotube layer 3800 illustrated in
NV NT Switches Fabricated with Nonvolatile Nanotube Block Dimensions Scaled to the Technology Node
Laboratory testing results of nonvolatile nanotube switch 5850 is illustrated by graph 5900 illustrated in
NV NT Switches Fabricated with Nonvolatile Nanotube Blocks with End Contacts
NV NT switch 6000/6000′ corresponds to NV NT switch 4900 described further above with respect to
Laboratory ON/OFF switching test results of nanotube switch 6050 with only end-region contacts corresponds to the electrical characteristics of NV NT switch 4900 described further above with respect to graph 5000 illustrated in
NV NT Switches Fabricated with Nonvolatile Nanotube Blocks with Bottom and End/Top Contacts
Laboratory ON/OFF switching test results of nanotube switch 6200/6200′ are described with respect to graph 6300 illustrated in
NV NT Switches Fabricated with Nonvolatile Nanotube Blocks with Top and Bottom Contacts
A graph 6500 of nonvolatile nanotube switch 6450 switching results for 100 ON/OFF cycles is illustrated in
NV NT switches using NV NT blocks as switching elements demonstrate ON/OFF switching for fabricated devices over a wide range of horizontal dimensions, e.g., from 22 nm to 300 nm and contacting schemes involving bottom, top, end, and side contacts in various combinations. NV NT blocks may be used in various integration schemes to form a large variety of three-dimensional nonvolatile nanotube diode-based memory arrays. For example, cross section 4000 illustrated in
The flexibility of NV NT blocks enables integration in a variety of structures and product applications. For example, NV NT switches formed using NV NT blocks may be used as scalable nonvolatile nanotube switches in structures and circuits, such as the structures and circuits described in U.S. Provisional Patent Application No. 60/836,343. Also, NV NT switches formed using NV NT blocks may be used in memory arrays, such as the memory arrays described in U.S. patent application Ser. Nos. 11/280,786 and 11/274,967. Also, NV NT switches formed using NV NT blocks may be used in non-volatile shadow latches to form register files used in logic circuits, such as the register files described in U.S. patent application Ser. No. 11/280,599. These scalable NV NT Switches formed using NV NT blocks may be used instead of stacked capacitors in DRAM cells to create a less complex scalable nonvolatile storage structure.
Methods of Fabrication of NV NT Switches using Nonvolatile Nanotube Blocks
Some embodiments of methods of depositing and patterning a CNT layer, or layers, of carbon nanotubes (CNTs) from CNT dispersion in aqueous or non-aqueous solutions that may be used to fabricate nonvolatile nantotube blocks are described in incorporated patent references. Examples of such NV NT blocks are illustrated in 3-D representations in
Some embodiments of methods of NV NT block fabrication may be extended to include deposition of a CNT layer, or layers, from CNT dispersions in a sacrificial polymer dissolved in an organic solvent as described with respect to methods 6600A of fabrication illustrated in
Some embodiments of methods of NV NT block fabrication may also be extended to include the addition of performance enhancing material such as a porous dielectric, for example, as described with respect to methods 6600B of fabrication illustrated in
Methods of fabrication of Nonvolatile Nanotube Blocks using a Sacrificial Polymer
Next, methods 6608 deposit a CNT layer, or layers, from CNT dispersions in a sacrificial polymer dissolved in an organic solvent. For example, sacrificial polymer polypropylene carbonate (PPC) dissolved in one or more organic solvents such as NMP or cyclohexanone available in the industry. A description of the properties of polypropylene carbonate may be found, for example, in referenced technical data available from the company Empower Materials, Inc. While sacrificial polymer PPC is used in this example, other sacrificial polymers such as Unity sacrificial polymer and polyethylene carbonate sacrificial polymer may also be used. At this point in the process, the CNT layer may be patterned continuing with fabrication flow 1A illustrated in
Continuing methods 6600A of fabrication description using fabrication flow 1A, next, methods 6610 then pattern (etch) the CNT layer using nanotube etching techniques described in incorporated patent references. In certain embodiments, the methods include substantially removing (e.g., etching) the sacrificial polymer such as polypropylene carbonate (PPC) in exposed regions. This removal may be performed, e.g., using anisotropic physical etch, etch as Ar ion milling; or reactive ion etching (RIE) involving O2 plasma; or a combination of both.
Next, methods 6612 complete NV NT block fabrication. Such methods include deposition and patterning a conductor layer to form terminals in contact with the NV NT block at a top, side, or end region, or combinations of contacts thereof as illustrated in
At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and methods 6680 complete the fabrication of chips including passivation and package interconnect means using known industry methods of fabrication. The encapsulated NV NT blocks include a sacrificial polymer as illustrated with respect to block 5730 shown in a 3-D representation in
Alternatively, methods 6615 may substantially remove, (e.g., evaporate) the sacrificial polymer such as polypropylene carbonate for example, by heating the wafer to a temperature in the range of 200 deg. C. to 400 deg. C. In this example, NV NT block 5730 becomes like NV NT block 5730′ shown in a 3-D representation in FIG. 57B′ with NV NT blocks having substantially only CNT fabric formed of individual nanotubes.
Then, methods 6680 complete the fabrication of chips including passivation and package interconnect means using known industry methods of fabrication. The encapsulated NV NT blocks substantially do not include a sacrificial polymer as illustrated with respect to block 5730′ shown in a 3-D representation in FIG. 57B′. At this point in the process, method 6600A of fabrication using fabrication flow 1A ends.
In an alternative fabrication sequence, methods 6600A of fabrication that include fabrication flow 2A use methods 6620 to deposit additional fabrication layers added to the CNT layer, or layers, deposited in a previous step using methods 6608 of fabrication.
Next, methods 6622 pattern multiple layers including the CNT layer. Known industry methods remove (etch) exposed regions of metal, insulator, and semiconductor layers. Exemplary methods of CNT layer etch are described in incorporated patent references. Some methods remove (etch) sacrificial polymer such as polypropylene carbonate (PPC) in exposed regions. Exemplary methods may include anisotropic physical etch, etch as Ar ion milling; or reactive ion etching (RIE) involving O2 plasma; or a combination of both.
By way of example, NV NT switch 6400/6400′ illustrated in
At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and methods 6680 complete the fabrication of chips including passivation and package interconnect means using known industry methods of fabrication. The encapsulated NV NT blocks include a sacrificial polymer as illustrated with respect to block 5730 shown in a 3-D representation in
Alternatively, methods 6615 substantially remove, (e.g., evaporate) the sacrificial polymer such as polypropylene carbonate for example, by heating the wafer to a temperature in the range of 200 deg. C. to 400 deg. C. In this example, NV NT block 5730 becomes like NV NT block 5730′ shown in a 3-D representation in FIG. 57B′ with NV NT blocks having substantially only CNT fabric formed of individual nanotubes.
Then, methods 6680 complete the fabrication of chips including passivation and package interconnect means using known industry methods of fabrication. The encapsulated NV NT blocks substantially do not include a sacrificial polymer as illustrated with respect to block 5730′ shown in a 3-D representation in FIG. 57B′. At this point in the process, method 6600A of fabrication using fabrication flow 2A ends.
A First Method of fabrication of Nonvolatile Nanotube Blocks having a Porous Dielectric
Next, methods 6608 deposit a CNT layer, or layers, from CNT dispersions in a sacrificial polymer dissolved in an organic solvent. For example, sacrificial polymer polypropylene carbonate (PPC) dissolved in an organic solvent such as NMP or cyclohexanone available in the industry. At this point in the process, methods 6600B of fabrication process flow may proceed with fabrication flow 1B. Alternatively, methods 6600B of fabrication process flow may proceed with fabrication flow 2B. Exemplary methods 6600B of fabrication will be described first with respect to fabrication flow 1B, and then followed by methods 6600B of fabrication with respect to fabrication flow 2A.
Continuing methods 6600B of fabrication description using fabrication flow 1B, next, methods 6625 then pattern (etch) the CNT layer using nanotube etching techniques described in incorporated patent references. In some embodiments, methods substantially remove (e.g., etch) the sacrificial polymer such as polypropylene carbonate (PPC) in exposed regions. Exemplary methods include anisotropic physical etch, etch as Ar ion milling; or reactive ion etching (RIE) involving O2 plasma; or a combination of both.
Next, methods 6628 substantially remove (e.g., evaporate) the sacrificial polymer such as polypropylene carbonate for example, by heating the wafer to a temperature in the range of 200 deg. C. to 400 deg. C. In this example, NV NT block 5730 becomes like NV NT block 5730′ shown in a 3-D representation in FIG. 57B′ with NV NT blocks having substantially only CNT fabric formed of individual nanotubes.
Next, methods 6630 form a performance enhancing material such as a porous dielectric. Porous dielectric may be formed using spin-on glass (SOG) and spin-on low-κ organic dielectrics as described in a paper by S. Thanawala et al., “Reduction in the Effective Dielectric Constant of Integrated Interconnect Structures Through an All-Spin-On Strategy”, available from Honeywell Electronic Materials, Honeywell International Inc., Sunnyvale, Calif. 94089. Alternatively, individual nanotubes forming nonvolatile nanotube block structures may be derivitized covalently or non-covalently to generate a modified surface as described in USPTO Patent Pub. No. 2006/0193093 which includes common inventor Bertin and is hereby incorporated by reference in its entirety. Derivitized individual nanotubes may include oxygen, fluorine, chlorine, bromine, iodine (or other) atoms, for example, thereby forming nonvolatile nanotube blocks that include a porous dielectric for performance enhancement purposes.
Next, methods 6632 complete NV NT block fabrication. Such methods include deposition and patterning a conductor layer to form terminals in contact with the NV NT block at a top, side, or end region, or combinations of contacts thereof. In this example, encapsulated NV NT blocks with top and bottom contacts include a performance enhancing material such as a porous dielectric as illustrated with respect to block 5750 shown in a 3-D representation in
At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and methods 6680 complete the fabrication of chips including passivation and package interconnect means using known industry methods of fabrication. The encapsulated NV NT blocks include a performance enhancing material such as a porous dielectric as illustrated with respect to block 5750 shown in a 3-D representation in
In an alternative fabrication sequence, methods 6600B of fabrication that include fabrication flow 2B use methods 6635 to substantially remove (e.g., evaporate) the sacrificial polymer such as polypropylene carbonate from the CNT layer for example, by heating the wafer to a temperature in the range of 200 deg. C. to 400 deg. C.
Next, methods 6638 form a performance enhancing material such as a porous dielectric. Porous dielectric may be formed using spin-on glass (SOG) and spin-on low-κ organic dielectrics as described in a paper by S. Thanawala et al., “Reduction in the Effective Dielectric Constant of Integrated Interconnect Structures Through an All-Spin-On Strategy”, available from Honeywell Electronic Materials, Honeywell International Inc., Sunnyvale, Calif. 94089. Alternatively, individual nanotubes forming nonvolatile nanotube block structures may be derivitized covalently or non-covalently to generate a modified surface as described in USPTO Patent Pub. No. 2006/0193093. Derivitized individual nanotubes may include oxygen, fluorine, chlorine, bromine, iodine (or other) atoms, for example, thereby forming nonvolatile nanotube blocks that include a porous dielectric for performance enhancement purposes.
Next, methods 6640 of fabrication deposit additional fabrication layers added to the CNT layer, or layers, such as conductor, insulating, or semiconducting layers deposited using industry methods of fabrication.
Next, methods 6642 pattern multiple layers including the CNT layer. Known industry methods remove (etch) exposed regions of metal, insulator, and semiconductor layers. Exemplary methods of CNT layer etch are described in incorporated patent references. Exemplary methods remove (etch) exposed portions of the performance enhancing material such as a porous dielectric using known industry methods for etching dielectric material.
At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and methods 6680 complete the fabrication of chips including passivation and package interconnect means using known industry methods of fabrication. The encapsulated NV NT blocks include a performance enhancing material such as a porous dielectric as illustrated with respect to block 5750 shown in a 3-D representation in
A Second Method of fabrication of Nonvolatile Nanotube Blocks having a Porous Dielectric
Next, methods 6650 deposit a CNT layer, or layers, from CNT dispersion in aqueous or non-aqueous solutions are used to fabricate nonvolatile nanotube blocks as described in incorporated patent references. At this point in the process, methods 6600C of fabrication process flow may proceed with fabrication flow 1C. Alternatively, methods 6600C of fabrication process flow may proceed with fabrication flow 2C. Exemplary methods 6600C of fabrication will be described first with respect to fabrication flow 1C, and then followed by methods 6600C of fabrication with respect to fabrication flow 2C.
Continuing methods 6600C of fabrication description using fabrication flow 1C, next, methods 6655 then pattern (etch) the CNT layer using nanotube etching techniques described in incorporated patent references.
Next, methods 6658 form a performance enhancing material such as a porous dielectric. Porous dielectric may be formed using spin-on glass (SOG) and spin-on low-κ organic dielectrics as described in a paper by S. Thanawala et al., “Reduction in the Effective Dielectric Constant of Integrated Interconnect Structures Through an All-Spin-On Strategy”, available from Honeywell Electronic Materials, Honeywell International Inc., Sunnyvale, Calif. 94089. Alternatively, individual nanotubes forming nonvolatile nanotube block structures may be derivitized covalently or non-covalently to generate a modified surface as described in USPTO Patent Pub. No. 2006/0193093. Derivitized individual nanotubes may include oxygen, fluorine, chlorine, bromine, iodine (or other) atoms, for example, thereby forming nonvolatile nanotube blocks that include a porous dielectric for performance enhancement purposes.
Next, methods 6660 complete NV NT block fabrication. Such methods include deposition and patterning a conductor layer to form terminals in contact with the NV NT block at a top, side, or end region, or combinations of contacts thereof. In this example, encapsulated NV NT blocks with top and bottom contacts include a performance enhancing material such as a porous dielectric as illustrated with respect to block 5750 shown in a 3-D representation in
At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and methods 6680 complete the fabrication of chips including passivation and package interconnect means using known industry methods of fabrication. The encapsulated NV NT blocks include a performance enhancing material such as a porous dielectric as illustrated with respect to block 5750 shown in a 3-D representation in
In an alternative fabrication sequence, methods 6600C of fabrication that include fabrication flow 2C uses methods 6665 to form a performance enhancing material such as a porous dielectric. Porous dielectric may be formed using spin-on glass (SOG) and spin-on low-κ organic dielectrics as described in a paper by S. Thanawala et al., “Reduction in the Effective Dielectric Constant of Integrated Interconnect Structures Through an All-Spin-On Strategy”, available from Honeywell Electronic Materials, Honeywell International Inc., Sunnyvale, Calif. 94089. Alternatively, individual nanotubes forming nonvolatile nanotube block structures may be derivitized covalently or non-covalently or mixed with pristine nanotubes to generate a modified surface as described in USPTO Patent Pub. No. 2006/0193093. Derivitized individual nanotubes may include oxygen, fluorine, chlorine, bromine, iodine (or other) atoms, for example, thereby forming nonvolatile nanotube blocks that include a porous dielectric for performance enhancement purposes.
Next, methods 6670 of fabrication deposit additional fabrication layers added to the CNT layer, or layers, such as conductor, insulating, or semiconducting layers deposited using methods industry methods of fabrication.
Next, methods 6675 pattern multiple layers including the CNT layer. Known industry methods substantially remove (etch) exposed regions of metal, insulator, and semiconductor layers. Exemplary methods of CNT layer etch are described in incorporated patent references. In some embodiments, methods remove (etch) exposed portions of the performance enhancing material such as a porous dielectric by using known industry methods for etching dielectric material, especially oxygen plasma and reactive ion etching with gasses that are capable of removing carbon nanotubes which are unprotected by photoresist or other processing materials. Such etches may be isotropic or anisotropic depending upon the orientation required.
At this point in the process, NV NT switches incorporating NV NT blocks have been formed, and methods 6680 complete the fabrication of chips including passivation and package interconnect means using known industry methods of fabrication. The encapsulated NV NT blocks include a performance enhancing material such as a porous dielectric as illustrated with respect to block 5750 shown in a 3-D representation in
3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Nonvolatile Nanotube Blocks as Nonvolatile NT Switches using Top and Bottom Contacts to form Cathode-on-NT Switches
Some embodiments of methods 2710 described further above with respect to
Next, methods 2730 illustrated in
Exemplary methods 2740 illustrated in
NV NT blocks with top (upper level) and bottom (lower level) contacts, illustrated further above in
Methods fill trenches with an insulator; and then methods planarize the surface. Then, methods deposit and pattern word lines on the planarized surface.
The fabrication of vertically-oriented 3D cells illustrated in
The electrical characteristics of Schottky (and PN, PIN) diodes may be improved (low leakage, for example) by controlling the material properties of polysilicon, for example polysilicon deposited and patterned to form polysilicon regions 6820-1 and 6820-2. Polysilicon regions may have relatively large or relatively small grain boundary sizes that are determined by methods of fabrication such as anneal times and temperatures for example. In some embodiments, SOI deposition methods in the semiconductor industry may be used that result in polysilicon regions that are single crystalline (no longer polysilicon), or nearly single crystalline, for further electrical property enhancement such as low diode leakage currents.
Examples of contact and conductors materials include elemental metals such as Al, Au, Pt, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix. In some cases conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as both contact and conductors materials as well as anodes for Schottky diodes. However, in other cases, optimizing anode material for lower forward voltage drop and lower diode leakage is advantageous. Schottky diode anode materials may be added (not shown) between conductors 6710-1 and 6710-2 and polysilicon regions 6720-1 and 6720-2, respectively. Such anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ti, W, Ta, Zn and other elemental metals. Also, silcides such as CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2, and ZrSi2 may be used. Schottky diodes formed using such metals and silicides are illustrated in the reference by NG, K. K. “Complete Guide to Semiconductor Devices”, Second Edition, John Wiley and Sons, 2002, pp. 31-41, the entire contents of which are incorporated herein by reference.
Next, having completed Schottky diode select devices, methods form N+ polysilicon regions 6725-1 and 6725-2 to contact N polysilicon regions 6720-1 and 6720-2, respectively. N+ polysilicon is typically doped with arsenic or phosphorous to 1020 dopant atoms/cm3, for example, and has a thickness of 20 to 400 nm, for example. N and N+ polysilicon region dimensions are defined by trench etching near the end of the process flow.
Next, methods form bottom (lower level) contact regions 4030-1 and 4030-2 with ohmic or near ohmic contacts to polysilicon regions 6725-1 and 6725-2, respectively. Examples of contact and conductors materials include elemental metals such as Al, Au, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix.
Next, methods form NV NT block 4050-1 and 4050-2 on the surface of contact regions 4030-1 and 4030-2, respectively, having the nanotube element length of the NV NT blocks defined by the nanotube thickness in the vertical Z direction and X-Y cross section defined by trench etching near the end of the process flow. Note that NV NT block 4050-1 in
Next, methods form top (upper level) contacts 4065-1 and 4065-2 on the top surfaces of NV NT blocks 4050-1 and 4050-2, respectively, with X and Y dimensions defined by trench etching near the end of the process flow.
Next, methods form (etch) trench openings 4075, 4075A, and 4075B, each of width F, thereby forming inner and outer sidewalls of cells C00 and C01 and corresponding top (upper level) and bottom (lower level) contacts, nanotube elements, and insulators. Bottom (lower level) contacts 4030-1 and 4030-2 form an electrical connection between NV NT blocks 4050-1 and 4050-2, respectively, and corresponding underlying steering diode cathode terminals, and form bit lines 6710-1 and 6710-2. Trench formation (etching) stops at the surface of insulator 6703.
Next, methods fill trench openings 4075, 4075A, and 4075B with an insulator 4060, 4060A, and 4060B, respectively, such as TEOS and planarize the surface. All trenches can be formed simultaneously.
Next, methods deposit and planarize a word line layer.
Next, methods pattern word line 6770.
Next, methods 2750 illustrated in
Nonvolatile nanotube diodes forming cells C00 and C01 correspond to nonvolatile nanotube diode 1200 schematic in
Embodiments of methods 2700 illustrated in
Methods of Fabricating 3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Nonvolatile Nanotube Blocks as Nonvolatile NT Switches Using Top and Bottom Contacts to form Cathode-on-NT Switches
Embodiments of methods 2710 illustrated in
Methods of fabrication for elements and structures for support circuits and interconnections 6801, insulator 6803, memory array support structure 6805, conductor layer 6810, N polysilicon layer 6820, N+ polysilicon layer 6825, and bottom (lower level) contact layer 6830 illustrated in
Next, methods deposit a nanotube layer 6835 on the planar surface of contact layer 6830 as illustrated in
At this point in the fabrication process, methods deposit top (upper level) contact layer 6840 on the surface of nanotube layer 6835 as illustrated in
Next methods deposit and pattern a masking layer 6850 on top (upper level) contact layer 6840 as illustrated in
At this point in the process, mask layer 6850 openings 6855, 6855A, and 6855B may be used for directional etching of trenches using methods that define a cell boundary along the X direction for 3D cells using one NV NT diode with an internal cathode-to-nanotube connection per cell. U.S. Pat. No. 5,670,803, the entire contents of which are incorporated herein by reference, to co-inventor Bertin, discloses a 3-D array (in this example, 3D-SRAM) structure with simultaneously trench-defined sidewall dimensions. This structure includes vertical sidewalls simultaneously defined by trenches cutting through multiple layers of doped silicon and insulated regions in order avoid multiple alignment steps. Such trench directional selective etch methods may cut through multiple conductor, semiconductor, oxide, and nanotube layers as described further above with respect to trench formation in FIGS. 34A-34FF and 36A-36FF. In this example, selective directional trench etch (RIE) removes exposed areas of top (upper level) contact layer 6840 to form upper level contact regions 6840-1 and 6840-2; removes exposed areas of nanotube layer 6835 to form nanotube regions 6835-1 and 6835-2; removes exposed areas of bottom (lower level) contact layer 6830 to form bottom (lower level) contact regions 6830-1 and 6830-2; directional etch removes exposed areas of N+ polysilicon layer 6825 to form N+ polysilicon regions 6825-1 and 6825-2; removes exposed areas of polysilicon layer 6820 to form N polysilicon regions 6820-1 and 6820-2; and removes exposed areas of conductor layer 6810 to form conductor regions 6810-1 and 6810-2, stopping at the surface of insulator 6803 and simultaneously forming trench openings 6860, 6860A, and 6860B as illustrated in
Next methods fill trench openings 6860, 6860A, and 6860B with insulators 6865, 6865A, and 6865B, respectively, such as TEOS for example and planarize as illustrated in
Next, methods deposit and planarize a conductor layer 6870 that contacts top (upper level) contacts 6840-1 and 6840-2 as illustrated in
Next, conductor layer 6870 is patterned to form word lines approximately orthogonal to conductors (bit lines) 6810-1 and 6810-2 as illustrated further below.
At this point in the process, cross section 6875 illustrated in
Next, methods deposit and pattern a masking layer such as masking layer 6880 with openings 6882, 6882A, and 6882B on the surface of word line layer 6870 as illustrated in
At this point in the process, openings 6882, 6882A, and 6882B in masking layer 6880 may be used for directional etching of trenches using methods that define new cell boundaries along the Y direction for 3D cells using one NV NT diode with an internal cathode-to-nanotube connection per cell. All trenches and corresponding cell boundaries may be formed simultaneously (e.g., using one etch step) using the methods of fabrication as used to form X-direction trenches as described with respect to
Next methods fill trench openings 6884, 6884A, and 6884B with insulators 6885, 6885A, and 6885B such as TEOS for example and planarize as illustrated by cross section 6890 in
At this point in the process, cross sections 6875 and 6890 illustrated in
3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Nonvolatile Nanotube Blocks as Nonvolatile NT Switches using Top and Bottom contacts to form Anode-on-NT Switches
In some embodiments, methods 3010 described further above with respect to
Next, methods 3030 illustrated in
In some embodiments, methods 3040 illustrated in
NV NT blocks with top (upper level) and bottom (lower level) contacts, illustrated further above in
Methods fill trenches with an insulator; and then methods planarize the surface. Then, methods deposit and pattern bit lines on the planarized surface.
The fabrication of vertically-oriented 3D cells illustrated in
Examples of contact and conductors materials include elemental metals such as Al, Au, W, Ta, Cu, Mo, Pd, Pt, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix. Insulators may be SiO2, SiNx, Al2O3, BeO, polyimide, Mylar or other suitable insulating material.
Next, methods form N+ polysilicon regions 6920-1 and 6920-2 to contact word line regions 6910-1 and 6920-2, respectively. N+ polysilicon is typically doped with arsenic or phosphorous to 1020 dopant atoms/cm3, for example, and has a thickness of 20 to 400 nm, for example.
Next, N polysilicon regions 6925-1 and 6925-2 are formed to contact N+ polysilicon regions 6920-1 and 6920-2, respectively, and may be doped with arsenic or phosphorus in the range of 1014 to 1017 dopant atoms/cm3 for example, and may have a thickness range of 20 nm to 400 nm, for example. N polysilicon regions 6925-1 and 6925-2 form the cathode regions of corresponding Schottky diodes. N and N+ polysilicon region dimensions are defined by trench etching near the end of the process flow.
Next, methods form contact regions 6930-1 and 6930-2 on N polysilicon regions 6925-1 and 6925-2, respectively. Contact regions 6930-1 and 6930-2 form anode regions that complete the formation of vertically oriented steering diode structures. Contact regions 6930-1 and 6930-2 also form bottom (lower level) contacts for NV NT blocks 4050-1 and 4050-2, respectively. Fabrication of the vertically-oriented diode portion of structure 6900 is similar to methods of fabrication described with respect to
In some cases conductors such as Al, Au, W, Cu, Mo, Ti, and others may be used as both NV NT block contacts and anodes for Schottky diodes. However, in other cases, optimizing anode material for lower forward voltage drop and lower diode leakage is advantageous. In such an example (not shown) a sandwich may be formed with Schottky diode anode material in contact with N polysilicon regions and NV NT block contact material forming bottom (lower regions) contacts. Such anode materials may include Al, Ag, Au, Ca, Co, Cr, Cu, Fe, Ir, Mg, Mo, Na, Ni, Os, Pb, Pd, Pt, Rb, Ru, Ta, Ti, W, Zn and other elemental metals. Also, silicides such as CoSi2, MoSi2, Pd2Si, PtSi, RbSi2, TiSi2, WSi2, and ZrSi2 may be used. Schottky diodes formed using such metals and silicides are illustrated in the reference by NG, K. K. “Complete Guide to Semiconductor Devices”, Second Edition, John Wiley and Sons, 2002, pp. 31-41, the entire contents of which are incorporated herein by reference. Examples of NV NT block contact and materials, also in contact with anode materials, include elemental metals such as Al, Au, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix.
Next, methods form NV NT block 4050-1 and 4050-2 on the surface of contact regions 6930-1 and 6930-2, respectively, having the nanotube element length LSW-CH of the NV NT blocks defined by the nanotube thickness in the vertical Z direction and X-Y cross section defined by trench etching near the end of the process flow. Note that NV NT block 4050-1 in
Next, methods form top (upper level) contacts 4065-1 and 4065-2 on the top surfaces of NV NT blocks 4050-1 and 4050-2, respectively, with X and Y dimensions defined by trench etching near the end of the process flow.
Next, methods form (etch) trench openings 6975, 6975A, and 6975B of width F thereby forming inner and outer sidewalls of cells C00 and C10 and corresponding top (upper level) and bottom (lower level) contacts, nanotube elements, and insulators. Bottom (lower level) contacts 6930-1 and 6930-2 form an electrical connection between NV NT blocks 4050-1 and 4050-2, respectively, and also form underlying steering diode anode terminals, and form word lines 6910-1 and 6910-2. Trench formation (etching) stops at the surface of insulator 6903.
Next, methods fill trench openings 6975, 6975A, and 6975B with an insulator 6960, 6960A, and 6960B such as TEOS and planarize the surface. All trenches can be formed simultaneously.
Next, methods deposit and planarize a bit line layer.
Next, methods pattern bit line 6970.
Nonvolatile nanotube diodes forming cells C00 and C10 correspond to nonvolatile nanotube diode 1300 schematic in
At this point in the process, corresponding structures in the X direction are formed to complete NV NT diode-based cell structures.
Cross section 7000 illustrated in
N+ polysilicon regions 6920-1′ and 6920-1″ form contacts between word line 6910-1 (WL0) and N polysilicon regions 6925-1′ and 6925-1″, respectively, that form diode cathode regions. Bottom (lower level) contacts 6930-1′ and 6930-1″ act as anodes to form Schottky diodes with N polysilicon regions 6925-1′ and 6925-1″, respectively, as well as contacts to nonvolatile nanotube blocks 4050-1′ and 4050-1″, respectively, as illustrated in cross section 7000 illustrated in
NV NT block 4050-1′ and 4050-1″ on the surface of contact regions 6930-1′ and 6930-1″, respectively, have nanotube element length LSW-CH of the NV NT blocks defined by the nanotube thickness in the vertical Z direction and X-Y cross section defined by trench etching near the end of the fabrication process. Note that NV NT block 4050-1′ in
Contacts to the top surfaces of NV NT tubes are illustrated in
Bit lines 6970-1 (BL0) and 6970-2 are in direct contact with top (upper level) contacts 4065-1′ and 4065-1″, respectively, as illustrated in
Next, methods 3050 illustrated in
Corresponding cross sections 6900 and 7000 illustrated in
Corresponding cross sections 6900 and 7000 illustrated in
Nonvolatile Memories using NV NT Diode Device Stacks with both Shared Array Line and Non-Shared Array Line Stacks and Cathode-to-NT Switch Connections and Nonvolatile Nanotube Block with Top and Bottom Contacts forming 3-D NV NT Switches
In general, methods 3210 fabricate support circuits and interconnections in and on a semiconductor substrate. This includes NFET and PFET devices having drain, source, and gate that are interconnected to form memory (or logic) support circuits. Such structures and circuits may be formed using known techniques that are not described in this application. In some embodiments, methods 3210 are used to form a support circuits and interconnections 7201 layer as part of cross sections 7200 and 7200′ illustrated in
Next, methods 3210 are also used to fabricate an intermediate structure including a planarized insulator with interconnect means and nonvolatile nanotube array structures on the planarized insulator surface such as insulator 7203 illustrated in cross sections 7200 and 7200′ in
Next, methods 3220, similar to methods 2740, are used to fabricate a first memory array 7210 using diode cathode-to-nanotube switches based on a nonvolatile nanotube diode array similar to a nonvolatile nanotube diode array cross section 6700 illustrated in
Next, methods 3230 similar to methods 3040 illustrated in
The memory array cell area of 1 bit for array 7210 is 4F2 because of the 2F periodicity in the X and Y directions. The memory array cell area of 1 bit for array 7220 is 4F2 because of the 2F periodicity in the X and Y directions. Because memory arrays 7220 and 7210 are stacked, the memory array cell area per bit is 2F2. If four memory arrays (not shown) are stacked, then the memory array cell area per bit is 1F2.
Exemplary methods 3240 using industry standard fabrication techniques complete fabrication of the semiconductor chip by adding additional wiring layers as needed, and passivating the chip and adding package interconnect means.
In operation, memory cross section 7200 illustrated in
The memory array cell area of 1 bit for array 7410 is 4F2 because of the 2F periodicity in the X and Y directions. The memory array cell area of 1 bit for array 7420 is 4F2 because of the 2F periodicity in the X and Y directions. Because memory arrays 7420 and 7410 are stacked, the memory array cell area per bit is 2F2. If four memory arrays (not shown) are stacked, then the memory array cell area per bit is 1F2.
An Alternative Simplified 3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Nonvolatile Nanotube Blocks as Nonvolatile NT Switches using Top and Bottom contacts to form Cathode-on-NT Switches
A memory block structure with top (upper level) and bottom (lower level) contacts illustrated in
Nonvolatile memory array methods of fabrication correspond to methods of fabrication described further above with respect to
Defining bit lines BL0 and BL1 prior to 3-D NV NT diode formation requires that masks be aligned to pre-defined bit lines BL0 and BL1. Using semiconductor industry methods, alignment may be achieved within a range of approximately +−F/3. So, for example, for F=45 nm node, the alignment will be within +−15 nm and bit lines BL0 and BL1 are therefore in contact with most of the anode area of 3-D NV NT diodes memory cells as illustrated further below with respect to
Support circuits and interconnections 7501 illustrated in nonvolatile memory array 7500 illustrated in
Planarized insulator 7503 illustrated in
Bit lines 7510-1 (BL0) and 7510-2 (BL1) are patterned as described further below with respect to
Cell C00 includes a corresponding 3-D NV NT diode formed by a steering diode with a cathode-to-NT series connection to a bottom (lower level) contact of a NV NT block. Anode 7515-1 is in contact with bit line 7510-1 (BL0), and the top (upper level) contact 7565-1 of NV NT block 7550-1 is in contact with word line 7570-1 (WL0). The NV NT diode corresponding to cell C00 includes anode 7515-1 in contact with bit line 7510-1 (BL0), and also in contact with N polysilicon region 7520-1. N polysilicon region 7520-1 is in contact with N+ polysilicon region 7525-1. Anode 7515-1, N polysilicon region 7520-1, and N+ polysilicon region 7525-1 form a Schottky-type of steering diode. Note that PN or PIN diodes (not shown) may be used instead. N+ polysilicon region 7525-1 is in contact with bottom (lower level) contact 7530-1, which also forms the bottom (lower level) contact of NV NT block 7550-1. NV NT block 7550-1 is also in contact with top (upper level) contact 7565-1, which is in turn in contact with word line 7570-1 (WL0). NV NT block 7550-1 channel length LSW-CH is vertically oriented and is approximately equal to the distance between top (upper level) contact 7565-1 and bottom (lower level) contact 7530-1, which may be defined by the thickness of the NV NT block.
Cell C01 includes a corresponding 3-D NV NT diode formed by a steering diode with a cathode-to-NT series connection to a bottom (lower level) contact of a NV NT block. Anode 7515-2 is in contact with bit line 7510-2 (BL1), and the top (upper level) contact 7565-2 of NV NT block 7550-2 is in contact with word line 7570-1 (WL0). The NV NT diode corresponding to cell C01 includes anode 7515-2 in contact with bit line 7510-2 (BL1), and also in contact with N polysilicon region 7520-2. N polysilicon region 7520-2 is in contact with N+ polysilicon region 7525-2. Anode 7515-2, N polysilicon region 7520-2, and N+ polysilicon region 7525-2 form a Schottky-type of steering diode. Note that PN or PIN diodes (not shown) may be used instead. N+ polysilicon region 7525-2 is in contact with bottom (lower level) contact 7530-2, which also forms the bottom (lower level) contact of NV NT block 7550-2. NV NT block 7550-2 is also in contact with top (upper level) contact 7565-2, which is in turn in contact with word line 7570-1 (WL0). NV NT block 7550-2 channel length LSW-CH is vertically oriented and is approximately equal to the distance between top (upper level) contact 7565-2 and bottom (lower level) contact 7530-2, and may be defined by the thickness of the NV NT block.
Cell C10 includes a corresponding 3-D NV NT diode formed by a steering diode with a cathode-to-NT series connection to a bottom (lower level) contact of a NV NT block. Anode 7515-3 is in contact with bit line 7510-1 (BL0), and the top (upper level) contact 7565-3 of NV NT block 7550-3 (not visible behind word line 7570-1) is in contact with word line 7570-2 (WL1). The NV NT diode corresponding to cell C10 includes anode 7515-3 in contact with bit line 7510-1 (BL0), and also in contact with N polysilicon region 7520-3. N polysilicon region 7520-3 is in contact with N+ polysilicon region 7525-3. Anode 7515-3, N polysilicon region 7520-3, and N+ polysilicon region 7525-3 form a Schottky-type of steering diode. Note that PN or PIN diodes (not shown) may be used instead. N+ polysilicon region 7525-3 is in contact with bottom (lower level) contact 7530-3, which also forms the bottom (lower level) contact of NV NT block 7550-3. NV NT block 7550-3 is also in contact with top (upper level) contact 7565-3, which is in turn in contact with word line 7570-2 (WL1). NV NT block 7550-3 channel length LSW-CH is vertically oriented and is approximately equal to the distance between top (upper level) contact 7565-3 and bottom (lower level) contact 7530-3, and may be defined by the thickness of NV NT block.
Cell C11 includes a corresponding 3-D NV NT diode formed by a steering diode with a cathode-to-NT series connection to a bottom (lower level) contact of a NV NT block. Anode 7515-4 is in contact with bit line 7510-2 (BL1), and the top (upper level) contact 7565-4 of NV NT block 7550-4 (not visible behind word line 7570-1) is in contact with word line 7570-2 (WL1). The NV NT diode corresponding to cell C11 includes anode 7515-4 in contact with bit line 7510-2 (BL1), and also in contact with N polysilicon region 7520-4. N polysilicon region 7520-4 is in contact with N+ polysilicon region 7525-4. Anode 7515-4, N polysilicon region 7520-4, and N+ polysilicon region 7525-4 form a Schottky-type of steering diode. Note that PN or PIN diodes (not shown) may be used instead. N+ polysilicon region 7525-4 is in contact with bottom (lower level) contact 7530-4, which also forms the bottom (lower level) contact of NV NT block 7550-4. NV NT block 7550-4 is also in contact with top (upper level) contact 7565-4, which is in turn in contact with word line 7570-2 (WL1). NV NT block 7550-4 channel length LSW-CH is vertically oriented and is approximately equal to the distance between top (upper level) contact 7565-4 and bottom (lower level) contact 7530-4, and may be defined by the thickness of the NV NT block. The opening 7575 between 3-D NV NT diode-based cells C00, C01, C10, and C11 is filled with in an insulator such as TEOS (not shown).
Nonvolatile nanotube diodes forming cells C00, C01, C10, and C11 correspond to nonvolatile nanotube diode 1200 schematic in
An Alternative Simplified Methods of Fabricating 3-Dimensional Cell Structure of Nonvolatile Cells using NV NT Devices having Vertically Oriented Diodes and Nonvolatile Nanotube Blocks as Nonvolatile NT Switches Using Top and Bottom Contacts to form Cathode-on-NT Switches
In some embodiments, methods 2710 illustrated in
Methods of fabrication for elements and structures for support circuits and interconnections 7601 and insulator 7603 forming memory array support structure 7605 correspond to methods of fabrication described further above with respect to
At this point in the process, methods of fabrication pattern conductor layer 7610 to form bit lines 7610-1 and bit lines 7610-2 and other bit lines separated by insulating regions 7612, as illustrated in
Examples of conductor (and contact) materials include elemental metals such as Al, Au, Pt, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides such as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix.
In some cases materials such as those used in conductor layer 7610 may also be used as anodes for Schottky diodes, in which case a separate layer such as contact (anode) layer 7615 may not be required. In other cases, a separate contact (anode) layer 7615 may be used for enhanced diode characteristics. For example, contact layer 3415 illustrated in
In some embodiments, methods may deposit Schottky diode anode materials to form contact (anode) layer 7615 on conductor layer 7610 as in
At this point in the process, methods deposit N polysilicon layer 7620 on contact (anode) layer 7615; N+ polysilicon layer 7625 deposited on N polysilicon layer 7620; and bottom (lower level) contact layer 7630 deposited on N+ polysilicon layer 7625 as illustrated in
Exemplary methods of fabrication for N polysilicon layer 7620 illustrated in
Next, methods deposit a nanotube layer 7650 on the planar surface of contact (anode) layer 7630 as illustrated in
At this point in the fabrication process, methods deposit top (upper level) contact layer 7665 on the surface of nanotube layer 7650 as illustrated in
Next methods deposit and pattern a masking layer 7672 on top (upper level) contact layer 7650 as illustrated in
At this point in the process, methods selectively directionally etch exposed regions between mask shapes 7672-1R, 7672-2R, 7672-3R, and 7672-4R, beginning with top (upper level) contact layer 7665 ending on surface of conductor layer 7610, at the top surface of bit lines such as bit lines 7610-1 and 7610-2 thus forming opening 7675 (not shown) and simultaneously forming all surfaces (boundaries) of 3-D NV NT diodes that form cells C00, C01, C10, and C11 in
U.S. Pat. No. 5,670,803, the entire contents of which are incorporated herein by reference, to co-inventor Bertin, discloses a 3-D array (in this example, 3D-SRAM) structure with simultaneously trench-defined sidewall dimensions. This structure includes vertical sidewalls simultaneously defined by trenches cutting through multiple layers of doped silicon and insulated regions in order avoid multiple alignment steps. Such trench directional selective etch methods may be adapted for use to cut through multiple conductor, semiconductor, oxide, and nanotube layers as described further above with respect to trench formation in FIGS. 34A-34FF, 36A-36FF, and 68A-68I for example. In this example, selective directional trench etch (RIE) removes exposed areas of top (upper level) contact layer 7665 to form top (upper level) contacts 7565-1, 7565-2, 7565-3, and 7565-4 illustrated in
Exemplary methods of selectively directionally etching exposed regions between mask shapes 7672-1R, 7672-2R, 7672-3R, and 7672-4R correspond to methods of directionally etching corresponding to forming trench regions in
Next methods fill trench openings 7675 and planarize with an insulator such as TEOS for example filling region 7575 (fill not shown) illustrated in
Next, methods deposit, planarize, and pattern (form) conductors such as word lines 7570-1 (WL0) and 7570-2 (WL1) illustrated in
Nonvolatile Memories using Stacks of Alternative Simplified 3-Dimensional Cell Structures with Non-Shared Array Lines
Simplified 3-dimensional nonvolatile memory array 7500 enables stacking multi-levels of sub-arrays based on memory array 7500 to achieve high density bit storage per unit area. Nonvolatile memory array 7500 has a cell area 4F2 and a bit density of 4F2/bit. However, a 2-high stack holds two bits in the same 4F2 area and achieves a bit density of 2F2/bit. Likewise, a 4-high stack achieves a bit density of 1F2/bit, an 8-high stack achieves a 0.5F2/bit density, and a 16-high stack achieves a 0.25F2/bit density.
Planarized insulator 7707 illustrated in
Three stacking levels with left and right-side 3-D sub-arrays corresponding to nonvolatile memory array 7500 in
Sub-array bit line segments are interconnected by vertical interconnections and then fanned out to BL driver and sense circuits 7705 as illustrated in stacked nonvolatile memory arrays 7700 in
BL driver and sense circuits 7705 may be used to read or write to bit locations on any of the stacked levels in stacked nonvolatile memory array 7700 illustrated in
When forming nonvolatile memory arrays, annealing of polysilicon layers in the temperature range of 700 to 800 deg-C for approximately one hour may be required to control grain boundary size and achieve desired electrical parameters such as forward voltage drop and breakdown voltages for steering diodes. For 3-D arrays, such annealing may be performed before or after NV NT block switch formation. When stacking memory arrays to form stacked nonvolatile memory arrays 7700, annealing in the temperature range of 700 to 800 deg-C for one hour may be required to improve steering diode electrical properties after NV NT block switches are formed, because the diode layers may be arranged over the NV NT blocks. Bottom (lower level) and top (upper level) contact materials may need to tolerate temperatures of up to 800 deg-C without forming carbides (note, nanotubes are tolerant of temperatures well in excess of 800 deg-C). Choosing a block contact material such as Pt can help to ensure that carbides do not form because Pt is insoluble in carbon. Also, choosing high melting point materials such as Mo, Cr, and Nb can also avoid carbide formation. Mo and Nb carbides form above 1000 deg-C, and Cr carbides form above 1200 deg-C. Other high-melting point metals may be used as well. By choosing contact metals that either do not form carbides, or form carbides above 800 deg-C, annealing of stacked nonvolatile memory arrays, in which diodes are arranged above and/or below the NV NT blocks and their associated contacts, can be performed without contact-to-nanotube degradation. Thus, at least some embodiments of the invention are resilient to high temperature processing without degradation. Phase diagrams for various metals and carbon may found in various references.
Alternate Embodiments
CELL 1 includes p-type doped substrate PSUB with n-type doped regions N+, and write line 1 WL 1, according to conventional field effect transistor select technology. Conductive element (stud) 7810 creates an electrical pathway between N+ (e.g. drain) and first conductive terminal 7830. Thin nanotube article 7850 is disposed in direct and permanent physical contact to the first conductive terminal 7830 and the second conductive terminal 7830′. The resistive characteristics of the thin NV NT article 7850 may be controllably changed in response to electrical stimulus applied to 7830 and 7830′ according to the various explanations provided above and in the incorporated references.
The 2-D NV NT switches depicted in 7800 have numerous advantages. The nanotube article 7850 may be coated with one or relatively few applications towards the end of the fabrication process flow. Moreover, the thin characteristics imply that less CNT material, on the whole, is needed to form the film from which nanotube article 7850 is patterned. In certain instances, less CNT material corresponds to lower fabrication costs. Moreover, the aforementioned attributes result in higher wafer throughput, in certain embodiments. By increasing wafer throughput, fabrication costs can again be reduced when producing relatively significant volume of arrays of 2D NV NT switches. In certain instances, structure 7800 may be more easily patterned at smaller dimensions than alternate structures having, for example, multilayered nanotube fabrics.
Yet the 2D NV NT switches depicted in 7800 have various disadvantages as well, under particular circumstances. The structure of
CELL 1 includes select circuitry, according to conventional field effect transistor select technology. Conductive element (stud) 7910 creates an electrical pathway between N+ (e.g. source) and first conductive terminal 7930. 3-D nanotube block 7950 is disposed in direct and permanent physical contact to the first conductive terminal 7830 and the second conductive terminal 7965. The resistive characteristics of the NV NT block 7950 may be controllably changed in response to electrical stimulus applied to 7930 and 7965, according to the various explanations provided above and in the incorporated references.
The 3-D NV NT switch with NV NT block 7910 has various advantages that differentiate it from the structure disclosed above in
As compared with the structure depicted in
3-D NV NT diode with a NV NT block structure 8000 has a number of advantages. The first prominent advantages involves the highly compact cell size of approximately 4F2 and, correspondingly the smallest chip area implemented to date. As a result, the embodiment depicted in
For purposes of illustration,
Specifically, NV NT cross point switches 8100 include one or more bottom traces 8130 disposed in or on a substrate 8140. Disposed over an upper surface of the bottom trace 8130 and adjacent substrate 8140 is NV NT trace 8150 comprising a patterned CNT fabric layer and patterned conductor 8120, conformally disposed. The NV NT trace 8150 and conductor 8120 are typically applied conformally and then etched in a single step to form the sandwitched NV NT trace. However, numerous fabrication methods are described in incorporated reference U.S. patent application Ser. No. 61/074,241 and envisioned here. U.S. patent application Ser. No. 61/074,241 shows examples of cells such as illustrated in
NV NT switch 8100 layout, when combined with 3-D NV NT diode cells such as illustrated in
The various disadvantages to structure 8100 are similar to those described above with reference to structure 8000, in terms of the thick multi-layered fabric entailing multiple thin coats and relatively larger amounts of CNT material used. However, structure 8100 is distinguishable from the NV NT block embodiments discussed above. First, it is less difficult to pattern a NV NT trace at the smallest dimensions than it is to pattern a NV NT block because fewer critical etching (and alignment) steps are required. Second, the NV NT traces should be operated in a way such that adjacent cell cross talk is minimized. The NV NT block structures have no such operation limitation. Of note is that the multilevel storage features and program/erase operation operation described above, with reference to incorporated reference U.S. Ser. No. 11/835,583, filed Aug. 8, 2007 entitled “Latch Circuits and Operation Circuits Having Scalable Nonvolatile Nanotube Switches as Electronic Fuse Replacement Elements” also apply to structure 8100.
The advantages detailed above with reference to
Switch and Diode Structures Using Mixed Nanoscopic Materials and Various Performance and Fabrication Advantages
The above NV NT switches, structures, NRAM arrays and NV NT diodes have all been described as containing nanotube fabric articles. Nanotube fabric articles can be composed primarily of nanotubes. In certain embodiments, purified nanotubes may be preferred. In fact, relatively purified nanotube materials may have clear performance benefits in particular applications. However, in other applications, a nanotube fabric can include any number of different additional materials that can play an active or passive role in switching performance. Together, a first volume of carbon nanotubes and a second volume of other nanoscopic particles can be used to provide a matrix of mixed or composite nanoscopic materials. The first volume of carbon nanotubes and second volume of other nanoscopic particles may interact covalently or non-covalently. The introduction of the second volume of other nanoscopic particles may be used to controllably alter the porosity of a nanotube fabric and/or the density of the resultant matrix.
Although the Figures below depict the nanoscopic particles as discrete particles and the nanotubes as the matrix, it should be noted that the morphology of the nanoscopic particles and carbon nanotubes may be different. For example, in certain embodiments, the carbon nanotubes may form the discrete phase and the nanoscopic particles may form the matrix phase. In some other embodiments, the carbon nanotubes and the nanoscopic particles can both form interconnected matrix phases. The nanotube fabric layer can act as a switching material between a first electrode and a second electrode.
Whereas in other contexts, nanoscopic particles other than nanotubes might be viewed as undesirable impurities, in the composite article of the present invention, the nanoscopic particles are a deliberately added component, introduced to achieve the desired device performance, such as desired switching attributes. Indeed, the nanoscopic particles are selectively mixed with nanotubes to form a composite article having a predefined volumetric ratio of nanoscopic particles to nanotubes. The ratio may be pre-selected and tuned to ensure, for example, the desired range of electrical switching or resistive states. The attributes of the nanoscopic particles—the material, the size, the uniformity of the particulate population, the shape of the nanoscopic particles, its interaction with the nanotubes, etc.—can all be specifically selected to further tune the desired device characteristics (e.g., electrical switching or resistive characteristics) of the resultant composite article. Moreover, in certain instances, the attributes of the nanoscopic particles itself may further dictate the predefined ratio of the nanoscopic particles and nanotubes. Regardless, in each case, the purposeful and deliberate addition of nanoscopic particles can have the common effect of allowing inventors additional control in tuning and refining the characteristics (electrical, physical, thermal or otherwise) of the composite article. For example, addition of the nanoscopic particles in a predefined ratio with the nanotubes may decrease the switching voltages of the composite article as compared to switches formed from pristine nanotubes.
The predefined ratio of the nanoscopic particles to the nanotubes can be any ratio selected by the manufacturer depending on the application, method of combination, or the composition of materials used in the device. For example, in certain applications, some suitable and non-limiting predefined ratio of the nanoscopic particles to the nanotubes may be from about 1:1 (one part nanoscopic particles to about one part nanotubes) to about 1:10 (one part nanoscopic particles to about ten part nanotubes). For example, some suitable and non-limiting predefined ratio of the nanoscopic particles to the nanotubes may be 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10.
In such cases, the employment of composite nanoscopic materials may have certain different advantages, both in terms of device performance and ease of fabrication. As noted above with respect to
By way of introduction, the advantages and disadvantages of including certain selected additional nanoscopic materials to create a composite or mixed nanoscopic material fall under two categories: fabrication process and device performance. In certain process flows, a composite or mixed nanoscopic material can be easier to fabricate and use than a material consisting of substantially purified nanotubes. For example, corresponding equivalent nonvolatile nanotube switches formed using mixed or composite nanoscopic materials may be applied to a wafer in a single coat, or at most a few coats, as opposed to multiple coats (i.e. 10 to 50 for example). A single coat (or few coats) relaxes the process flow requirements because a single coat (or few coats) requires less process time, fewer tools, and increases wafer throughput, as well as reducing the amount of costly purified nanotubes required to achieve certain device parameters. Lower fabrication costs result in less costly NV NT memory. Mixed or composite nanoscopic material can be also be more easily patterned. This is because mixed or composite nanoscopic material may be thinner than CNT-only nanotube material while still preventing shorts between upper and lower electrodes. Therefore, mixed or composite nanoscopic material may be somewhat easier to pattern than a substantially purified nanotube fabric at smaller dimensions.
In addition to fabrication advantages, when using mixed or composite nanoscopic materials to form the various NV NT devices, there are performance advantages as well. As discussed above with reference to
In certain embodiments, a variety of nanoscopic particles may be used as an additional nanoscopic material and/or performance enhancing material to form a mixed or composite nanoscopic material. Carbon particles may be used. Carbon particles may include may include various allotropes of carbon. To date, known allotropes of carbon include Diamond, Graphite, Lonsdaleite, C60 (Buckminsterfullerene), fullerenes such as but not limited to C20, C26, C28, C36, C50, C70, C72, C76, C84, C540, Amorphous carbon, and carbon nanotubes, each having a distinct atomic structure. Additional nanoscopic materials may have one or more of these forms of carbon. For the purposes of the ensuing discussion, “nanoscopic particle”, (which has no required short-range structural periodicity) will be used to cover these “mixed or composite carbon allotropes” and other types of nanoscopic elements or materials that might be used. While amorphous carbon is typically used in the art to describe one particular allotrope of carbon having no short range order in lattice structure or other atomic pattern, this application will use the term “nanoscopic particles” (NP) to additional nanoscopic materials that may include one or more allotropes of carbon that may or may not have short range order (e.g. fullerene, graphene, carbon nanotubes, etc.). Accordingly, in the ensuing discussion, the particular form of a mixed or composite nanoscopic material in which the additional nanoscopic material includes carbon in some form will be referred to as a nanoscopic particle:carbon nanotube mixture (NP:CNT). This mixed or composite nanoscopic material is understood to cover a matrix of material having at least some carbon nanotubes and other nanoscopic particles.
Selected carbon allotropes may be specifically used, or a generic mixture of nanoscopic particles may be used as the additional nanoscopic material. In certain instances, there will occur in situ formation of one or more particular allotropes of carbon from an NP mixture, in response to electrical stimulus (with certain voltage and current combinations). To date, a generic mixture of NP having multiple carbon allotropes has been observed to actively contribute to electrical switching mechanisms of an NP:CNT device. Thus at least one allotrope of carbon aside from the carbon nanotubes contributes to the NP:CNT switching behaviors. The inventors, while not wishing to be bound by theory, believe that the observed switching behavior may be attributable to nanoscopic electromechanical behaviors, atomic dislocation and/or structural transformations on the atomic scale, or contributions of both.
The other nanoscopic particles 8350b can take a plurality of forms depending on the needs of an application or structure in which the methods of the present invention are employed. In certain embodiments, the nanoscopic particles may be miscible with the nanotubes and form a continuous material around the nanotube. In some other embodiments, the nanoscopic particles The additional nanoscopic particles may be inert to the nanotubes and remain in the same form as initially introduced into the mixture and therefore non-miscible. In yet some other embodiments, the nanoscopic particles may be partially miscible with the nanotubes and form a semi-miscible mixture with the nanotubes. The nanoscopic particles may be introduced to the mixture of nanoscopic particles and carbon nanotubes either before deposition on the substrate or after the nanotube fabric is applied to the substrate. In the first application, the nanoscopic particles are combined with the carbon nanotubes by introducing them into the solution in which the carbon nanotubes are suspended. In the second application, the nanoscopic particles may be introduced by, for example, ion-implantation, vapor deposition, or other methods known in the art.
Furthermore, in certain embodiments, the choice of such nanoscopic particles can include a material or materials that can be formed with a uniform particle size. In certain applications, the choice of a nanoscopic particle can include a material or materials which can be fabricated as individual particles within certain dimensions. For example, an application may require a nanoscopic particle wherein individual particles are not larger than some fraction of a device feature size. Nanoscopic particles can be some aggregation of material having a size of one or more atoms or molecules grouped together. At least one dimension being less than one micron (μm) and at least one dimension being greater than or equal to one nanometer (nm). The particles can have any variety of shapes with a corresponding range of surface areas. The nanoscopic particles may interact covalently or non-covalently with another nanoscopic materials, for example the carbon nanotubes. The nanoscopic particles have the ability to alter the porosity of the total matrix.
The additional nanoscopic particles can take a plurality of forms depending on the needs of an application or structure in which the methods of the present invention are employed. The nanoscopic particles may be spherical, oblong, square, irregular, or any other shapes as would be readily apparent to ordinary skill in the art. The nanoscopic particles may have at least one dimension that is in the nanometer size. For example, the nanoscopic particles may have at least one dimension which is less than 100 nm, 50 nm, 40 nm, 30 nm, 25 nm, 20 nm, 10 nm, 5 nm, or 1 nm. In certain embodiments, the nanoscopic particles may have dimensions that are acceptable in semiconductor fabrication facilities, such as a CMOS facility. In certain embodiments, the nanoscopic particles may be individual atoms or ions. In each such case, the nanoscopic particle can interact covalently or non-covalently to another nanoscopic material, for example, carbon nanotubes. In certain embodiments, the nanoscopic particles may be miscible with the nanotubes and form a continuous material around the nanotube. In some other embodiments, the nanoscopic particles may be inert to the nanotubes and remain in the same form as initially introduced into the mixture and therefore non-miscible. In yet some other embodiments, the nanoscopic particles may be partially miscible with the nanotubes and form a semi-miscible mixture with the nanotubes. In certain embodiments, the nanoscopic particles has the ability to alter the porosity between the carbon nanotubes.
The nanscopic particles may be introduced to the mixture of nanoscopic particles with carbon nanotubes either before deposition non the substrate or after the nanotube fabric is applied to the substrate. In the first application, the nanoscopic particles can be combined with the carbon nanotubes by introducing them into the solution containing carbon nanotubes. In the second application, the nanoscopic particles can be introduced, for example, by ion implantation, vapor deposition, or other methods known in the art.
In some other embodiments, the choice of such nanoscopic particles can include a material or materials which do not adversely affect the switching operation (that is, the changing from one nominal nonvolatile resistive state to another) of the nanotube fabric layer. In fact, in certain embodiments, the nanoscopic particles 8350b may improve switching operation by lowering the voltage needed for the nanotube fabric layer to change its resistance.
In some other embodiments, inorganic nanoparticles can be utilized. For example, silicon based materials (such as, but not limited to silicon oxide and silicon nitride) can be used for said other nanoscopic particles 8350b.
In some embodiments, one or more allotropes of carbon (such as, but not limited to, diamond, graphite, graphene, fullerenes, amorphous carbon, carbon black, carbon nanopowder, carbon nanobuds, carbon nanorods, carbon nanofoam, lonsdaleite, linear acetylenic carbon, polyaromatic hydrocarbons, and the like) can be used for said other nanoscopic particles 8350b.
In certain embodiments, nanoscopic particles 8350b can include a mixture of different nanoscopic materials, such as any combination of nanoscopic particles 8350b described above.
In the ensuing discussion, nanoscopic particle/carbon nanotube mixture “NP:CNT” will be used to refer to those mixed or composite materials in which one or more allotropes of carbon, including carbon nanotubes, are present. The particular allotrope, amorphous carbon (aC), and the general nanoscopic particle mixture (NP) are exemplary instances of the additional nanoscopic material. In certain embodiments, NP may consist of a plurality of different carbon structures that may repeat their atomic arrangement over comparatively short periods and may, in fact, vary their atomic arrangement during switching operation. Depending on the particular NP used, the additional nanoscopic material may play an active or passive role in the switching mechanism enacted in the NP:CNT composite nanoscopic material article.
The nonvolatile nanotube switch channel length LSW-CH is the separation between terminal 8310 and 8320. LSW-CH is important to the operation of nonvolatile nanotube switch 8300 as described further below. Substrate 8360 may be an insulator such as ceramic or glass, a semiconductor, or an organic rigid or flexible substrate. Substrate 8360 may be also be organic, and may be flexible or stiff. Insulator 8340 may be SiO2, SiN, Al2O3, or another insulator material. Terminals 8310 and 8320 may be formed using a variety of contact and interconnect elemental metals such as Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSix and TiSix. Carbon may be used as well.
Within the nanomaterial switching element 8350, there are a variety of nanomaterials. In certain embodiments, the composite nanomaterial may be constructed so that the ratio of the first component—the plurality of nanotubes 8350a, to the second component—the plurality of additional nanoscopic particles 8350b, is carefully managed. The ratio may be selected such that the volume density of nanotubes 8350a within the switching element 8350 is optimized for the intended application of the NV NT Switch 8300. For example, a switching element (article of composite nanomaterial) 8350 that has a smaller volume density of nanotubes 8350a would, in a typical application, tend to require a smaller switching voltage. In contrast, a switching element (article of composite nanomaterial) 8350 that has a larger volume density of nanotubes may, depending on the additional nanoscopic material population, tend to use a larger switching voltage. Further, by optimizing the volume density of nanotubes 8350a, the switching performance and responsiveness of the switching element (article of composite nanomaterial) can be controlled, independently from the physical dimensions of switching element 8350. In other words, the ratio of the number of nanotubes 8350a to additional nanoscopic material particles 8350b used within said switching element 8350, is selected to achieve the desired switching parameters for a range of physical dimensions and geometries. As a result, the switching element 8350 has the flexibility to be integrated into a great range of applications.
In addition to electrical consideration, the additional nanoscopic material may reduce the overall need for nanotube material. Since nanotubes are more expensive, significant cost reduction per wafer may be achieved.
Within switching element 8350, the nanotubes 8350a are typically nanotubes. A variety of nanotubes are envisioned for use—semiconducting, metallic, single-walled, multi-walled, etc.—and may be selected according to the requirements of the particular application. The additional nanoscopic particles 8350b can be selected from a plurality of materials including, but not limited to, other allotropes of carbon—such as amorphous carbon, graphene, graphite, diamond, and black carbon, or mixtures of carbon fiber materials. Additional nanoscopic particles 8350b may also be composed of silicon based materials—such as, but not limited to, silicon oxide particles and silicon nitride particles. Performance enhancing materials 8350b may also include porous dielectric materials (e.g. polypropylene). In some embodiments the selected additional nanoscopic material is inert, meaning that it does not participate in the programming of nonvolatile resistance states within the NV NT switch 8300. In yet other embodiments, the selected additional nanoscopic material is active, meaning that is does participate in the programming of nonvolatile resistance states within the NV NT switch 8350. Further, in some embodiments, more than one type of additional nanoscopic material is used.
The formation of nanotubes 8350 having inert and active selected additional nanoscopic materials is also detailed in Nantero U.S. patent application Ser. No. 10/936,119, now U.S. Pat. No. 7,416,993, incorporated by reference in its entirety. U.S. Pat. No. 7,416,993 specifically describes nanotube articles in which the carbon nanotubes may be pristine, functionalized, or filled with other material, e.g., nanowire materials. Additionally, Nantero U.S. Pat. No. 6,643,165, the entire contents of which are incorporated by reference, discloses combinations of carbon nanotubes and other materials—e.g. pyrenes. Various other examples of inert and active additional nanoscopic materials are envisioned.
In those embodiments in which the selected additional nanoscopic material is inert, the nanotubes 8350a provide a plurality of variably conductive pathways through the nanotube article. The nanotube fabric's characteristics and variable resistance in response to electrical stimulus are described at length in U.S. patent application Ser. No. 11/280,786, the entire contents of which are incorporated by reference in their entirety. Inert additional nanoscopic materials may be used to provide various structural, fabrication, and performance improvements. For example an inert additional nanoscopic material may be used to create a more robust mixed or composite nanotube fabric, reducing the amount of nanotubes present in a given volume of composite material. In other embodiments, inert additional nanoscopic materials may simplify fabrication process flows by permitting certain impurities or reducing the amount of purified carbon nanotube material used. fewer layers. Moreover, the density of nanotubes may be deliberately controlled to influence electrical characteristics by adjusting the matrix porosity. In certain embodiments, the introduction of inert materials effectively lowers the required operating voltage. The introduction of certain inert additional nanoscopic materials may also reduce the contact voltage between the composite nanoscopic material and the conductive contacts.
In those embodiments in which the selected additional nanoscopic material is active, the nanotubes 8350a and additional nanoscopic particles 8350b jointly provide a plurality of variably conductive pathways through the composite nanoscopic article. The active additional nanoscopic material may be selected to enhance switching performance by, for example, increasing the difference in resistance values between the substantially conductive (ON) and substantially non-conductive (OFF) states of the switch. The active additional nanoscopic material may also be selected to enhance switching performance by increasing the number of switch cycles achieved without degradation of results. Where the selected additional nanoscopic material is active and comprises one or more carbon allotropes, high and low resistance states of the switching element 8350 can be attributed to changes in the electrically conductive pathways provided by nanotubes 8350a and particles 8350b.
Various explanations have been proposed for the switching mechanism, including the mechanism described in European Patent No. 1916722 entitled “Carbon Filament Memory and Fabrication Method,” the entire contents of which are hereby incorporated by reference. European Patent No. 1916722 proposes a mechanism in which conductive filaments may be formed in one or more carbon layers, the carbon layer(s) including the sp2-rich carbon that is substantially conductive and the sp3-rich carbon that is substantially insulating. European Patent No. 1916722 proposes that changes in conductivity in the carbon layers(s) is attributed to changes in the proportion of sp2 and sp3 carbon, in response to applied electrical stimulus. While not wishing to be bound by theory, the inventors believe that the mechanism proposed by European Patent No. 1916722 is one of several possible explanations for the operation of nonvolatile nanotube switches having carbon-based active additional nanoscopic materials. As a variety of non-carbon-based active additional nanoscopic materials may be used as performance enhancing materials, the aforementioned example is illustrative and not representative.
There are many advantages to using a mixed or composite nanoscopic material for switching applications, as described above. The new switching material 8350 enables the fabrication of NV NT switches and NV NT diodes and other structures with these advantages. For example, NP:CNT mixtures enable at least some of the following advantages over purified CNT materials, when used in fabricating NV NT switches and/or NV NT diodes:
Detailed information concerning the fabrication steps and corresponding advantages are provided in U.S. Pat. No. 7,915,637 filed on date even herewith, entitled “Improved Switching Materials Comprising Mixed Nanoscopic Particles and Carbon Nanotubes and Methods of Making and Using Same,” the entire contents of which are herein incorporated by reference. Inventors have found that NP:CNT mixture materials can enable the combined advantages of more chips per wafer with less CNT material and fewer process steps than those contemplated in CNT-only applications. As a result, the NP:CNT mixtures and devices employing them entail reduced memory manufacturing costs. These various fabrication processes are compatible with providing a NV NT switch, diode, or memory element having multi-level storage characteristics, as described in detail in incorporated reference U.S. patent application Ser. No. 11/835,583. Depending upon the particular semiconductor fabrication methods implemented (e.g. to form select diodes, select FETs or other integrated circuit components) certain additional nanoscopic materials may be more or less preferable in improving process flow and switching performance.
Generally, the process to form a mixed or composite nanoscopic particle layer over a substrate includes the following steps. First, a plurality of nanotubes 8350a is combined with a volume of additional nanoscopic particles 8350b to create a homogenous solution or heterogeneous mixture 8350. The homogenous solution or heterogeneous mixture 8350 is then applied to a substrate 8340 via a spin coat process. The ratio of nanotubes 8350a to additional nanoscopic particles 8350b within the mixture 8350 is selected such as to provide a desired volume density of nanotubes 8350a within said mixture 8350 such that a desired nanotube volume density within a layer formed using said homogenous solution can be realized. The nanotubes 8350a can be carbon nanotubes with multi-wall, single-wall, semiconducting, metallic and/or other characteristics. The additional nanoscopic particles 8350b can be comprised of one or more silicon based materials, including, but not limited to, silicon oxide (siO2) and silicon nitride (Si3N4). Or, additional nanoscopic particles 8350b can be comprised of one or more allotropes of carbon, including but not limited to, graphite, carbon nanopowder, amorphous carbon, carbon black, and diamond. Mixtures of various additional nanoscopic materials are also possible. Creating additional nanoscopic materials from carbon typically entails creating carbon black material from a carbon nanopowder and implementing a number of chemical treatment processes known in the art to create nanoscopic carbon particles (e.g. one or more carbon allotropes with having no clear short term atomic order).
The conversion involves one or more chemical treatments. According to one exemplary embodiment of the process flow, a first step comprises reacting carbon black with an oxidizing agent such as nitric acid. The reaction typically decreases the size of carbon black particles and also enables the removal of metallic contaminants via solubilization (which can be improved by adding other acids such as HCl). Subsequently, filtration at low pH via cross-flow membranes may be used to remove the solubilized impurities from the slurry. Next, an exemplary process may include increasing the slurry pH to achieve a homogeneous or stable colloidal system. In certain embodiments, sonication might be used to improve homogeneity. The resulting colloidal system may subsequently be filtered through a train of filters to remove any particles which would lead to defects in the spin coated film. In certain embodiments, this may entail using filters with pores as small as approximately 5 nm. At this point, the process entails mixing the resultant colloidal system with a CNT solution at rations which will enable the generation of a suitable film. Suitable films will be expected to have incorporated the necessary density of CNT's to build memory devices of the specified sizes and performance attributes.
In one or more process steps, the NP:CNT mixture is deposited over a first electrode element via a spin coating process to form composite article (as illustrated by structure 8350). The NP:CNT mixture allows for the deposition of significantly thicker (as compared to prior art nanotube solutions) layers (or films) within a single spin coat process as compared to nanotube-only liquids. For example, thickness ranging from about a few to hundreds of nanometers may be possible through a single coat. Some non-limiting example thicknesses that can be achieve include 1, 2, 2.5, 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 150, or 200 nm. As such, a sufficiently thick composite article suitable for use within a plurality of nanotube block switching devices (such as, but not limited to, block switches, programmable resistive materials, and programmable logic devices) can be realized in a minimum number of spin coat process steps. Further, in many applications, such a layer can be realized within a single spin coat process step, significantly reducing process time and cost.
The NP:CNT mixture can be deposited over a first electrode via a spin coating process to form composite article 8350. The composite article 8350 can have very low level metal contamination. For example, the composite article 8350 may have less than 1018, 1016, 1015, 1014, 1013, 1012, 5×1011, 1×1011, 5×1010, or even less than 1×1010 atoms/cm2. Thereafter, a second electrode can be deposited over the composite article 8350.
The first column 8601 of table 8600 lists various nonvolatile nanotube switch configurations, as exemplified in the indicated Figures. By way of example, the first entry of column 8601 refers to the geometrical arrangement depicted in
The fifth column, 8605 simply indicates that element 8350 of
Specifically, NAND memory array 8900 includes a first bit line BL1, a reference line REF, write lines corresponding to each cell WL1-WL4 and corresponding switch regions SW1-SW4. The stud/vias form electrical connections to corresponding N+ diffusions of underlying FETs TR1-TR4, respectively. The select line SL1 enables an electrical connection between bit line BL1 and a contact on one side of the NAND array structure by activating transistor TRS1. The select line SL2 enables an electrical connection between reference line REF and a contact on the other side of the NAND array structure by activating transistor TRS2. Note that it is also possible to connect one side (contact) of the NAND array directly to reference line REF and eliminate select line SL2 and transistor TRS2.
Switching mechanisms for the vertical conductive pathway are described fully in incorporated U.S. patent application Ser. No. 11/835,613, entitled “Memory Elements and Cross Point Switches and Arrays of Same Using Nonvoltatile Nanotube Blocks,” incorporated by reference in its entirety. Each bit line—word line combination (e.g. bottom and top conductive trace) selects a discrete NP:CNT block 9050, thereby selecting a discrete nanotube memory cell in the NRAM array. The resistance state of each NP:CNT block 9010 may thus be programmed to represent a memory state of each nonvolatile cross point switch used for logic signal routing. Multi-resistance states (values) may be used to represent multiple to generate logic weighting states programmed into the same nonvolatile nanotube block. As an example, one low resistance state and one high resistance state may be used to represent an activated routing path and an unactivated routing path, respectively. Alternatively, three low resistance states and one high resistance state may be used to store three logic weighting factors and one no connect represented as logical 00, logical 01, logical 10, and logical 11 states. More logic weighting states are possible using more resistance states. U.S. patent application Ser. No. 11/835,612 illustrates NRAM memories with multi-resistance states per nonvolatile nanotube storage location. Similar techniques may be used to generate multiple logic weighting states. The electrical signals for programming the weighting factor of each logic routing path is formed by altering the resistance state for each nanotube block as described fully in the incorporated references and may be selected according the various requirements of the particular application.
Constructed with NP:CNT material 8350 to form switching region 9010, array 9000 is capable of being SET and RESET at lower voltages than analogous cross point switch arrays using primarily CNT material. The switching element 9005 (dashed outline of switching region 9010 and top and bottom lines 9030, 9020) can be SET and RESET to ON or OFF states multiple times for programmable wiring. The switching function of each adjacent cell is largely independent but may experience certain amounts of capacitive coupling. Capacitive coupling at the intersection between approximately orthogonal conductors can cause unwanted noise coupling between adjacent lines and is factored into cross point switch design.
Switching element 9005 can be made of a thicker or thinner NP:CNT layer 9010 to minimize coupling noise as needed. The thickness of 9010 may be varied between approximately 2-5 nm to approximately 500 nm, for example, based on capacitance coupling considerations without inhibiting or compromising the switch operation. As noted above, the use of the NP:CNT material 8350 to form blocks 9010 enable switching for SET and RESET functions at or less than a device operating voltage of 5 V. Programmable wiring and implementation for array 9000 is described in detail in U.S. Provisional Patent Application No. 61/088,828, entitled “Nonvolatile Nanotube Programmable Logic Devices and a Nonvolatile Nanotube Field Programmable Gate Array Using Same,” filed Aug. 14, 2008, the entire contents of which are herein incorporated by reference. U.S. Provisional Patent Application No. 61/088,828 specifically details field programmable gate array (FPGA) technology integrated with NV NT switches.
NV NT Switches Formed Using Carbon Nanotube Elements, Carbon Elements, and Various Non-carbon Elements
As described in detail above, nonvolatile nanotube switches and blocks may be formed using a carbon nanotube-only material (CNT) or may be formed using a mixture of nanoscopic elements such as CNT with another nanoscopic material to form a composite material having carbon nanotubes and additional nanoscopic particles (NP:CNT). CNT-only material and NP:CNT material may be used to form nanoscopic switching elements and various devices. Various geometrical configurations and devices of interest include: NRAM® memory cells such as 7800 and 7900 illustrated in
In each such instance depicted in the Figures, the nonvolatile nanotube (NV NT) switches and NV NT blocks use nanotube material (CNT) of varying thickness and composition. Each device and geometrical configuration may also be constructed using a composite material, NP:CNT. When these NV NT switches and blocks include an additional nanoscopic material, a composite is formed from a mixture of the CNT with that additional material. As noted, the composite may be substantially homogeneous or heterogeneous. One example in which a composite material NP:CNT is used is depicted in
In a variety of embodiments, carbon-based materials may be chosen and fabricated to form carbon layers in contact with carbon nanotube layers so as to improve the performance of switches constructed from these layers. For example, the use of carbon layers may improve switch performance by lowering the operating voltage to less than 5 volts, lowering operating current to less than 50 μA, and improving the ability to tolerate high rapid thermal anneal (RTA) temperatures. The RTA temperature tolerance depends on the application. For example, for NRAM® memories in which memory arrays are formed, RTA temperatures of less than 500 to 600° C. for a short time may be sufficient. However, when forming NV NT diode memories such as illustrated in
One way of attaining the aforementioned characteristics includes reducing contact resistance between carbon nanotubes and contacts. Reducing contact resistance may reduce operating voltage by enabling more of the applied voltage across the two terminals of the switch to appear across the active region of the switch. In another example, nanotube material may be processed and nanotube solutions may be formed to provide enhanced electrical characteristics in the resultant NV NT switches (such as those illustrated in
The NV NT diode memory array 9260 in fact includes nonvolatile nanoscopic carbon stacks having multiple elements. The nanoscopic carbon stacks forming NV NT diode memory array 9260 are not composed exclusively of nanotubes but instead include one or more layers of carbon and carbon nanotubes to form one or more carbon elements and carbon nanotube elements, respectively. Whereas in previously described embodiments, such as
The NV NT switch 9205 is formed by replacing upper level (top) contact 4065 in
In the present example, nanoscopic element stack 9250 has upper level carbon element 9255 and underlying carbon nanotube (CNT) element referred to as nanotube element 9245. Thus together, the carbon element 9255 and nanotube element 9245 form a heterogeneous block referred to as nanoscopic element stack 9250. The top surface of carbon element 9255 is the portion of nanoscopic element stack 9250 that is in contact with array wire 9270, as noted above. Therefore, it is the interface between the carbon element 9255 and the array wire 9270 that forms the upper level (top) contact 9280. Similarly, it is the interface between the bottom surface of the nanotube material 9245 and bottom contact 9230 which forms the lower level (bottom) contact corresponding to element 4030 illustrated in
Within upper level carbon element 9255 can be found any range of carbon materials. As described in greater detail above, the carbon layer can comprise one or more carbon allotropes such as amorphous carbon, graphene, graphite, diamond, fullerenes such as but not limited to C20, C26, C28, C36, C50, C60, C70, C72, C76, C84, C540, etc. which includes carbon nanotubes (similar to carbon nanotubes in carbon element 9245), nanoscopic carbon elements, as well as any variety of impurities as described further below with respect to
Within the lower level carbon nanotube element 9245 can be found any range of carbon nanotube materials. As described in detail above, carbon nanotubes can comprise one or more of multi-walled, single-walled, semiconducting and/or metallic nanotubes, or nanotubes having other attributes. Due at least in part to the performance attributes of carbon element 9255, inventors have found that the thickness of carbon nanotube element 9245 may be less than corresponding nanotube element 4050 illustrated in
Forming the 3-D NV NT diodes in CELL 1 and CELL 2 of NV NT diode memory array 9260 having nanoscopic element stacks has a number of advantages. The first prominent advantage involves the highly compact cell size of approximately 4F2 and, correspondingly, the smallest chip area implemented to date. As a result, the embodiment depicted in
The present cell select and control structure include conductive plug (stud) 9310 connecting bottom contact 9330 to an N+ region embedded in P-type substrate PSUB. In the present cross sectional view, word line WL1 forms one portion of the cell select circuitry. CELL 1, structure 9305, may be integrated on a 1024 bit array for the purposes of electrical testing to evaluate electrical characteristics of nanoscopic element stack 9350 formed using carbon element 9355 and nanotube element 9345. In one or more embodiments, tests include SET to program the cell (write 1), RESET to erase the cell (write 0) and READ to access the stored state of the cell. SET, RESET and READ functions are known in the art and discussed in greater detail above in relation to 3-D cell structures employing nanotube articles as described in, U.S. patent application Ser. No. 11/835,613, filed Aug. 8, 2007, entitled “Memory Elements and Cross Point Switches and Arrays of Same Using Nonvolatile Nanotube Blocks,” the entire contents if which are incorporated by reference.
In the embodiments described below, the carbon material (carbon NP:CNT) may comprise one or more allotropes of carbon, for example, amorphous carbon. The discussion of performance and fabrication advantages will focus on NV nanoscopic element stacks for purposes of illustration. One of sufficient skill in the art will understand that other similar combinations are envisioned and within the scope of the present disclosure. Nanoscopic element stack 9650A is discussed in detail below. In the ensuing discussion, carbon elements will be used to refer to those materials in which one or more allotropes of carbon, including carbon nanotubes, are present. The particular allotrope, amorphous carbon, is referred to here to exemplify the variability of the carbon element material. In certain embodiments, NV nanoscopic carbon elements may consist of a plurality of different carbon structures that may repeat their atomic arrangement over comparatively short periods and may, in fact, vary their atomic arrangement during switching operation.
Within the NV nanoscopic element stack 9650A, there may be a variety of carbon materials, depending on the fabrication methods used. For example, portions of nanoscopic element stack 9650A may include electrically conductive regions, electrically nonconductive regions, thermally conductive regions, thermally nonconductive regions, and mixed electrically and thermally conducting regions. The electrically conductive regions may be conductive as-deposited, non-electrically conductive as-deposited, in situ-activated conductive regions. Electrically conductive paths in nanoscopic element stack 9650A form and uniform with applied voltage and/or current. Such regions may include various allotropes of carbon such graphite, diamond, amorphous carbon, Buckminster-fullerenes, and carbon nanotubes of various types. Characteristics of various regions of nanoscopic element stack 9650A correspond to those properties are listed in
Various characteristics of nanoscopic element stack 9650A described further above optimize the composition of nanoscopic element stack 9650A in terms of less fabrication complexity and electrical performance such as switching voltages below 5 volts. A variety of allotropes of carbon are envisioned based on methods of NV nanoscopic carbon element fabrication. An important consideration in achieving lower switch operating voltages is minimizing contact resistance and thereby maximizing the portion of applied voltage to terminals of NV NT switch 9600A that appears across nanoscopic element stack 9650A. For example, this involves controlling the contact resistance between top contact 9665 and carbon element 9655A and bottom contact 9630 and nanotube element 9645A of nanoscopic element stack 9650A. In addition, the interface between bottom surface of carbon element 9655A and the top surface of nanotube element 9645A may be optimized for performance as well. Optimization of electrical characteristics may be achieved by using carbon material and methods of fabrication that produce in carbon element 9655A composed of various allotropes of carbon. Also, a variety of nanotubes may be used in forming nanotube element 9645A: semiconducting, metallic, single-walled, multi-walled, etc. These, and other methods of fabrication may be selected to optimize nanoscopic element stack 9650A according to the requirements of particular applications.
The nanoscopic element stack 9650A can be formed from a plurality of performance enhancing materials other than allotropes of carbon or carbon black. For example, noncarbon material such as silicon, Ge, and other semiconductor materials may form the additional material. Silicon based materials include but not are not limited to, silicon oxide and/or silicon nitride particles. Other nanoscopic particles of Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitable conductors, or conductive nitrides, oxides, or silcides such as RuN, RuO, TiN, TiCN, WN, TaN, CoSix and TiSix may be used to provide the additional material. Yet other examples of performance enhancing materials such as porous dielectric materials (e.g. porous SiO2) are envisioned to provide enhanced structure for pattern definition and etching, used to prevent penetration of the top electrode during deposition, and enhanced operation through improved ion implant control in the CNT layer. For those skilled in the art of porous dielectric materials, other examples in addition to porous SiO2 are porous HSQ (hydrogen silsesquioxane), porous MSQ (methylsilsesquioxane), porous silicon oxynitride, and proprietary materials such as porous SiLK available from Dow Chemical Company, Silica Xerogels available from Honeywell Electronics Materials, and Orion™ a SiCOH PECVD film available from Trikon.
In each instance, the additional material is used to enhance the performance of the nanoscopic element stack 9650A material, from which the devices and/or switches are formed. In some embodiments the selected included material is inert, meaning that it does not participate in the programming of nonvolatile resistance states within the nanoscopic element stack 9650A of NV NT switch 9600A. In yet other embodiments, the selected included material is active, meaning that is does participate in the programming of nonvolatile resistance states within the NV NT switch 9600A. Further, in some embodiments, more than one type of selected included material is used.
NV NT switch 9600A illustrates one of a number of NV carbon-based structures. Other examples of NV NT switch structures are illustrated further below in
For NV NT switch 9600A, during the fabrication of nanoscopic element stack 9650A described further below with respect to
While top and bottom contacts are described in terms of conductive material, top and bottom contacts may be formed of semiconducting material such as silicon, germanium, and others. Silicon, for example, may be P-type or N-type and doped over a broad range of dopant concentrations values from near-intrinsic high resistivity to degenerately doped low resistivity. Various dopants including boron, phosphorous, or arsenic, for example, may be used and are well known in the industry.
In the case of NV NT switch 9600B illustrated in
As described above with respect to
Various NV NT switch configurations such as NV NT switch 4005 shown in
In certain embodiments, an amorphous carbon layer or a high resistance region within the nanoscopic element stack is used in the construction of NV NT switch structures to increase the initial resistance of the nanoscopic element stack. In such embodiments, various modifications may be made with the use of the process flow and resultant structures described in detail above and with reference to the preceding Figures. In certain embodiments, NRAM® cells may be formed by providing an amorphous carbon layer. Upper metal or dielectric layers may be deposited over the nanotube layer and provided such that they do not penetrate into the nanotube fabric or have only limited penetration into the nanotube fabric. To control the penetration of the metal or dielectric layer into the nanotube layer, characteristics of the nanotube fabric are controlled.
In certain embodiments, a thin oxide layer (thin enough to permit tunneling, for example) may be interposed between a conductor such as tungsten and the nanotubes at or near the nanoscopic element stack surface. This thin oxide layer may be used to enhance contact performance and/or yield. In this case, surface functionalization may be achieved using standard chemical surface modification techniques known to those skilled in the art.
Contact resistance between carbon nanotube elements and top or bottom contacts may also be affected by relatively high RTA temperatures. For example, when top or bottom contacts are formed using TiN in contact with carbon nanotube elements and the contact is exposed to high temperatures (e.g. 750° C. RTA), contact resistance may be reduced by the formation of relatively low resistance titanium-carbide contacts. If higher contact resistance is desired, then tungsten may be used. Tungsten is a good option because it does not react with carbon to form tungsten-carbide unless temperatures are significantly above 800° C.
Lower ON resistance of NV NT switches may also be caused at relatively high RTA temperatures in excess of 700° C. for example. In this case, defects present in carbon nanotube elements may be reduced by RTA and corresponding carbon nanotube element resistance may be reduced. Ion implantation of nitrogen, argon, or xenon for example in the carbon nanotube element region may be used to controllably introduce defects that may increase carbon nanotube element resistance. However, in cases where carbon nanotube element resistance is too high, carbon may be implanted to lower the resistance.
In certain embodiments, ion implantation may be applied through the top conductor layer into various underlying layers. This is enabled by optimizing ion implant energy for various species such as nitrogen, argon, germanium, silicon, oxygen, carbon, and other examples.
The operation of the nanoscopic element stack switch may be controlled by introducing additional non-carbon nanoscopic particles NP (
NV NT switch (device) performance altering materials—carbon and non-carbon—may be added anywhere within a nanoscopic element stack region that may include carbon nanotube elements (material) or NP:CNT matrix material for example. Thus a stack may have non-carbon elements, carbon elements, carbon nanotube elements and/or NP:CNT matrix material elements. Performance enhancing atoms may also be added by ion implantation or material may be included during deposition anywhere in the NV NT switch, including in top and bottom contact regions as well. Performance altering material may be used to decrease or increase NV NT switch ON resistance, to reduce NV NT switching voltages and/or current flow during transitions between high and low resistance states for example, to increase NV NT switch cyclability (number of ON/OFF cycles allowed), or any other number of attributes. Performance altering material may be used to increase NV NT switch reliability and improve tolerance to harsh conditions such as high temperatures operation (250° C., for example) or relatively high doses of radiation.
By way of example,
Interface element 9635D may be formed using relatively thin SiO, SiN, alumina or other dielectric structures in the range of 1 to 20 nm for example. Interface element 9635D thickness may be chosen such that tunneling current may flow, thereby limiting current flow in NV NT switch 9600D resulting in relatively high ON resistance states. Alternately, interface element 9635D may be formed as an antifuse layer which is activated in-situ and used to limit current flow. Another alternative is to form a silicon rich SiO oxide element for use as interface element 9635D with limited controlled current flow. Still another alternative for current control is to form interface element 9635D using a semiconductor layer doped in a range from relatively low to relatively high resistivity values, as described further above. Semiconductor materials may include silicon, germanium, or other semiconductor materials.
In certain cases, even with the inclusion of interface element 9635D, NV NT switch 9600D ON resistance may still be too low. In that case, NV NT switch ON resistance may be increased further by using less carbon material in the NV NT switch structure.
In certain cases, lower ON resistance NV NT switches may be desirable. In such cases, ON resistance may be reduced by adding another carbon element layer. However, carbon element resistance may vary depending on methods of fabrication as described below with respect to
Matrix material may also correspond to a composition of multiple materials or material phases including various nanoscopic particles and carbon nanotubes in a matrix (NP:CNT matrix) described further above. Nanoscopic particles may include insulators such as SiO, SiN, AlO, other insulators. Nanoscopic particles may also include various semiconductor nanoscopic particles such as Si, Ge, and other semiconductor material. Nanoscopic particles may include various conductive nanoscopic particles such as W, Ti, TiN and others, nanoscopic particles may also include nanoscopic particles of carbon. Nanoscopic particles may also include various combinations of these various insulating, semiconducting, conducting, carbon including one or more allotropes of carbon, and other nanoparticles. Examples of NP:CNT matrix materials are described further above with respect to
Specifically, NV nanoscopic nanotube cross point switches 9800 include one or more bottom traces 9830 disposed in or on a substrate 9840. These elements correspond to bottom traces 8130 in or on a substrate 8140 illustrated in
U.S. patent application Ser. No. 61/074,241 shows examples of cells such as illustrated in
NV nanotube cross point switches 9800 layout using nanoscopic trace stack concepts may be combined with 3-D NV NT diode cells such as illustrated in
For purposes of illustration,
Specifically, NV nanoscopic carbon cross point switches 9900 include one or more bottom traces 9930 disposed in or on a substrate 9940. These elements correspond to bottom traces 8230 in or on a substrate 8240 illustrated in
NV nanoscopic carbon switch 9900 layout using nanoscopic plane stack concepts when combined with 3-D NV NT diode cells such as illustrated in
NV NT switch 10015-1 corresponds to NV NT switch 9600A. Nanoscopic element stack 10050-1 corresponds to nanoscopic element stack 9650A shown in
By using nanoscopic element stack 10050-1 as part of NV NT Switch 10015-1, a thin layer of nanotube element 10045-1 may deposited in a single operation. This reduces process complexity and results in simpler deposition methods. NV NT switch 10015-1 performance is enhanced because lower operating voltages may be used. The operating conditions are similar to those described in
As is the case with NV NT switch structure 10000 described further above, NV NT switch structure 10000′ may enhance the performance of NV NT switch 10015-2 because lower operating voltage may be used as described further above with respect to NV NT switch 10015-1.
NV NT switch structure 10000″ illustrated in
Nanotube article 10065 may be used as local wiring within cell 10005-3. Examples of nanotube articles (fabrics) used as local wiring in memory cells and arrays as illustrated in incorporated references U.S. Pat. No. 6,706,402 and U.S. Provisional Patent Appl. No. 61/088,828. Nanotube article 10065 may include a combination of metallic and semiconducting nanotubes; may include SWNTs, MWNTs or combinations thereof, may include only metallic nanotubes; may include only semiconductor nanotubes. Contact 10070 electrical properties may be optimized by the type of thin nanotube article 10065 used and the properties of carbon element 10060. Nanotube article 10065 may be relatively thin in the range of 1-20 nm for example, or relatively thick in the range of 20 to 200 nm for example.
As is the case with NV NT switch structure 10000′ described further above, NV NT switch structure 10000″ may enhance the performance of NV NT switch 10015-3 because lower operating voltage may be used as described further above with respect to NV NT switch 10015-1 and 10015-2.
For example, note that a nanoscopic trace stack 9750A-based NV NT switch illustrated in
Specifically, N-NAND memory array 10100 includes a first bit line BL1, a reference line REF, write lines corresponding to each cell WL1-WL4 and corresponding switch regions SW1-SW4. The stud vias form electrical connections to corresponding N+ diffusions of underlying FETs TR1-TR4, respectively. The select line SL1 enables an electrical connection between bit line BL1 and a contact on one side of the N-NAND array structure by activating transistor TRS1. The select line SL2 enables an electrical connection between reference line REF and a contact on the other side of the N-NAND array structure by activating transistor TRS2. Note that it is also possible to connect one side (contact) of the NAND array directly to reference line REF and eliminate select line SL2 and transistor TRS2. While only a first bit line BL1 is illustrated in
In the present embodiment, nonvolatile cross point switch array 10200 includes a NV carbon nanoscopic element stack 10250 etched to form discrete integrated programmable logic switches 10205 at the intersection of upper conductor traces 10220 and bottom conductor traces 10230. Cross point switch array 10200 includes a substrate 10260 in which bottom conductive traces 10230 are embedded. The bottom conductive traces may comprise, for example, a first logic wiring layer. Disposed above the bottom conductive traces are upper conductive traces 10220 which may comprise, for example a second logic wiring layer. In nonvolatile cross point switch array 10200, the bottom and upper conductive traces 10220 and 10230, are arranged approximately perpendicularly, with respect to the x-y plane (shown), but any number of other configurations may be suitable in other contexts. In the present example, each of the bottom and upper conductive traces 10230, 10220, intersect in a vertical region (along z-axis) where a discrete nanoscopic element stack 10250 is disposed.
The discrete nanoscopic element stack 10250, at each such intersection, forms an active region between the bottom and upper conductive traces 10230, 10220, providing a vertical conductive pathway between the bottom and upper conductive traces. This vertical conductive pathway can be formed and unformed (corresponding to a low and high resistance path) between conductive traces. In this example, discrete nanoscopic element stack 10250 is formed with carbon element 10255 on top of nanotube element 10245 with the top surface of carbon element 10255 in contact with the bottom surface of conductive traces 10220 and the bottom surface of nanotube element 10245 in contact with the top surface of conductive traces 10230. Cross point switch array 10200 and variation on it are described in detail in U.S. Provisional Patent Application 61/074,241.
Switching mechanisms for the vertical conductive pathway are described fully in incorporated U.S. patent application Ser. No. 11/835,613, entitled “Memory Elements and Cross Point Switches and Arrays of Same Using Nonvolatile Nanotube Blocks,” incorporated by reference in its entirety. Each bit line—word line combination (e.g. bottom and top conductive trace) selects a discrete nanoscopic element stack 10250, the active region of a discrete integrated programmable logic switch 10250, thereby selecting a discrete nanotube memory cell in cross point switch array 10200. The resistance state of each nanoscopic element stack 10250 may thus be programmed to represent a memory state of each nonvolatile cross point switch used for logic signal routing. Multi-resistance states (values) may be used to generate multiple logic weighting states programmed into the same NV nanoscopic element stack. As an example, one low resistance state and one high resistance state may be used to represent an activated routing path and an unactivated routing path, respectively. Alternately, three low resistance states and one high resistance state may be used to store three logic weighting factors and one no connect represented as logical 00, logical 01, logical 10, and logical 11 states. More logic weighting states are possible using more resistance states. In fact, any resistance value may be set between a lowest and a highest value such that an analog (continuously varying) resistance state or resistance ratio with other resistor (or impedance) function may be achieved. U.S. patent application Ser. No. 11/835,612 illustrates NRAM® memories with multi-resistance states per nonvolatile nanotube storage location. Similar techniques may be used to generate multiple logic weighting states. The electrical signals for programming the weighting factor of each logic routing path is formed by altering the resistance state for each NV nanoscopic carbon element are as described fully in the incorporated references and may be selected according the various requirements of the particular application.
Constructed with nanoscopic element stack 10250 that corresponds to nanoscopic element stack 9650 to form programmable logic switch 10205, and cross point switch array 10200 is capable of being SET and RESET at lower voltages than analogous cross point switch arrays using primarily nanotube material. The programmable logic switch 10205 (dashed outline of switching region 10250 and corresponding regions of top and bottom lines 10230, 10220) can be SET and RESET to ON or OFF states multiple times for programmable wiring. The switching function of each adjacent cell is largely independent but may experience certain amounts of capacitive coupling. Capacitive coupling at the intersection between approximately orthogonal conductors can cause unwanted noise coupling between adjacent lines and is factored into cross point switch design.
Switching element 10205 can be made of a thicker or thinner nanoscopic element stack 10250 to minimize coupling noise as needed. The thickness of carbon element 10255 and nanotube element 10245 that comprise nanoscopic element stack 10250 may be adjusted independently to minimize coupling noise as needed and each can be varied in thickness between approximately 2-5 nm to approximately 500 nm, for example, based on capacitance coupling considerations without inhibiting or compromising the switch operation. As noted above, the use of the nanoscopic element stack 9650A-I-type switching material show in
Multi-resistance states (values) may also be used to generate multiple logic weighting states programmed into the same NV nanoscopic carbon element as described further above with respect to cross point switch array 10200. Therefore, in addition to one low resistance state and one high resistance state that may be used to set a low voltage and a high voltage output, three low resistance states and one high resistance state may be used to store three logic weighting factors and one no connect represented as logical 00, logical 01, logical 10, and logical 11 states to output four voltage levels. For multi-level (greater that two in this example) voltage level outputs, a multilevel voltage sensing circuits (not shown) may replace NAND circuit 10310.
Methods of Fabricating NV NT Switches Using CNT Layers, Carbon NP Layers, and Various Non-carbon NP Layers
These methods for depositing non-carbon layers such as a thin insulator regions forming interface element 9535D in
Methods of Fabricating NV NT Switches Using Combinations of Carbon Layers, CNT Layers, Non-Carbon Interface Layers, and Atomic Species Implanted in Various Layers
Next, methods 10420 deposit a bottom contact layer of an electrically conducting material on a substrate with fabricated layers using known industry methods resulting in the structure illustrated in
At this point in the process, methods 10430 may optionally be used to deposit a carbon layer. In this example, a carbon nanotube layer is deposited directly on the top surface of bottom contact layer 10520 so optional methods 10430 are bypassed. However, methods 10430 corresponds to methods 10450 of carbon deposition described further below.
Next, methods 10440 deposits a carbon layer such as carbon nanotube (CNT) layer, or layers, from CNT dispersions in aqueous or non-aqueous solutions and deposit carbon nanotube layer 10530 on the top surface of bottom contact layer 10520 illustrated in
Alternately, method 10440 may include additional material between individual carbon nanotubes (CNTs) as described further above with respect to
Then, method 10450 deposit carbon layer 10540 on the top surface of carbon nanotube layer 10530 as illustrated in
Other methods 10450 of carbon layer deposition may include CVD (chemical vapor deposition) but typically at higher temperatures than for PECVD depositions. Methods 10450 also include PVD (physical vapor deposition), ebeam evaporation of a carbon source, spin-on of a carbon layer such as carbon black for example. PVD (physical vapor deposition) may be deposited at lower temperatures such as 200° C. for example and may be integrated with TiN PVD for example.
Still other methods 10450 of carbon layer deposition include PhECVD (photo-enhanced CVD) typically laser based. Also, microwave surface-wave plasma CVD, FCAD (filtered cathodic arc deposition) that may produce hydrogen-free carbon layers, and electroplating using tools such as those supplied by Semitool may be used. Deposition of a polymer coated layer and then carbonization (“burning”) to form a carbon layer may also be used.
At this point in the process, methods 10455 may optionally be used to deposit a sacrificial material layer. A sacrificial polymer layer is described further above with respect to deposition in
After the formation of carbon nanotube layer 10530 as described further above, methods 10455 forms a Ge layer by depositing a layer of Ge of approximately 5 nm to approximately 250 nm in thickness using rapid thermal processing (RTP) using industry LPCVD tools and methods, for example. Methods 10455 of Ge deposition may deposit a layer of polycrystalline Ge that penetrates a porous carbon nanotube layer such as carbon nanotube layer 10530 completely from top-to-bottom or may penetrate only the top portion of the carbon nanotube layer 10530 depending on the relative thickness of the Ge and carbon nanotube layers. Carbon nanotube layer 10530 volume is typically approximately 90% void with carbon nanotubes occupying approximately 10% of the volume.
Next, methods 10455 etch-back sufficient Ge to expose the top surface of the carbon nanotube layer such as carbon nanotube layer 10530 to ensure contact to the next layer, a top contact layer for example. A chlorine-based chemistry may be applied using reactive ion etch (RIE) industry tools and methods to remove a controlled amount of Ge. A sufficiently thick Ge layer remains within the carbon nanotube volume region to prevent top-to-bottom shorts when another layer is deposited. Examples of other layers that may be deposited are carbon, W, WN, TiN, TiCN, and other conductors and semiconductors illustrated with respect to step 10420 described further above.
At this point in the process, methods 10460 may optionally be used to deposit an interface layer. In this example, no interface layer is included in the structure and these optional fabrication steps are omitted. However, methods 10460 of depositing an interface layer corresponds to interface layer materials described further above in
Next, in this example, methods 10470 deposit top contact layer 10550 on the top surface of carbon layer 10540 as illustrated in
Alternately, methods 10470 may deposit a top contact conductive layer on the surface of a carbon nanotube layer such as carbon nanotube layer 10530 in
At this point in the process, photolithographic methods 10475 that pattern and etch corresponding to well known industry methods may be applied to layers 10560 of
At this point in the process, methods 10480 may optionally remove the sacrificial material if present in the structure. Methods 10480 is chosen to optimize the removal of a layer or layers of sacrificial material in the carbon nanotube layer. For purposes of illustration, it is assumed that a TiN top contact layer is in contact with the top surface of a carbon nanotube layer that includes sacrificial Ge material that needs to be removed and that a pattern has been formed in a masking layer on the top surface of the TiN contact layer.
Next, methods 10480 removes TiN using a chlorine-chemistry-based RIE process for example. This process is selective to carbon nanotubes and exposes the tops of the carbon nanotubes and the top surface of the Ge sacrificial layer. Dilute peroxide may be used to remove the Ge sacrificial material in the opening and below the TiN top contact region. Exposed portions of the carbon nanotube layer may be etched using methods disclosed in U.S. Pat. No. 6,835,591, filed Apr. 23, 2002, entitled “Methods of Nanotube Films and Articles,” the contents of which are incorporated reference in their entirety. Then, methods 10485 complete the fabrication of chips including additional contact and interconnect structures, passivation, and package interconnect terminals.
Methods 10475 for patterning and etching are introduced prior to methods 10485. However, there are examples where patterning and etching may be introduced later in the process. For example, a diode layer (a silicon-based PN junction diode for example) may be formed by applying silicon layers above the layers that form an underlying NV NT switch. In that case, methods may be used to pattern and etch to form PN diodes, and other etch methods may then continue to etch and form underlying NV NT switches in series with the PN diodes.
Ion implantation may be used to enhance performance by introducing various species (atoms and molecules) in any of the layers described above with respect to various methods of fabrication 10400. Ion implantation may be carried out after the deposition of a top contact layer for example. Ion implantation may also be carried out after patterning and etching. Ion implantation may also be carried out after deposition of a carbon nanotube layer such as carbon nanotube layer 10530. Examples of ion implanted regions in various elements corresponding to various layers are illustrated in
Methods of fabrication 10400 may be used to form various NV NT switch structures including various nanoscopic element stacks summarized in table 10600 shown in
Fabrication of NV NT switch 9600B (item # 2 in table 10600) and illustrated in
Fabrication of NV NT switch 9600D (item #3 in table 10600) and illustrated in
Fabrication of NV NT switch 9600E (item #4 in table 10600) and illustrated in
Fabrication of NV NT switch 5700B (item # 5 in table 10600) and illustrated in
Methods 10455 and 10480 are shown as dotted-Xs because the sacrificial material is removed and is not part of the final NV NT switch 5700B′ structure. NV NT block 5730′ in FIG. 57B′ is formed of only carbon nanotubes; however, top-to-bottom contacts may be more closely spaced because of the use of the sacrificial material. Combined with new methods of processing nanotube material and solution formation may make it easier to enhance the electrical characteristics of the carbon nanotube material such that it exhibit lower voltage switching at <5volts, lower currents for reset (set) of <50 μA, and tolerance of RTA temperatures of 750° C. for NV NT switch dimensions of <50 nm thereby enabling scaling of cells sizes to smaller dimensions.
While NV NT switch 5700B′ does not include any substantial amount of additional NP material in the carbon nanotube fabric region,
Fabrication of NV NT switch 9750A (item #6 in table 10600) and illustrated in
Ion implantation may be used to enhance performance by introducing various species (atoms and molecules) in any of the layers described above with respect to methods of fabrication 10400. Ion implantation may be carried out after the deposition of a top contact layer for example. Ion implantation may also be carried out after patterning and etching. Ion implantation may also be carried out after deposition of a carbon nanotube layer such as carbon nanotube layer 10530. Examples of ion implanted regions in various elements corresponding to various layers are illustrated in
Example Methods for Increasing CNT Fabric Resistance by Fabricating CNT Fabrics with Defects in the CNTs
CNTs used in forming CNT dispersions corresponding to methods 10440 illustrated in
Monitor wafers are used to monitor CNT fabric layer resistance per unit area using well known four-point probe resistance measuring techniques. What is observed for CNT dispersions with primarily multi-wall nanotubes (MWNTs) is that if CNTs are treated with a combination of nitric acid and sulfuric acid instead of just nitric acid, then the resistance per unit area for approximately the same thickness films is higher. CNT exposure to a stronger acid solution appears to increase defect in the CNTs which in turn increases resistance to current flow resulting in higher CNT fabric (nanofabric) resistance. Four-point probing of CNT fabric layers minimizes the effect of contact resistance between probes and CNT fabric layer so measured increase in per unit area resistance is primarily caused by an increase in the CNT fabric resistance. Additional CNT defects also are expected to reduce the maximum current carrying capacity of CNTs. The effects of reduced maximum current carrying capacity of CNTs may be observed in terms of reduced maximum switching currents from an ON to an OFF state for example.
Changing the type of CNTs can also change the sensitivity of CNTs to acid treatment. For example, if single wall nanotubes (SWNTs) are used to form CNT dispersions and deposited on monitor wafers using methods 10440 for example, then a similar increase in CNT fabric resistance is observed with just nitric acid treatment. In other words CNT dispersions formed primarily of SWNTs treated with nitric acid result in approximately the same CNT fabric resistance increase as CNT dispersions formed primarily of MWNTs and treated with nitric and sulfuric acid. Monitor wafer four point probe resistance increases are correlated with NV NT switch electrical test results such that NV NT switch voltages are less than or equal to 5 volts and reset currents are less than or equal to 40 μA. Higher defect levels may be used to achieve even lower switching voltages (less than 4 volts for example, and reset currents lower than 40 μA for example).
In addition to, or instead of, forming defects with increased acid (or other) CNT treatments, CNT defects can be introduced by ion implantation of CNT fabric layers before or after patterning. Examples of ion implantation used to change CNT fabric properties are described further above with respect to
Nanotube switches such as nanotube switch 4005 illustrated in
Since a lower overall switching voltage is applied across the two terminals of the nanotube switch, the maximum available switching current is reduced. Measuring switching reset currents (ON-to-OFF state), which are typically higher than set current (OFF-to-ON state), shows that the required NV NT switch switching current is reduced for higher nanotube fabric resistance (RCNT) switches. So the combination of lower applied switching voltage and higher NV NT switch resistance reduces the maximum available switching current. However, since defective CNTs require less current to switch from ON to OFF states for example, then these reduced nanotube switching currents are sufficient to cause switching. In other words, CNT defects resulting in higher CNT fabric resistance RCNT reduces the threshold for the switching current such that a lower switching current at a lower overall switching voltage across a higher resistance remains adequate for switching. Switching voltage and switching current measurements on sulfuric/nitride acid treated CNT-based switches show the following:
Tests were carried out on a 1024 bit 32×32 bit NRAM® memory test structure with FET select devices corresponding to
While a variety of reaction schemes can be used to produce the above-mentioned carbon nanotube materials and introduce defects in CNTs that form the nanofabric, a specific example is provided. The example is illustrative and should not be considered limiting, as a variety of other parameters can be favorably used by a one skilled in the art. In this example, 4-16 g of carbon nanotubes were mixed with 225-450 mL of 96% sulfuric acid and 150-300 ml of 70% nitric acid in a quartz reaction vessel. The volume ratio of sulfuric acid and nitric acid is 3:2. The addition of acids has to be done slowly and carefully to avoid excessive heat evolution. The quartz reaction vessel was attached to a reflux condenser and the reaction mixture was heated in oil bath set to 125-150° C. for 6 h.
In this example, after the acid reaction step, the CNT suspension in acid was diluted in 1% nitric acid (˜2 L) and taken through several passes of cross-flow filtration (CFF). The pH of the suspension is maintained at 1+/−0.3 during this process by recovering the material in 1% nitric acid after each step. Typically ten CFF are performed. After the CFF1 steps, the retentate was recovered in DI water and the pH of the nanotube:DI water suspension was increased to 9.0+/−0.5 with 29% ammonium hydroxide and sonicated. The CNT suspension in DI water was rendered optically homogeneous. This liquid was taken through another set of CFF passes (hereinafter referred as CFF2). CFF2 was performed until optical density of the permeate was about less than 0.035. After CFF2 process the retentate is collected in basic de-ionized water (pH 8.5+/−0.5) and sonicated for 60-120 min in a chilled sonicator bath (4-5° C.). If necessary the pH of the solution is adjusted to 8.5+/−0.5 during the sonication step. Finally, the solution was centrifuged about two or three times at about 37700 g for 30 min at 15° C. After centrifugation step, the supernatant was collected and used as the final CMOS grade applicator liquid.
Methods of Fabricating NV NT Switches using Processing on a Substrate and Off-line Processing Using a Handle Wafer
NV NT switch methods of fabrication to enhance NV NT switch performance with respect to methods of fabrication 10400 are illustrated in
Ion implantation may be used to optimize electrical characteristics of layers on handle wafers at various steps in the process prior to transfer of layers to substrates. Or ion implantation may be applied to various layers after completion of layer deposition, including a conductive layer, by varying the energy applied to various species of doping atoms.
Forming structures on handle wafers may be used to improve performance by characterizing handle wafers prior to transfer of structure to the substrate as described further below with respect to
Fabrication flow 10700 illustrated in
Methods 10800 illustrated in
Now turning to methods of fabrication 10900 shown in
At this point in the process, methods 10930 deposit one or more nanofabric layers on sacrificial polymer release layer 10730 to form nanofabric layer 10735 as shown in
Next, methods 10950 may deposit an adhesion promoting layer. Alternately, methods 10950 may be omitted and quarts handle wafer to substrate bonding (joining) may be carried out using methods 10840 described further below.
At this point in the process, quartz handle wafer 10725 and substrate 10710 are aligned and joined as described with respect to methods 10840. The alignment is non-critical because non-patterned layers are transferred. Patterning and etching occurs later in the process. However, for some applications it may be desirable to pattern and etch structures on the quarts handle wafer 10725 as described further below in which case alignment may be required. One alignment method is to alignment marks by using the transparency of the quartz handle wafer using known industry wafer-to-wafer alignment techniques that may be adapted for this application. For example, IC wafer alignment and bonding tools and corresponding processes create hydrophobic or hydrophilic surfaces using tools such as SST International Model 3180/3190, EV Group EVG501, SUSS Microtech ELAN CB6L and others for alignment and bonding. Accordingly, methods 10840 may use known industry methods of wafer-to-wafer bonding to join two or more wafers or substrates by creating hydrophobic or hydrophilic surfaces for example. After alignment and bonding, wafers and substrates may be held together by van de Waals forces for example. Alternately, wafers or wafers and substrates may be bonded with an adhesive layers.
Next, methods 10850 exposes sacrificial polymer release layer 10730 to UV radiation or to heat. Then, methods 10860 removes quartz handle wafer 10725 by holding substrate 10710 while mechanically lifting quarts handle wafer 10725 and leaving nanofabric layer 10735 in contact with bottom contact layer 10720. After removal, quartz handle wafer 10725 may be cleaned and reused.
Next, methods 10880 complete deposition of nanofabric layers which may include methods 10470 of depositing a top contact layer such as top contact layer 10550 described further above with respect to
Methods and structures corresponding to fabrication flow 10700 illustrated in
Now turning to methods of fabrication 10900, processing up to applying sacrificial polymer layer 10730 is the same as described with respect to
At this point in the process, nanofabric layers needed for a complete NV NT switch have been deposited on sacrificial polymer layer 10730 which is on the surface of quarts wafer 10725. At this point in the process, quartz handle wafer 10725 and substrate 10710 are aligned and joined as described with respect to methods 10840 and form stacked wafer 10785 as described further above with respect to stacked wafer 10740.
Next, methods 10850 and 10860 release and remove quartz handle wafer 10725, respectively, as described further above with respect to
Methods of Test and Burn-in of NV NT Switches and NV NT Switches Integrated with Other Devices
Test and burn-in methods for enhancing the performance of memory and other types of chips are well known in the industry. For example, burn-in and test methods are described in Bertin et al. patent U.S. Pat. No. 6,574,763 “Method and Apparatus for Semiconductor Integrated Circuit Testing and Burn-in” Jun. 3, 2003 hereby incorporated by reference and multi-chip testing on a wafer and then dicing and mounting chips for further evaluation is described in Bertin et al. U.S. Pat. No. 7,132,841 “Carrier for Test, Burn-in, and First Level Packaging” Nov. 7, 2006 hereby incorporated by reference in its entirety. The methods illustrated in U.S. Pat. No. 6,574,763 and U.S. Pat. No. 7,132,841 may be applied to NV NT switches and NV NT switches combined with other devices.
For example,
For purposes of illustration, handle wafer 11010 is assumed to be quarts handle wafer 11011 corresponding to handle wafer 10725 with added nanofabric layers as illustrated in
In one embodiment, a voltage at elevated temperature is applied to bottom conductor layer 10780 with respect to the top conductor layer 10770 then NV NT switches formed after wafer bonding, separation, pattern and etch are tested and compared (correlated) to applied voltage and temperature conditions.
In another embodiment, a few quarts handle wafers with nanofabric layers are patterned, tested, then burned-in, then tested and switch performance is measured. Quarts handle wafer batches are selected based on test and burn-in results for bonding to substrates as illustrated in
In yet another embodiment, NV NT switches or combinations of NV NT switches and other devices may be cut and mounted in packages for test and burn-in. In yet another embodiment, NV NT switches or combinations of NV NT switches and other devices may be patterned, tested, and burned-in for all quarts handle wafers. Only those quarts handle wafers passing test and burn-in requirements are bonded to substrate wafers. This embodiment may result in the best switch performance; however, alignment is more difficult than when transferring non-patterned wafers. Test and burn-in methods may be enhanced by incorporating device structures 11020 to assist in wafer-level, or in this case handle wafer-level, test and burn-in.
The various embodiments described further above may be used to test, burn-in, and select quarts handle wafers with NV NT switches that exhibit desired performance criteria such as lower voltage switching at <5 Volts, lower currents for reset (set) of <50 μA, and tolerance of high RTA temperatures of 750° C. for NV NT switch dimensions of <50 nm thereby enabling scaling of cells sizes to smaller dimensions. Also, process changes such as ion implantation for example may be evaluated to optimize NV NT switch electrical characteristic.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in respects as illustrative and not restrictive. For example, the 3D examples described further above may be used to form stand alone memory arrays. Alternatively, the 3D examples described further above may be used as embedded memory in logic chips. Also, 3D examples described further above may be stacked above one or more microprocessors in a logic chip such that address, timing, and data line lengths are mostly vertically oriented and short in distance for enhanced performance at lower power. Also, for example, many of the embodiments described above are described with reference to minimum technology node F. While it can be useful to fabricate memory elements at the smallest size allowed by the minimum technology node, embodiments can be fabricated at any size allowed by the minimum technology node (e.g., larger than the minimum feature size).
The following commonly-owned patent references, referred to herein as “incorporated patent references,” describe various techniques for creating nanotubes (nanotube fabric articles and switches), e.g., creating and patterning nanotube fabrics, and are incorporated by reference in their entireties:
Electromechanical Memory Array Using Nanotube Ribbons and Method for Making Same (U.S. patent application Ser. No. 09/915,093, now U.S. Pat. No. 6,919,592), filed on Jul. 25, 2001;
Electromechanical Memory Having Cell Selection Circuitry Constructed With Nanotube Technology (U.S. patent application Ser. No. 09/915,173, now U.S. Pat. No. 6,643,165), filed on Jul. 25, 2001;
Hybrid Circuit Having Nanotube Electromechanical Memory (U.S. patent application Ser. No. 09/915,095, now U.S. Pat. No. 6,574,130), filed on Jul. 25, 2001;
Electromechanical Three-Trace Junction Devices (U.S. patent application Ser. No. 10/033,323, now U.S. Pat. No. 6,911,682), filed on Dec. 28, 2001;
Methods of Making Electromechanical Three-Trace Junction Devices (U.S. patent application Ser. No. 10/033,032, now U.S. Pat. No. 6,784,028), filed on Dec. 28, 2001;
Nanotube Films and Articles (U.S. patent application Ser. No. 10/128,118, now U.S. Pat. No. 6,706,402), filed on Apr. 23, 2002;
Methods of Nanotube Films and Articles (U.S. patent application Ser. No. 10/128,117, now U.S. Pat. No. 6,835,591), filed Apr. 23, 2002;
Methods of Making Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. patent application Ser. No. 10/341,005), filed on Jan. 13, 2003;
Methods of Using Thin Metal Layers to Make Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. patent application Ser. No. 10/341,055), filed Jan. 13, 2003;
Methods of Using Pre-formed Nanotubes to Make Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. patent application Ser. No. 10/341,054), filed Jan. 13, 2003;
Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. patent application Ser. No. 10/341,130), filed Jan. 13, 2003;
Non-volatile Electromechanical Field Effect Devices and Circuits using Same and Methods of Forming Same (U.S. patent application Ser. No. 10/864,186, US Patent Publication No. 2005/0062035), filed Jun. 9, 2004;
Devices Having Horizontally-Disposed Nanofabric Articles and Methods of Making the Same, (U.S. patent application Ser. No. 10/776,059, US Patent Publication No. 2004/0181630), filed Feb. 11, 2004;
Devices Having Vertically-Disposed Nanofabric Articles and Methods of Making the Same (U.S. patent application Ser. No. 10/776,572, now U.S. Pat. No. 6,924,538), filed Feb. 11, 2004;
Patterned Nanoscopic Articles and Methods of Making the Same (U.S. patent application Ser. No. 10/936,119, now U.S. Pat. No. 7,416,993);
Nonvolatile Nanotube Programmable Logic Devices and a Nonvolatile Nanotube Field Programmable Gate Array Using Same (U.S. Provisional Patent Application No. 61/088,828), filed Aug. 14, 2008; and
NRAM Arrays With Nanotube Blocks, Nanotube Traces, and Nanotube Planes and Methods of Making Same, (U.S. Provisional Patent Application No. 61/074,241) filed Jun. 20, 2008.
This application is a continuation in part of and claims priority under 35 USC. §120 to U.S. patent application Ser. No. 12/273,807 entitled Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same, filed Nov. 19, 2008 which is a continuation-in-part of and claims priority under 35 USC. §120 to U.S. patent application Ser. No. 11/835,865 entitled Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same, filed Aug. 8, 2007 which is a continuation-in-part of and claims priority to the following applications, the entire contents of which are incorporated by reference: U.S. patent application Ser. No. 11/280,786, entitled “Two-Terminal Nanotube Devices And Systems And Methods Of Making Same,” filed Nov. 15, 2005; and U.S. patent application Ser. No. 11/274,967, entitled “Memory Arrays Using Nanotube Articles With Reprogrammable Resistance,” filed Nov. 15, 2005; and This application is related to the following applications, the entire contents of which are incorporated by reference: U.S. patent application Ser. No. 11/280,599, entitled “Non-Volatile Shadow Latch Using A Nanotube Switch,” filed Nov. 15, 2005. U.S. patent application Ser. No. 11/835,612, entitled “Nonvolatile Resistive Memories Having Scalable Two-Terminal Nanotube Switches,” filed Aug. 8, 2007; U.S. patent application Ser. No. 11/835,583, entitled “Latch Circuits and Operation Circuits Having Scalable Nonvolatile Nanotube Switches as Electronic Fuse Replacement Elements,” filed Aug. 8, 2007; U.S. patent application Ser. No. 11/835,651, entitled “Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same,” filed Aug. 8, 2007; U.S. patent application Ser. No. 11/835,759, entitled “Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same,” filed Aug. 8, 2007; U.S. patent application Ser. No. 11/835,845, entitled “Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same,” filed Aug. 8, 2007; U.S. patent application Ser. No. 11/835,852, entitled “Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same,” filed Aug. 8, 2007; U.S. patent application Ser. No. 11/835,856, entitled “Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same,” filed Aug. 8, 2007; U.S. patent application Ser. No. 12/195,675, entitled “Patterned Nanoscopic Articles and Methods of Making Same,” filed Aug. 21, 2008; and U.S. Provisional Patent Application No. 61/074,241, entitled “NRAM Arrays with Nanotube Blocks, Nanotube Traces, and Nanotube Planes and Methods of Making Same,” filed Jun. 20, 2008.
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