OPTICAL DEVICE

BACKGROUND
1. Technical Field

The present disclosure relates generally to an optical device.

2. Description of the Related Art

Silicon photonics and optical engines with integration of at least an electronic IC (EIC) and a photonic IC (PIC) have advantages of high transmission speed and low power loss and thus are applied in various areas. The electronic ICs or dies may be formed in a package followed by each of the electronic ICs or dies flip-chip bonding to a photonic IC or die, and an ASIC may be arranged with the electronic ICs or dies in a side-by-side fashion. Therefore, the transmission path between the electronic ICs and the ASIC may be relatively long.

SUMMARY

In one or more embodiments, an optical device includes a processing component, a first electronic component, a second electronic component, a first pillar, and an encapsulant. The first electronic component is disposed over and electrically connected to the processing component. The second electronic component is disposed over the processing component and electrically connected to the first electronic component. The first pillar is disposed between the first electronic component and the second electronic component and electrically connected to the processing component. The encapsulant is disposed over the processing component. The encapsulant encapsulates the first electronic component, the second electronic component, and the first pillar.

In one or more embodiments, an optical device includes a processing component, a first electronic component, and a plurality of second electronic components. The first electronic component is disposed over and electrically connected to the processing component. The second electronic components is disposed over and electrically connected to the processing component. The second electronic components are disposed adjacent to the first electronic component.

In one or more embodiments, an optical device includes a processing component, a first electronic component, and a first pillar. The first electronic component is disposed over and electrically connected to the processing component. The first pillar is disposed around the processing component and configured to transmit a power to the processing component and the first electronic component.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is noted that various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 2 illustrates a cross-sectional view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 3 illustrates a cross-sectional view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 4 illustrates a cross-sectional view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 5A illustrates a top view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 5B illustrates a top view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 5C illustrates a top view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 5D illustrates a top view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 6 illustrates a cross-sectional view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 7A illustrates a cross-sectional view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 7B illustrates a cross-sectional view of an optical device in accordance with some embodiments of the present disclosure;

FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, and FIG. 8E illustrate various operations in a method of manufacturing an optical device in accordance with some embodiments of the present disclosure; and

FIG. 9A, FIG. 9B, FIG. 9C, FIG. 9D, and FIG. 9E illustrate various operations in a method of manufacturing an optical device in accordance with some embodiments of the present disclosure.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1 illustrates a cross-sectional view of an optical device 1 in accordance with some embodiments of the present disclosure. The optical device 1 includes a carrier 10, components 20, and 32, a photonic component 40, one or more optical fiber array components 42, pillars 50, 52, 60 and 62, redistribution layers (RDLs) 70, 72 and 74, an adhesive layer 91, encapsulants 710 and 730, connection elements 940, and electrical contacts 930.

The carrier 10 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The carrier 10 may include an interconnection structure, which may include such as a plurality of conductive traces and/or a plurality of conductive vias. The interconnection structure may include a redistribution layer (RDL) and/or a grounding element. In some embodiments, the carrier 10 includes a ceramic material or a metal plate. In some embodiments, the carrier 10 may include a substrate, such as an organic substrate or a leadframe. In some embodiments, the carrier 10 may include a two-layer substrate which includes a core layer and a conductive material and/or structure disposed on an upper surface and a bottom surface of the carrier 10. The conductive material and/or structure may include a plurality of traces. The carrier may include one or more conductive pads in proximity to, adjacent to, or embedded in and exposed at an upper surface and/or a bottom surface of the carrier 10. The carrier 10 may include a solder resist (not shown) on the upper surface and/or the bottom surface of the carrier 10 to fully expose or to expose at least a portion of the conductive pads for electrical connections. In some embodiments, the carrier 10 supports the component 20.

The component 20 may be disposed over the carrier 10. In some embodiments, the component 20 includes an electronic component, such as an electronic IC (EIC). In some embodiments, the component 20 includes a processing component (e.g., ASICs, FPGAs, GPUs, or the like).

The component 30 may be disposed over the component 20. In some embodiments, the component 30 is disposed over and electrically connected to the component 20. In some embodiments, an active surface 301 of the component 30 is bonded to an active surface 201 of the component 20. In some embodiments, the component 30 includes an electronic component, such as an EIC. In some embodiments, the component 30 includes an integrated digital signal processor (DSP). The integrated DSP may include a plurality of DSP units. For example, each of the DSP units may be divided from a monolithic optical engine, and the integrated DSP includes a plurality of DSP units divided or originated from a plurality of optical engines. In some embodiments, each of the DSP units of the component 30 may electrically connect to a corresponding one of the components 32, respectively.

The optical device 1 may include one or more components 32. The component 32 may be disposed over the component 20. In some embodiments, the components 32 are disposed over and electrically connected to the component 20. In some embodiments, the components 32 are electrically connected to the component 30. In some embodiments, the components 32 are disposed adjacent to the component 30 from a top view perspective. In some embodiments, the components 32 are disposed around the component 30 from a top view perspective. In some embodiments, the components 32 are disposed adjacent to at least two sides of the component 30 from a top view perspective. In some embodiments, the components 32 surround the component 30 from a top view perspective. In some embodiments, the components 32 include electronic components, such as EICs. In some embodiments, one or more of the components 32 may include an integrated component including a plurality of electro-optical units (or chiplets). The electro-optical units may include at least one transimpedance amplifier (TIA) unit, at least one driver (DRV) unit, or a combination thereof. For example, each of the TIA units and each of the DRV units may be divided from a monolithic optical engine, and the integrated component includes a plurality of TIA units and/or DRV units divided or originated from a plurality of optical engines.

The photonic component 40 may be disposed over the component 30. The photonic component 40 may be or include a photonic IC (PIC). The photonic component 40 may include an integrated component including a plurality of photonic units. For example, each of the photonic units may be divided from a monolithic optical engine, and the integrated component includes a plurality of photonic units divided or originated from a plurality of optical engines. In some embodiments, each of the photonic units of the photonic component 40 is coupled to a corresponding one of the optical fiber array components 42, respectively. The photonic component 40 may be disposed over the component 32. In some embodiments, the photonic component 40 has a region 40R exposed by the component 30. In some embodiments, a projection of the component 30, projections of the components 32, and a projection of the component 20 are located within a range covered by the photonic component 40 from a top view perspective.

The optical fiber array component 42 may be connected to the photonic component 40. The optical fiber array component 42 may be connected to the photonic component 40 through a waveguide (not shown in FIG. 1). In some embodiments, the optical fiber array component 42 is disposed or received within the region 40R of the photonic component 40. In some embodiments, the optical fiber array component 42 includes an integrated component including a plurality of fiber array units (FAUs).

The optical device 1 may include one or more pillars 50. The pillars 50 may be conductive pillars or electrically conductive pillars. In some embodiments, the pillar 50 is disposed around the component 30. In some embodiments, the pillar 50 is adjacent to the component 30. In some embodiments, the pillar 50 is adjacent to the component 32. In some embodiments, the pillar is disposed between the component 30 and the component 32 and electrically connected to the component 20. In some embodiments, the pillar 50 is connecting to the component 20. The pillar may include a conductive material such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.

The optical device 1 may include one or more pillars 52. The pillars 52 may be conductive pillars or electrically conductive pillars. In some embodiments, the pillar 52 is disposed around the component 30. In some embodiments, the pillar 52 is disposed adjacent to the component 32. In some embodiments, the pillar 52 is disposed around the component 32. In some embodiments, the pillar 52 is electrically connected to the component 20. The pillar 52 may include a conductive material such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.

The optical device 1 may include one or more pillars 60. The pillars 60 may be conductive pillars or electrically conductive pillars. In some embodiments, the pillar 60 is disposed adjacent to the component 20. In some embodiments, the pillar 60 is disposed around the component 20. In some embodiments, the pillar 60 is electrically connected to the pillar 50. In some embodiments, the pillar 60 is electrically connected to the pillar 52. In some embodiments, the pillar 60 is configured to transmit a power. In some embodiments, the pillar 60 is configured to transmit a power to the components 20 and 30. The pillar 60 may include a conductive material such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.

The optical device 1 may include one or more pillars 62. The pillars 62 may be conductive pillars or electrically conductive pillars. In some embodiments, the pillar 62 is between the component 20 and the components 30 and 32. In some embodiments, the pillar 62 is electrically connected to the component 20 and the components 30 and 32. In some embodiments, the pillar 62 is configured to transmit an electrical signal between the component 20 and the component 30. The pillar 62 may include a conductive material such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.

The RDL 70 may be between the component 20 and the component 30. The RDL 70 may be or include a circuit layer. In some embodiments, the component 20 is electrically connected to the component 30 through the RDL 70. The RDL 70 may be between the component 20 and the component 32. In some embodiments, the RDL 70 electrically connects the pillar 50 and the pillar 60. In some embodiments, the pillar 52 is disposed over and electrically connected to the RDL 70. In some embodiments, the RDL 70 electrically connects the pillar 52 and the pillar 60. In some embodiments, the pillar 52 connects to the pillar 60 through the RDL 70. In some embodiments, a projection of the pillar 52 at least partially overlaps a projection of the pillar 60 from a top view perspective. In some embodiments, a projection of the pillar 52 on the carrier 10 and a projection of the pillar 60 on the carrier 10 overlap from a top view perspective.

In some embodiments, the RDL 70 includes a first part and a second part. In some embodiments, the RDL 70 includes conductive patterns or conductive structures, and the first part and the second part are different ones of the conductive patterns or conductive structures of the RDL 70. For example, the RDL 70 may include a first conductive pattern (or a first conductive structure) as the first part and a second conductive pattern (or a second conductive structure) as the second part. In some embodiments, the first part of the RDL 70 is free from overlapping or contacting the second part of the RDL 70. In some embodiments, the first part of the RDL 70 is physically spaced apart from the second part of the RDL 70. In some embodiments, the first part of the RDL 70 is configured to transmit a power to the component 20 or the component 30. In some embodiments, the second part of the RDL 70 is configured to transmit an electrical signal between the component 20 and the component 30. In some embodiments, the first part of the RDL is electrically insulated from the second part of the RDL 70.

In some embodiments, an active surface 201 of the component 20 is electrically connected to the RDL 70. In some embodiments, an active surface 301 of the component 30 and an active surface 321 of the component 32 are electrically connected to the RDL 70. In some embodiments, an active surface 401 of the photonic component 40 is electrically connected to the RDL 70. In some embodiments, the pillar 62 is between the RDL 70 and the component 20. The RDL 70 may include a plurality of dielectric layers, a plurality of conductive layers in the dielectric layers, and a plurality of conductive vias connecting the conductive layers. According to some embodiments of the present disclosure, with the aforesaid design of the active surface 301 and the active surface 321 directly electrically connected to the RDL 70, an electrical transmission path between the component 30 and the component 32 can be reduced, and thus the transmission speed can be increased.

The RDL 72 may be disposed over the components 30 and 32. The RDL 72 may be or include a circuit layer. In some embodiments, a backside surface 302 (or a passive surface) of the component 30 and a backside surface 322 (or a passive surface) of the component 32 are spaced apart from the RDL 72. In some embodiments, the RDL 72 is electrically connected to the pillar 50. In some embodiments, the RDL 72 is electrically connected to the photonic component 40. In some embodiments, the RDL 72 is electrically connected to the RDL 70 through the pillar 50. In some embodiments, the pillar 50 is configured to transmit a power from the pillar 60 to the RDL 72. In some embodiments, the RDL 72 is electrically connected to the RDL 70 through the pillar 52. In some embodiments, the pillar 52 is configured to transmit a power from the pillar 60 to the RDL 72. The RDL 72 may include a plurality of dielectric layers, a plurality of conductive layers in the dielectric layers, and a plurality of conductive vias connecting the conductive layers.

The RDL 74 may be disposed under or below the component 20. The RDL 74 may be or include a circuit layer. In some embodiments, the RDL 74 is disposed between the carrier 10 and the component 20. In some embodiments, the RDL 74 is electrically connected to the pillar 60. In some embodiments, the RDL 74 is electrically connected to the RDL 72. The RDL 74 may include a plurality of dielectric layers, a plurality of conductive layers in the dielectric layers, and a plurality of conductive vias connecting the conductive layers. In some embodiments, the pillar is configured to transmit a power form the RDL 74 to the RDL 72.

The adhesive layer 91 may be between the component 20 and the carrier 10. In some embodiments, the component 20 is adhered to the RDL 74 through the adhesive layer 91. In some embodiments, the adhesive layer 91 contacts a backside surface 202 (or a passive surface) of the component 20. In some embodiments, the adhesive layer 91 directly contacts the component 20 and the RDL 74. In some embodiments, the adhesive layer 91 includes a die attach film (DAF). In some embodiments, the adhesive layer 91 includes a thermal interface material (TIM). In some embodiments, the RDL 74 includes dummy conductive portions (e.g., dummy conductive patterned layers, dummy conductive vias, dummy conductive pads, or the like) that are free from electrically connecting to any component. In some embodiments, the dummy conductive portions of the RDL 74 are directly under the adhesive layer 91. In some embodiments, the dummy conductive portions of the RDL 74 directly contact the adhesive layer 91.

The encapsulant 710 may be between the RDL 70 and the RDL 74. In some embodiments, the encapsulant 710 covers or encapsulates the component 20 and the pillars 60 and 62. The encapsulant 710 may include an epoxy resin having fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination thereof.

The encapsulant 730 may be disposed over the component 20. The encapsulant 730 may be between the RDL 70 and the RDL 72. In some embodiments, the encapsulant 730 covers or encapsulates the components 30 and 32 and the pillars 50 and 52. The encapsulant 730 may include an epoxy resin having fillers, a molding compound (e.g., an epoxy molding compound or other molding compound), polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination thereof.

The electrical contacts 930 may be between the carrier 10 and the component 20. In some embodiments, the electrical contacts 930 electrically connect the RDL 74 to the carrier 10. In some embodiments, the electrical contacts 930 electrically connect to the RDL 74 through conductive pads 932. The electrical contacts 930 may include controlled collapse chip connection (C4) bumps, a ball grid array (BGA) or a land grid array (LGA). The conductive pads 932 may include one or more conductive materials such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.

The connection elements 940 may be between the photonic component 40 and the components 30 and 32. In some embodiments, the connection elements 940 electrically connect the photonic component 40 to the RDL 72. In some embodiments, the connection elements 940 electrically connect the photonic component 40 to the RDL 72 through conductive pads 942 and 944. The connection elements 940 may include conductive bumps. The connection elements 940 and the conductive pads 942 and 944 may include one or more conductive materials such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.

In some embodiments, the pillar 60 is configured to provide a power path P1. In some embodiments, the power path P1 passes through the carrier 10, the RDL 74, and the pillar 60. In some embodiments, the power path P1 further passes through the electrical contacts 930 and the conductive pads 932. In some embodiments, the power path P1 passes through the pillars 60 and 52. In some embodiments, the power path P1 passes through the pillars 60 and 50. In some embodiments, the power path P1 further passes through the first part of the RDL 70. The power path P1 may be configured to supply or transmit power to the components 20, 30, and 32. The power path P1 may further pass through the connection element 940 to supply or transmit power to the photonic component 40.

In some embodiments, the RDL 70 is configured to provide vertical electrical connection between the component 20 (e.g., ASIC) and the components 30 and 32 (e.g., EICs) stacked over the component 20. In some embodiments, the RDL 70 (e.g., the second part of the RDL 70) is configured to provide a signal path E1. In some embodiments, the signal path E1 passes through the second part of the RDL 70 and the pillar 62. An electrical signal may be transmitted between the component 20 (e.g. ASIC) and the component 30 (e.g., DSP) through the signal path E1.

In some embodiments, the signal path E1 passes through the optical fiber array component 42, the photonic component 40, the connection element 940, the RDL 72, the pillar 52, the RDL 70, the component 32 (e.g., including one or more TIA units), the RDL 70, the component (e.g., including one or more DSP units), the RDL 70, the pillar 62, the component 20 (e.g., the processing component), the pillar 62, the RDL 70, the component 30, the RDL 70, the component 32 (e.g., including one or more DRV units), the RDL 70, the pillar 50, the RDL 72, the connection element 940, the photonic component 40, and the optical fiber array component 42. The photonic component 40 may convert an optical signal to an electrical signal and transmit the electrical signal to the component 32 (e.g., TIA) through the signal path E1. An electrical signal may be transmitted from the component 32 to the component 30 (e.g., DSP) through the signal path E1, and an electrical signal may be transmitted between the component 30 and the component 32 through the signal path E1. An electrical signal may be transmitted from the component 32 (e.g., DRV) to the photonic component 40 through the signal path E1.

In some cases wherein an ASIC is arranged with EICs in a side-by-side fashion, the ASIC and the EICs are electrically connected to each other through a substrate or an interposer disposed underneath. The transmission path between the EICs and the ASIC may be relatively long, the relatively long transmission path may increase the possibility of distortion of signals, and the device area is relatively large. In contrast, according to some embodiments of the present disclosure, with the design of the vertical electrical connection between the component 20 and the components 30 and 32 stacked over the component 20, the transmission path is significantly reduced, thereby the resistance of the transmission path is significantly reduced, and thus the electrical performance of the optical device 1 can be improved. In addition, the device area in horizontal direction (e.g., x-y plane) can be reduced as well.

In addition, according to some embodiments of the present disclosure, with the design of the active surface 301 of the component 30 bonded to the active surface 201 of the component 20, due to the reduced distance between the active surface 301 of the component 30 (e.g., DSP) and the active surface 201 of the component 20 (e.g., ASIC), the pitch of the electrical connection structure (e.g., the RDL 70 and/or the pillars 62) therebetween can be reduced significantly. As such, the number of connection terminals or ports can be increased, individual signals can be transmitted through respective terminals or ports (also referred to as “a parallel interface”), instead of multiple signals sharing the same terminal or port (also referred to as “a serial electrical interface”). Therefore, additional electrical connection element (e.g., a SERDES device) is not required for assisting the electrical connection between the component 20 and the component 30, and the manufacturing cost can be reduced as well.

In addition, according to some embodiments of the present disclosure, with the design of the adhesive layer 91 including a TIM and between the component 20 and the electrical contacts 930, heat may be dissipated from the component 20 towards the carrier 10 more efficiently. Moreover, according to some embodiments of the present disclosure, with the design of the dummy conductive portions of the RDL 74 directly under the adhesive layer 91, heat dissipation effect may be further improved.

Moreover, in some cases where a plurality of optical engines each including at least a TIA, a DRV, a DSP, and a PIC are arranged around multiple sides of an ASIC, the transmission paths may be relatively long, and each optical engine requires a die attach operation to be connected to the ASIC. In contrast, according to some embodiments of the present disclosure, with the design of integrating a plurality of DSP units into the component 30, integrating a plurality of electro-optical units (e.g., TIA units and/or DRV units) into the component 32, and integrating a plurality of photonic units into the photonic component 40, the number of components 30 and 32 and the photonic component 40 can be reduced, and thus the number of the electrical connection structures as well as die attach operations can be reduced, so as to simplify the structure as well as the manufacturing process of the optical device 1. For example, a plurality of DSP units can be integrated into one component 30 which can be stacked over the component 20, thus the transmission path can be reduced as mentioned above, the number of components in the optical device 1 can be reduced, and the costs can be reduced. Besides, with the number of the photonic component 40 being reduced, the number of FAUs can be reduced, and thus the number of the waveguide can be reduced, so as to further simplify the structure as well as the manufacturing process of the optical device 1.

In some embodiments, a wafer node of EICs is less than about 16 nm, and a wafer node of PICs is about 45 nm or 90 nm. According to some embodiments of the present disclosure, with the design of the components 20, 30, and 32 including integrated EIC units and the photonic component 40 including integrated PIC units, the components 20, 30, and 32 and the photonic component 40 are manufactured separately prior to being bonded into the optical device 1. For example, the photonic component 40 having a relatively large wafer node and the component 30 having a relatively small wafer node can be manufactured separately prior to being bonded to each other. Therefore, the flexibility of the manufacturing process is increased, and the yield can be increased as well.

FIG. 2 illustrates a cross-sectional view of an optical device 2 in accordance with some embodiments of the present disclosure. The optical device 2 is similar to the optical device 1 in FIG. 1, and the differences therebetween are described as follows.

In some embodiments, the active surface 321 of the component 32 is electrically connected to the RDL 72. In some embodiments, the active surface 321 of the component 32 is electrically connected to the RDL 72 through pillars 66. The pillars 66 may be conductive pillars or electrically conductive pillars. In some embodiments, the pillars 66 are covered or encapsulated by the encapsulant 730.

According to some embodiments of the present disclosure, the active surface 301 is directly electrically connected to the RDL 70, and the active surface 321 is directly electrically connected to the RDL 70, e.g., through the pillars 62. Therefore, an electrical transmission path between the component 30 and the component 32 can be reduced, and thus the transmission speed can be increased.

FIG. 3 illustrates a cross-sectional view of an optical device 3 in accordance with some embodiments of the present disclosure. The optical device 3 is similar to the optical device 1 in FIG. 1, and the differences therebetween are described as follows.

In some embodiments, the active surface 201 of the component 20 is electrically connected to the RDL 74. In some embodiments, the active surface 201 of the component 20 is electrically connected to the RDL 74 through pillars 64. The pillars 64 may be conductive pillars or electrically conductive pillars. In some embodiments, the pillars 64 are covered or encapsulated by the encapsulant 710.

In some embodiments, the pillars 64 are between the component 20 and the RDL 74 and configured to provide a signal path E2. In some embodiments, the signal path E2 passes through the component 20, the pillar 64, the RDL 74, the pillar 60, the RDL 70, the component 30 (e.g., DSP), the RDL 70, the component 32 (e.g., DRV), the RDL 70, and the pillar 50. The photonic component 40 may convert an optical signal to an electrical signal and transmit the electrical signal to the component 32 (e.g., TIA) through a portion of the signal path E1 (not shown in FIG. 3, please refer to FIG. 1). The portion of the signal path E1 may pass through the optical fiber array component 42, the photonic component 40, the connection element 940, the RDL 72, the pillar 52, the RDL 70, and the component 32, as illustrated in FIG. 1. An electrical signal may be transmitted from the component 32 to the component 30 (e.g., DSP) through a portion of the signal path E1 which may pass through the RDL 70 (e.g., the second part of the RDL 70). An electrical signal may be transmitted between the component 20 and the component 30 through a portion of the signal path E2 which passes through the RDL 70 (e.g., the second part of the RDL the pillar 60, the RDL 74, and the pillar 64. An electrical signal may be transmitted between the component 20 and the photonic component 40 through the signal path E2. In some embodiments, the component 20 may dissipate heat towards the carrier 10 through the pillars 64.

According to some embodiments of the present disclosure, with the design of the active surface 201 of the component 20 being electrically connected to the carrier 10 through the pillars 64 and the RDL 74, the heat dissipation from the component 20 the carrier 10 can be further improved.

FIG. 4 illustrates a cross-sectional view of an optical device 4 in accordance with some embodiments of the present disclosure. The optical device 4 is similar to the optical device 3 in FIG. 3, and the differences therebetween are described as follows.

In some embodiments, the active surface 321 of the component 32 is electrically connected to the RDL 72. In some embodiments, the backside surface 322 of the component 32 is spaced apart from the RDL 70. According to some embodiments of the present disclosure, with the design of the active surface 201 of the component 20 being electrically connected to the carrier through the pillars 64 and the RDL 74, the heat dissipation from the component 20 the carrier can be further improved.

FIG. 5A illustrates a top view of an optical device 5A in accordance with some embodiments of the present disclosure. In some embodiments, a cross-sectional view of the optical device 5A along the cross-sectional line 5A-5A′ may show a cross-sectional structure as illustrated in any one of the structures in FIGS. 1-4. The optical device 5A is similar to the optical device 1 in FIG. 1, and the differences therebetween are described as follows.

In some embodiments, the optical device 5A includes a plurality of components 30 and a plurality of components 32. In some embodiments, each of the components 32 includes a set of one TIA unit and one DRV unit, and each of the components 30 includes a DSP unit. In some embodiments, each of the DSP units (or the component 30) may be corresponding to one component 32. In some embodiments, the components 30 and the components 32 are located within a projection of the component 20 from a top view perspective. In some embodiments, each of the optical fiber components 42 includes integrated FAUs and a waveguide 42W.

FIG. 5B illustrates a top view of an optical device 5B in accordance with some embodiments of the present disclosure. In some embodiments, a cross-sectional view of the optical device 5B along the cross-sectional line 5B-5B′ may show a cross-sectional structure as illustrated in any one of the structures in FIGS. 1-4. The optical device 5B is similar to the optical device 5A in FIG. 5A, and the differences therebetween are described as follows.

In some embodiments, each of the components 32 includes a set of one TIA unit and one DRV unit, and the component 30 includes integrated DSP units. In some embodiments, the component 30 and the components 32 are located within a projection of the component 20 from a top view perspective. In some embodiments, each of the optical fiber components 42 includes integrated FAUs and a waveguide 42W.

FIG. 5C illustrates a top view of an optical device 5C in accordance with some embodiments of the present disclosure. In some embodiments, a cross-sectional view of the optical device 5C along the cross-sectional line 5C-5C′ may show a cross-sectional structure as illustrated in any one of the structures in FIGS. 1-4. The optical device 5C is similar to the optical device 5A in FIG. 5A, and the differences therebetween are described as follows.

In some embodiments, the optical device 5C includes a plurality of components 32 and 32′. In some embodiments, the components 32 and 32′ include a plurality of electro-optical chiplets. In some embodiments, each of the components 32 includes integrated DRV units, and each of the components 32′ includes integrated TIA units. In some other embodiments, each of the components 32 and 32′ includes a plurality sets of TIA units and DRV units. In some embodiments, the component 30 includes integrated DSP units. In some embodiments, each of the optical fiber components 42 includes integrated fiber array units (FAUs) and a waveguide 42W.

In some embodiments, the component 30 and the components 32 and 32′ are located within a projection of the component 20 from a top view perspective. The device area in horizontal direction (e.g., x-y plane) can be reduced.

FIG. 5D illustrates a top view of an optical device 5D in accordance with some embodiments of the present disclosure. In some embodiments, a cross-sectional view of the optical device 5D along the cross-sectional line 5D-5D′ may show a cross-sectional structure as illustrated in any one of the structures in FIGS. 1-4. The optical device 5D is similar to the optical device 5A in FIG. 5A, and the differences therebetween are described as follows.

In some embodiments, the optical device 5D includes a component 30, a plurality of components 32, and an optical fiber component 42. In some embodiments, each of the sides of the component 30 is arranged with one component 32. In some embodiments, each of the components 32 includes a plurality sets of TIA units and DRV units. In some embodiments, the component 30 includes integrated DSP units. In some embodiments, the optical fiber component 42 includes integrated FAUs and a waveguide 42W.

According to some embodiments of the present disclosure, with the design of integrating a plurality of FAUs into the optical fiber component 42, the number of separate FAUs can be reduced, and thus the number of the waveguide 42W can be reduced, so as to simplify the manufacturing process of the optical device 5C.

FIG. 6 illustrates a cross-sectional view of an optical device 6 in accordance with some embodiments of the present disclosure. The optical device 6 is similar to the optical device 1 in FIG. 1, and the differences therebetween are described as follows.

In some embodiments, the optical device 6 further includes a heat dissipation structure disposed over the photonic component 40. In some embodiments, the heat dissipation structure is configured to reduce a heat accumulation in the component 20. In some embodiments, the photonic component 40 dissipates heat along a first direction towards the heat dissipation structure in a first rate and dissipates heat along a second direction opposite to the first direction in a second rate less than the first rate. In some embodiments, a heat resistance of the heat from the photonic component 40 towards the heat dissipation structure 80 is less than a heat resistance of the heat from the photonic component 40 towards a direction opposite to the heat dissipation structure 80 (e.g., towards the carrier 10). In some embodiments, a heat dissipation path from the photonic component 40 towards the heat dissipation structure 80 is less than a heat dissipation path from the photonic component 40 towards the carrier 10. In some embodiments, a thermal conductivity of one or more materials passed by the heat dissipation path from the photonic component 40 towards the heat dissipation structure 80 is higher than a thermal conductivity of one or more materials passed by the heat dissipation path from the photonic component 40 towards the carrier 10. In some embodiments, the component 20 dissipates heat towards a direction opposite to the heat dissipation structure 80. In some embodiments, the component 20 dissipates heat towards the carrier 10.

According to some embodiments of the present disclosure, while heat may be easily accumulated within the stacked structure of the optical device 6, with the design of dissipating heats of the photonic component 40 and the component 20 towards different directions, heat dissipation of the optical device 6 may be further improved, and thereby the temperature of the optical device 6 can be reduced.

In addition, in some cases where an optical device does not include a heat dissipation structure, all of the heat generated by the processing component, the electronic components, and the photonic component is dissipated towards a carrier, and thus heat may be easily accumulated within the optical device. In contrast, according to some embodiments of the present disclosure, with the arrangement of the heat dissipation structure 80, the photonic component 40 may dissipate heat along a direction towards the heat dissipation structure 80 at a higher rate, through a shorter heat dissipation path, and/or through one or more materials that have a higher thermal conductivity than along a direction opposite to the direction towards to the heat dissipation structure 80. Therefore, heat dissipation of the optical device 6 may be further improved, for example, about 66% of the heat generated within the optical device 6 may be dissipated towards the heat dissipation structure 80, and thereby the temperature of the optical device 6 can be further reduced.

FIG. 7A illustrates a cross-sectional view of an optical device 7A in accordance with some embodiments of the present disclosure. The optical device 7A is similar to the optical device 3 in FIG. 3, and the differences therebetween are described as follows.

In some embodiments, the optical device 7A includes RDLs 70 and 70′ between the encapsulant 710 and the encapsulant 730. The RDL 70 is electrically connected to the RDL 70′ through a bump joint structure. The bump joint structure may include a plurality of conductive pillars 950, a plurality of conductive bumps 952, and a plurality of conductive pads 954.

In some embodiments, carrier 10 includes an interconnection structure 10r (or an RDL). In some embodiments, the RDL 74 is electrically connected to the carrier 10 through the electrical contacts 930 and conductive pads 934. Each of the conductive pads 934 may include a multi-layered structure including, for example, a conductive layer, a seed layer, and/or the like. In some embodiments, the optical device 7A further includes a plurality of electrical contacts 10c disposed under the carrier 10. The electrical contacts 10c may include controlled collapse chip connection (C4) bumps, a ball grid array (BGA) or a land grid array (LGA).

FIG. 7B illustrates a cross-sectional view of an optical device 7B in accordance with some embodiments of the present disclosure. The optical device 7B is similar to the optical device 7A in FIG. 7A, and the differences therebetween are described as follows.

In some embodiments, the optical device 7B further includes pillars 52′, RDLs 72′ and 76, an encapsulant 730′, and connection elements 960 and 962. In some embodiments, the RDL 76 is over the RDL 72′, the RDL 72′ is over the RDL 72, and the encapsulant 730′ is over the encapsulant 730. In some embodiments, the encapsulant 730 covers or encapsulates the component 30 and the pillars 52. In some embodiments, the encapsulant 730′ covers or encapsulates the components 32 and the pillars 52′ and 66.

In some embodiments, the RDLs 72 and 72′ are between the encapsulant 730 and the encapsulant 730′. In some embodiments, the RDL 72 is electrically connected to the RDL 72′ through the connection elements 960 and 962. The connection elements 960 may include conductive bumps, and the connection elements 962 may include conductive pads. In some embodiments, the photonic component 40 is electrically connected to the RDL 76 through the connection elements 940. According to some embodiments of the present disclosure, with the design of stacking the components 32 over the component 30, the size of the optical device 7B in a horizontal direction may be reduced.

FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, and FIG. 8E illustrate various operations in a method of manufacturing an optical device 1A in accordance with some embodiments of the present disclosure.

Referring to FIG. 8A, a component 20 may be provided, and pillars 62 may be formed on an active surface 201 of the component 20.

Referring to FIG. 8B, an RDL 74 may be formed on a carrier 10A, the component 20 may be adhered to the RDL 74 through an adhesive layer 91, pillars 60 may be formed on the RDL 74 adjacent to the component 20, and the component 20 and the pillars 60 and 62 may be encapsulated by an encapsulant 710. In some embodiments, a planarization process (e.g., a grinding operation) may be performed to planarized upper surfaces of the encapsulant 710 and the pillars 60 and 62.

Referring to FIG. 8C, an RDL 70 may be formed on the upper surfaces of the encapsulant 710 and the pillars 60 and 62.

Referring to FIG. 8D, components 30 and 32 may be bonded to the RDL 70, pillars 50 and 52 may be formed on the RDL 70, and the components 30 and 32 and the pillars 50 and 52 may be encapsulated by an encapsulant 730. In some embodiments, an active surface 301 of the component 30 and active surfaces 321 of the components 32 may be flip-chip bonded to the RDL 70. In some embodiments, a planarization process (e.g., a grinding operation) may be performed to planarized upper surfaces of the encapsulant 730 and the pillars 50 and 52.

Still referring to FIG. 8D, an RDL 72 may be formed on the upper surfaces of the encapsulant 730 and the pillars 50 and 52, and connection elements 940 may be formed on the RDL 72.

Referring to FIG. 8E, a photonic component 40 with optical fiber array components 42 may be bonded to the RDL 72 through the connection elements 940, an underfill 946 may be formed to cover the connection elements 940, the carrier 10A (shown in FIG. 8A) may be removed, and the as-formed structure may be bonded to a carrier 10 through electrical contacts 930. The carrier 10 may include an interconnection structure 10r and electrical contacts 10c. As such, the optical device 1A is formed.

In some embodiments, referring to FIGS. 1 and 8E, an underfill 946 may not be formed to cover the connection elements 940. In some embodiments, referring to FIGS. 1 and 8E, conductive pads 942 may be further formed to have surfaces substantially coplanar with a surface of the RDL 72, and conductive pads 944 may be further formed to have surfaces substantially coplanar with a surface of the photonic component 40. As such, the optical device 1 illustrated in FIG. 1 is formed.

FIG. 9A, FIG. 9B, FIG. 9C, FIG. 9D, and FIG. 9E illustrate various operations in a method of manufacturing an optical device 3A in accordance with some embodiments of the present disclosure.

Referring to FIG. 9A, a component 20 may be provided, pillars 64 may be formed on an active surface 201 of the component 20, an RDL 70 may be formed on a backside surface 202 of the component 20, pillars 60 may be formed on the RDL 70 and adjacent to the component 20, and the component 20 and the pillars 60 and 62 may be encapsulated by an encapsulant 710. In some embodiments, a planarization process (e.g., a grinding operation) may be performed to planarized bottom surfaces of the encapsulant 710 and the pillars 60 and 64. In some embodiments, a carrier (not shown) may be provided, the RDL 70 may be formed on the carrier, and the component 20 and the pillars 60 and 64 may be formed on the RDL 70 supported by the carrier.

Still referring to FIG. 9A, an RDL 74 may be formed on the planarized surfaces of the encapsulant 710 and the pillars 60 and 64, and electrical contacts 930 may be formed on the RDL 74.

Referring to FIG. 9B, the structure illustrated in FIG. 9A may be flipped, and components 30 and 32 may be bonded to the RDL 70. In some embodiments, an active surface 301 of the component 30 and active surfaces 321 of the components 32 may be flip-chip bonded to the RDL 70.

Referring to FIG. 9C, pillars 50 and 52 may be formed on the RDL 70, and the components 30 and 32 and the pillars 50 and 52 may be encapsulated by an encapsulant 730. In some embodiments, a planarization process (e.g., a grinding operation) may be performed to planarized upper surfaces of the encapsulant 730 and the pillars 50 and 52.

Still referring to FIG. 9C, an RDL 72 may be formed on the upper surfaces of the encapsulant 730 and the pillars 50 and 52, and connection elements 940 may be formed on the RDL 72.

Referring to FIG. 9D, a photonic component 40 with optical fiber array components 42 may be bonded to the RDL 72 through the connection elements 940, and an underfill 946 may be formed to cover the connection elements 940.

Referring to FIG. 9E, the structure illustrated in FIG. 9D may be bonded to a carrier through electrical contacts 930. The carrier 10 may include an interconnection structure 10r and electrical contacts 10c. As such, the optical device 3A is formed.

In some embodiments, referring to FIGS. 3 and 9E, an underfill 946 may not be formed to cover the connection elements 940. In some embodiments, referring to FIGS. 3 and 9E, conductive pads 942 may be further formed to have surfaces substantially coplanar with a surface of the RDL 72, and conductive pads 944 may be further formed to have surfaces substantially coplanar with a surface of the photonic component 40. As such, the optical device 3 illustrated in FIG. 3 is formed.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of said numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” or “about” the same if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It can be clearly understood by those skilled in the art that various changes may be made, and equivalent components may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus, due to variables in manufacturing processes and the like. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.

OPTICAL DEVICE

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