Patent Application
20220336333
The disclosure relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a package structure and a manufacturing method thereof.
In recent years, high-performance computing (HPC) has gain increasing popularity and is widely used in advanced network and server applications, especially in artificial intelligence (AI) related products requiring high data rates, increased bandwidths, and decreased time delay. Among them, people's expectations and requirements for high-density (HD) package carriers used in package structures containing high-performance computing (HPC) grow. For example, the line width and line spacing of the metal layer are required to be between submicron and 10 microns, and the thickness of the dielectric layer of the redistribution layer is required to be between 1 micron and 5 microns. However, the current build-up package substrates fail to meet the above requirements.
The disclosure provides a package structure and a manufacturing method thereof that may be used to solve the above technical problems.
The disclosure provides a package structure including at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit. The first dielectric layer includes a first opening and a second opening communicating with each other. A pore size of the second opening is greater than a pore size of the first opening, and the first redistribution circuit fills the first opening and the second opening. A first upper surface of the first dielectric layer is aligned with a first surface of the first redistribution circuit. The second redistribution layer is disposed on the first redistribution layer. The second redistribution layer includes a second dielectric layer, a third dielectric layer, and a second redistribution circuit. The second dielectric layer includes a third opening, and the second redistribution circuit is disposed on the second dielectric layer, extends into the third opening, and is electrically connected to the first redistribution layer. The third dielectric layer covers the second dielectric layer and the second redistribution circuit and fills the third opening. A second upper surface of the third dielectric layer is aligned with a second surface of the second redistribution circuit. The chip pad is disposed on a first lower surface of the first dielectric layer opposite to the first upper surface and is electrically connected to the first redistribution circuit. The solder ball pad is disposed on the second upper surface of the third dielectric layer and is electrically connected to the second redistribution circuit. The chip is disposed on the chip pad and is electrically connected to the chip pad. The solder ball is disposed on the solder ball pad and is electrically connected to the solder ball pad. The molding compound is disposed on the first lower surface of the first dielectric layer and at least covers the chip and the chip pad.
In one embodiment of the disclosure, a material of the first dielectric layer includes silicon dioxide.
In one embodiment of the disclosure, a material of the second dielectric layer includes a photosensitive dielectric material.
In one embodiment of the disclosure, the above first redistribution circuit has a submicron metal line width and line spacing.
In one embodiment of the disclosure, the above second redistribution circuit has a metal line width and line spacing greater than or equal to 1 micron and less than or equal to 10 microns.
In one embodiment of the disclosure, each of the first redistribution circuit and the second redistribution circuit includes a seed layer and a metal layer disposed on the seed layer.
In one embodiment of the disclosure, each of the chip pad and the solder ball pad includes a seed layer and a metal layer disposed on the seed layer.
In one embodiment of the disclosure, a thickness of the first redistribution layer is less than a thickness of the second redistribution layer.
In one embodiment of the disclosure, the package structure further includes a protective layer disposed on the second upper surface of the third dielectric layer. A third surface of the protective layer is aligned with a fourth surface of the solder ball pad.
In one embodiment of the disclosure, the package structure further includes a copper pillar and a solder material. The copper pillar is disposed on the chip, and the solder material is disposed on the copper pillar. The chip is electrically connected to the chip pad through the solder material on the copper pillar.
The disclosure further provides a manufacturing method of a package structure, and the method includes the following steps. At least one first redistribution layer is formed on a first carrier. The first redistribution layer includes a first dielectric layer and a first redistribution circuit. The first dielectric layer includes a first opening and a second opening communicating with each other. A pore size of the second opening is greater than a pore size of the first opening, and the first redistribution circuit fills the first opening and the second opening. A first upper surface of the first dielectric layer is aligned with a first surface of the first redistribution circuit. At least one second redistribution layer is formed on the first redistribution layer. The second redistribution layer includes a second dielectric layer, a third dielectric layer, and a second redistribution circuit. The second dielectric layer includes a third opening, and the second redistribution circuit is disposed on the second dielectric layer, extends into the third opening, and is electrically connected to the first redistribution layer. The third dielectric layer covers the second dielectric layer and the second redistribution circuit and fills the third opening. A second upper surface of the third dielectric layer is aligned with a second surface of the second redistribution circuit. A solder ball pad is formed on the second upper surface of the third dielectric layer, and the solder ball pad is electrically connected to the second redistribution circuit. A second carrier is provided on the solder ball pad, and the first carrier is removed to expose a first lower surface of the first dielectric layer opposite to the first upper surface. A chip pad is formed on the first lower surface of the first dielectric layer, and the chip pad is electrically connected to the first redistribution circuit. A chip is disposed on the chip pad and is electrically connected to the chip pad. A molding compound is formed on the first lower surface of the first dielectric layer. The molding compound at least covers the chip and the chip pad. The second carrier is removed to expose the solder ball pad. A solder ball is formed on the solder ball pad and is electrically connected to the solder ball pad.
In one embodiment of the disclosure, the step of forming the first redistribution layer on the first carrier includes the following steps. The first dielectric layer is formed on the first carrier through a plasma-enhanced chemical vapor deposition (PECVD) process. A reactive ion etching (RIE) process is performed on the first dielectric layer to form the first opening and the second opening communicating with each other. A seed material is formed on the first upper surface of the first dielectric layer, an inner wall of the first opening, and an inner wall of the second opening. A metal material is formed on the seed material. The metal material covers the seed material and fills the first opening and the second opening. A polishing process is performed to the metal material and the seed material to expose the first upper surface of the first dielectric layer and form a metal layer and a seed layer located in the first opening and the second opening. The metal layer and the seed layer define the first redistribution circuit.
In one embodiment of the disclosure, the step of forming the second redistribution layer on the first redistribution layer includes the following steps. The second dielectric layer is formed on the first redistribution layer. The second dielectric layer covers the first upper surface of the first dielectric layer and includes a third opening exposing part of a first surface of the first redistribution circuit. A seed material is formed on the second dielectric layer and an inner wall of the third opening. A patterned photoresist layer is formed on the seed material, and the patterned photoresist layer exposes part of the seed material. The patterned photoresist layer is treated as an electroplating mask to deposit a metal material on the seed material exposed by the patterned photoresist layer through electro-chemical deposition (ECD). The patterned photoresist layer and the seed material thereunder are removed to form a metal layer and a seed layer thereunder to define the second redistribution circuit. The third dielectric layer is formed on the second dielectric layer and covers the second redistribution circuit.
In one embodiment of the disclosure, the step of forming the solder ball pad on the second upper surface of the third dielectric layer includes the following steps. A fourth dielectric layer is formed on the second redistribution layer. The fourth dielectric layer covers the second upper surface of the third dielectric layer and includes a fourth opening exposing part of the second surface of the second redistribution circuit. A seed material is formed on the fourth dielectric layer and an inner wall of the fourth opening. A patterned photoresist layer is formed on the seed material, and the patterned photoresist layer exposes part of the seed material. The patterned photoresist layer is treated as an electroplating mask to electroplate a metal material on the seed material exposed by the patterned photoresist layer. The patterned photoresist layer and the seed material thereunder are removed to form a metal layer and a seed layer thereunder to define the solder ball pad.
In one embodiment of the disclosure, the manufacturing method of the package structure further includes the following step. A protective layer is formed on the fourth dielectric layer, and a third surface of the protective layer is aligned with a fourth surface of the solder ball pad.
In one embodiment of the disclosure, the step of forming the chip pad on the first lower surface of the first dielectric layer includes the following steps. An RIE process is performed on the first dielectric layer to form an opening exposing part of the first redistribution circuit. A seed material is formed on the first dielectric layer and an inner wall of the opening. A patterned photoresist layer is formed on the seed material, and the patterned photoresist layer exposes part of the seed material. The patterned photoresist layer is treated as an electroplating mask to electroplate a metal material on the seed material exposed by the patterned photoresist layer. The patterned photoresist layer and the seed material thereunder are removed to form a metal layer and a seed layer thereunder to define the chip pad.
In one embodiment of the disclosure, the manufacturing method of the package structure further includes the following steps. A copper pillar is formed on the chip before the chip is disposed on the chip pad. A solder material is formed on the copper pillar. The chip is electrically connected to the chip pad through the solder material on the copper pillar.
In one embodiment of the disclosure, a material of the first dielectric layer includes silicon dioxide, and a material of the second dielectric layer includes a photosensitive dielectric material.
In one embodiment of the disclosure, the first redistribution circuit has a submicron metal line width and line spacing.
In one embodiment of the disclosure, the second redistribution circuit has a metal line width and line spacing greater than or equal to 1 micron and less than or equal to 10 microns.
Based on the above, in the package structure and the manufacturing method thereof provided by the disclosure, the first redistribution layer and the second redistribution layer of completely different structure types are formed. In following, the chip is disposed and the package process is performed before the second carrier is removed and the solder ball is disposed. The first redistribution circuit of the first redistribution layer fills the first opening and the second opening of the first dielectric layer communicating with each other and having different pore sizes. The first upper surface of the first dielectric layer is aligned with the first surface of the first redistribution circuit. The second redistribution circuit of the second redistribution layer is disposed on the second dielectric layer, extends into the third opening of the second dielectric layer, and is electrically connected to the first redistribution layer. The third dielectric layer covers the second dielectric layer and the second redistribution circuit and fills the third opening, and the second upper surface of the third dielectric layer is aligned with the second surface of the second redistribution circuit. Compared with the manufacturing of existing build-up package substrates, the package structure of the disclosure may form two redistribution layers of different structure types, and in this way, people's expectations and requirements for high-density package structures are satisfied.
In order to make the aforementioned features and advantages of the disclosure comprehensible, embodiments accompanied with drawings are described in detail below.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
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In detail, the first redistribution layer RDL11 in this embodiment includes the first dielectric layer 110 and the first redistribution circuit 115. The first dielectric layer 110 includes the first opening 112 and the second opening 114 communicating with each other, and the pore size of the second opening 114 is greater than the pore size of the first opening 112. The first redistribution circuit 115 fills the first opening 112 and the second opening 114, and the first upper surface 111 of the first dielectric layer 110 is aligned with a first surface 117 of the first redistribution circuit 115. Here, the first redistribution circuit 115 is formed through a copper Damascene process and the polishing process, the first redistribution circuit 115 is a stepped structure, and the first redistribution circuit 115 has a submicron metal line width and line spacing.
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Next, with reference to 1K, a second dielectric layer 130 is formed on the first redistribution layer RDL12 by coating. The second dielectric layer 130 covers a first upper surface 121 of the first dielectric layer 120 and includes a third opening 132 which exposes part of a first surface 127 of the first redistribution circuit 125. Here, a material of the second dielectric layer 130 is, for example, a photosensitive dielectric material, and a thickness of the second dielectric layer 130 is, for example, 5 microns.
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In detail, in this embodiment, the second redistribution layer RDL21 includes the second dielectric layer 130, the third dielectric layer 140, and the second redistribution circuit 135. The second dielectric layer 130 includes the third opening 132. The second redistribution circuit 135 is disposed on the second dielectric layer 130, extends into the third opening 132, and is electrically connected to the first redistribution circuit 125. The third dielectric layer 140 covers the second dielectric layer 130 and the second redistribution circuit 135 and fills the third opening 132 and the concave trench C1. A second upper surface 141 of the third dielectric layer 140 is aligned with a second surface 137 of the second redistribution circuit 135.
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Moreover, the second redistribution layers RDL21 and RDL22 provided by this embodiment are sequentially disposed on the first redistribution layer RDL12. The second redistribution layers RDL21 and RDL22 include the second dielectric layers 130 and 150, the third dielectric layers 140 and 160, and the second redistribution circuits 135 and 155. The second dielectric layers 130 and 150 include the third openings 132 and 152. The second redistribution circuits 135 and 155 are disposed on the second dielectric layers 130 and 150 and extend into the third openings 132 and 152. The second redistribution circuit 135 is electrically connected to the first redistribution circuit 125 of the first redistribution layer RDL12. The third dielectric layers 140 and 160 cover the second dielectric layers 130 and 150 and the second redistribution circuits 135 and 155 and fill the third openings 132 and 152. The second upper surfaces 141 and 161 of the third dielectric layers 140 and 160 are aligned with the second surfaces 137 and 157 of the second redistribution circuits 135 and 155.
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Moreover, the package structure 100a of this embodiment further includes the fourth dielectric layer 170 and the protective layer 180 thereon. The fourth dielectric layer 170 covers the second upper surface 161 of the third dielectric layer 160 and the second surface 157 of the second redistribution circuit 155. The solder ball pad 175 is located on the fourth dielectric layer 170. The protective layer 180 is disposed on the second upper surface 161 of the third dielectric layer 160, and the fourth dielectric layer 170 is located between the protective layer 180 and the third dielectric layer 160. The third surface 181 of the protective layer 180 is aligned with the fourth surface 177 of the solder ball pad 175.
In addition, the package structure 100a of this embodiment further includes the copper pillar 187 and the solder material 189. The copper pillar 187 is disposed on the chip 185, and the solder material 189 is disposed on the copper pillar 187. The chip 185 is electrically connected to the chip pad 118 through the solder material 189 on the copper pillar 187. The molding compound 190 covers the chip 185, the copper pillar 187, the solder material 189, and the chip pad 118. The chip 185 is electrically connected to the chip pad 118 through the copper pillar 187 and the solder material 189.
It is to be noted that the following embodiments use the reference numerals and a part of the contents of the above embodiments, and the same reference numerals are used to denote the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the above embodiments, and details are not described in the following embodiments.
In view of the foregoing, in the package structure and the manufacturing method thereof provided by the disclosure, the first redistribution layer and the second redistribution layer of completely different structure types are formed. The first redistribution circuit of the first redistribution layer is formed through the copper Damascene process and the polishing process, and the first dielectric layer is made of silicon dioxide. The second redistribution circuit of the second redistribution layer is manufactured through the PVD and ECD methods, and the second dielectric layer and the third dielectric layer are made of photosensitive dielectric materials. In this way, the metal line width and line spacing of the first redistribution circuit of the first redistribution layer may be submicron, and the metal line width and line spacing of the second redistribution circuit of the second redistribution layer may be greater than or equal to 1 micron and less than or equal to 10 microns. Compared with the manufacturing of existing build-up package substrates, the package structure of the disclosure may form two redistribution layers of different structure types, and in this way, people's expectations and requirements for high-density package structures are satisfied.
Although the disclosure has been disclosed in the above embodiments, the embodiments are not intended to limit the disclosure. Persons skilled in the art may make some changes and modifications without departing from the spirit and the scope of the disclosure. Accordingly, the protection scope of the disclosure shall be defined by the appended claims.
