Patent Application
20140138844
The invention relates to semiconductor structures and, more particularly, to patterned backside metal ground planes for improved metal adhesion and methods of manufacture.
Packaging lead inductance is a major design issue, particularly for RF analog chips such as WLAN power amplifiers (PA). For example, the emitter ground leads used in SiGe heterojunction bipolar transistor (HBT) RF designs are normally contacted to the package either using multiple wire bonds or flip chip solder bumps. Wire bond package ground leads have high inductance, on the order of 160 pH, which results in unacceptable PA insertion loss. Although flip chip solder bumps have low inductance, they increase packaging complexity and are expensive.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
In an aspect of the invention, a method comprises forming at least one die on a substrate. The at least one die is formed adjacent to a dicing channel and comprises through silicon vias (TSVs). The method further comprises forming a metalized ground plane on a backside of the substrate in contact with the TSVs and which is located in such areas on the backside of the substrate that it does not interfere with dicing operations performed within the dicing channel.
In an aspect of the invention, a method comprises forming a plurality of dies on a substrate separated by dicing channels. The plurality of dies each comprise a plurality of through silicon vias (TSVs). The method further comprises depositing a metal on selected areas on a backside of the substrate such that the metal is patterned to contact the TSVs on the plurality of dies. The method further comprises dicing the substrate to form the plurality of dies, wherein the dicing will avoid contact with the metal on the selected areas on the backside of the substrate.
In an aspect of the invention, a structure comprises a substrate comprising a plurality of dies, each having a plurality of through silicon vias. The structure further comprises dicing channels provided between the plurality of dies, and a metalized ground plane on a backside of the plurality of the dies in contact with the silicon vias. The dicing channels are substantially devoid of the metalized ground plane.
In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of the patterned backside metal ground planes, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the patterned backside metal ground planes. The method comprises generating a functional representation of the structural elements of the patterned backside metal ground planes.
The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
The invention relates to semiconductor structures and, more particularly, to patterned backside metal ground planes for improved metal adhesion and methods of manufacture. More specifically, the present invention relates to structures and methods of forming backside metal in specific locations (i.e., patterned backside metal) on a backside surface of a substrate. In embodiments, the metal is not formed in any dicing channel; instead, the backside metal is formed only on the die, and preferably in limited regions of the backside of the die, which contact through-silicon vias. In embodiments, the backside metal is patterned differently than wiring; that is, the backside metal is patterned to form patches and/or islands of metal which are all coupled to the same potential (e.g., ground).
Grounded through silicon vias (TSVs) can be used to reduce ground lead inductance and reduce the bond pad area on the chip surface. In such implementations, a metal is blanket deposited on the backside of the substrate, including in the dicing channel, to act as a ground plane. However, in such implementations, problems with metal adhesion are commonly observed during dicing. That is, the dicing process introduces a large peeling stress at the metal-Si interface, which can cause the metal to peel from the corners and edges of the die. Often, the peeled metal “folds over”, resulting in a very non-planar surface on the back of the die, which can cause problems with die yield and reliability.
Advantageously, the present invention solves the metal peeling problem by using a patterned backside metal ground plane, which, in some embodiments, is not deposited in the dicing channel. This allows the wafer to be diced without affecting the backside metal, thereby forming dies with a planar backside metal ground plane. The patterned backside metal ground plane can be formed with minimal additional cost by using a shadow mask, for example, during metal deposition. Other options for metal patterning contemplated by the present invention include, for example, liftoff of the metal and subtractive etching of the metal. By using a patterned backside metal ground plane, a less expensive dicing process can be used, thereby reducing the overall cost of the packaged module. Also, in embodiments, the use of the backside metal will reduce ground lead inductance and chip area that ordinarily occurs with wirebonding substrate designs.
In embodiments, the through silicon vias (TSV)12 can be formed using conventional processes, such as, for example, lithography, etching and deposition processes, with a backside polishing and grinding process, all of which are schematically represented in
As one example, Bosch deep reactive ion etching (DRIE) can be used to fabricate the TSVs with almost any diameter, from the submicrometer level to hundreds of micrometers. In more specific embodiments, a via can be formed in a front side of the die 10 using conventional lithography and etching processes. The via would typically extend only partially through the die 10 (or substrate 5). After formation of the via, metal can be deposited therein using conventional deposition processes such as, for example, electroplating or chemical vapor deposition techniques. In embodiments, the metal can be any appropriate metal used in semiconductor manufacturing processes for TSVs such as, for example, copper. The backside of the substrate 5 then undergoes a thinning process, e.g., a polishing and grinding process, in order to expose the TSVs 12.
In embodiments, the backside metal 16 can be formed by different processes, including, for example, the use of a shadow mask, a liftoff process or a subtractive etch process, all of which are schematically represented in
In a shadow mask process, a mechanical stencil mask is placed over the wafer (i.e., between the wafer and the metal target), with openings in the mask where metal deposition is required on the wafer. The mechanical stencil mask blocks the deposition of metal in the dicing channel 14 during subsequent deposition processes. In embodiments, the shadow mask can be a thin layer of metal with openings as required for deposition on the die, but not on the dicing channel 14. After placement of the stencil mask, metal is deposited on the backside of the die 10 using conventional deposition methods such as, for example, a sputter deposition, evaporation, or chemical vapor deposition process. The deposition of the backside metal is blocked in the dicing channel 14 by the stencil mask.
In the liftoff process, a resist can be applied to the backside of the substrate, after grinding and polishing processes that expose the TSVs 12. The resist is formed in an inverse pattern, created from a sacrificial stencil layer (e.g., resist) which is deposited in the dicing channel 14 (on the surface of the substrate 5). This can be accomplished by forming openings through the resist layer (e.g., resist apply, expose, develop) so that target material (e.g., backside metal 16) can reach the surface of the substrate only in regions, e.g., on the die 12, in contact with the TSVs 12. The backside metal 16 is then deposited over the substrate 5, including on the dies 10. This deposition reaches the surface of the substrate 5 in the open regions and stays on the top of the sacrificial stencil layer (resist) in the regions where it was not previously opened, e.g., dicing channel 14. When the sacrificial layer is washed away, the metal material on the top of the resist is lifted-off and washed together with the resist. After the lift-off, the target material, e.g., backside metal 16, remains only in the regions where it had a direct contact with the substrate, e.g., on the dies 10.
In embodiments, the backside metal 16 may be overlapped or underlapped with the dies 10. For example, as shown in
In the subtractive etching process, a backside metal 16 is blanket deposited on the backside of the substrate 5, e.g., on the die 10 and within the dicing channel 14. As in any of the embodiments, the backside metal 16 can be copper or gold with a diffusion layer of titanium. In embodiments, the titanium will improve the adhesion of the copper or gold on the substrate. In embodiments, a resist is formed over the metal, which is then exposed and developed to form a pattern, e.g., openings over the dicing channel 14. The exposed metal is then removed using a wet etching process with a chemistry to remove the metal in the dicing channel 14. In this way, metal is only left on the die 10 or portions thereof. The resist is then stripped using oxygen ashing or organic solvents.
In embodiments, the deposition of the metal will also form metal pads 16a. The metal pads 16a are provided at strategic locations on the dies 10 to provide mechanical support. In embodiments, the metal pads 16a can be dummy metal shapes formed for stability on the backside of the die 10. That is, the metal pads 16a can be formed and placed such that the die 10 will sit flatly on the package substrate, during packaging. The metal pad 16a and the backside metal 16 can be formed using a shadow mask, liftoff process or subtractive etch as described above. In any of the deposition processes, the backside metal 16 and the metal pads 16a have a planar surface, which can be formed by the deposition process or through additional processing such as, for example, CMP.
Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990.
Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw substrate 5 form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
