Patent Application
20240332148
This description relates to assembling and packaging semiconductor device modules, semiconductor device assemblies, and semiconductor devices. More specifically, this description relates to semiconductor device modules with superior thermal performance.
Semiconductor device assemblies, e.g., chip assemblies, that include power semiconductor devices can be implemented using multiple semiconductor dies, substrates (e.g., die attach pads (DAPs)), electrical interconnections, and a molding compound. Power transistors can include, for example, insulated-gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field effect transistors (MOSFETs), and so forth. Fast recovery diodes (FRDs) may be used in conjunction with power transistors. Electrical interconnections within a high-power semiconductor device module can include, for example, bond wires, conductive spacers, and conductive clips. A polymer molding compound can serve as an encapsulant to protect components of the device assembly. Such high-power chip assemblies, encapsulated as semiconductor device modules, can be used in various applications, including electric vehicles (EVs), hybrid electric vehicles (HEVs), and industrial applications.
In some aspects, the techniques described herein relate to an apparatus, including: a direct bonded metal substrate; a first power tab electrically coupled to the direct bonded metal substrate; a second power tab electrically coupled to the direct bonded metal substrate; a distal end of the first power tab aligned with a first longitudinal axis; and a distal end of the second power tab aligned with a second longitudinal axis non-parallel to the first longitudinal axis, the first power tab having a proximal end overlapping a proximal end of the second power tab, wherein the distal end of the first power tab does not overlap the distal end of the second power tab.
In some aspects, the techniques described herein relate to an apparatus, further including a heat transfer mechanism coupled to the direct bonded metal substrate.
In some aspects, the techniques described herein relate to an apparatus, further including at least two semiconductor dies electrically coupled via a wire bond or a clip.
In some aspects, the techniques described herein relate to an apparatus, further including an output tab electrically coupled to the direct bonded metal substrate.
In some aspects, the techniques described herein relate to an apparatus wherein, in operation, current flows from the first power tab to the output tab and from the output tab to the second power tab without flowing through the direct bonded metal substrate.
In some aspects, the techniques described herein relate to an apparatus, further including heat dissipating pins that are oriented perpendicular to a plane of the direct bonded metal substrate and a plane of the first power tab and the second power tab.
In some aspects, the techniques described herein relate to an apparatus, wherein a thickness of the first power tab and the second power tab is about three times greater than a thickness of a current path within a conductive layer of the direct bonded metal substrate.
In some aspects, the techniques described herein relate to an apparatus, further including a first opening in the distal end of the first power tab and a second opening in the distal end of the second power tab.
In some aspects, the techniques described herein relate to an apparatus, wherein a perimeter of the first power tab and the second power tab forms a heart shape.
In some aspects, the techniques described herein relate to an apparatus, including: a direct bonded metal substrate; a metal base plate attached to a bottom layer of the direct bonded metal substrate; an array of heat dissipating pins attached to the metal base plate; a first metal tab and a second metal tab coupled to the direct bonded metal substrate, the first metal tab oriented in a transverse direction with respect to the second metal tab; and a plastic case surrounding a top layer of the direct bonded metal substrate.
In some aspects, the techniques described herein relate to an apparatus, wherein the plastic case is attached to the metal base plate without screws.
In some aspects, the techniques described herein relate to an apparatus, further including power tabs extending over the direct bonded metal substrate.
In some aspects, the techniques described herein relate to an apparatus, wherein the first metal tab includes a negative terminal, and the second metal tab includes a positive terminal, and further including a third metal tab including an output terminal opposite the first metal tab and the second metal tab.
In some aspects, the techniques described herein relate to an apparatus, wherein the apparatus is configured for current to flow from the positive terminal to the output terminal and back to the negative terminal via a central region of the direct bonded metal substrate.
In some aspects, the techniques described herein relate to an apparatus, wherein the first metal tab is oriented at a right angle with respect to the second metal tab.
In some aspects, the techniques described herein relate to a method, including: overlapping proximal ends of a first power tab and a second power tab coupling clips of the first power tab to a central region of a substrate; coupling clips of the second power tab to an edge region of the substrate; and coupling clips of a third power tab to the central region of the substrate.
In some aspects, the techniques described herein relate to a method, wherein the first power tab, the second power tab, and the third power tab are configured as integral elements of a plastic case.
In some aspects, the techniques described herein relate to a method, wherein coupling the clips of the first power tab and the clips of the third power tab to a central region of the substrate includes overlaying the clips above circuitry on the substrate by positioning the plastic case relative to the substrate.
In some aspects, the techniques described herein relate to a method, wherein the overlapping includes aligning a first hole in the first power tab with a second hole in the second power tab to produce aligned first and second holes.
In some aspects, the techniques described herein relate to a method, further including attaching a heat dissipating pin to the substrate, wherein the heat dissipating pin extends through the aligned first and second holes.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with common practice in the industry, various features are not necessarily drawn to scale. Dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. In the drawings, like reference symbols may indicate like and/or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols shown in one drawing may not be repeated for the same, and/or similar elements in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of an element are illustrated.
The footprint of electronic devices is important with respect to materials cost and reliability. When electronic devices, e.g., high-power semiconductor device modules, are laid out in an inefficient manner, wasted space on a substrate increases material cost unnecessarily. In addition, wiring between devices that are spaced apart can be inherently more vulnerable to damage or breakage and, consequently, can cause reliability failures. These concerns are particularly significant for high power modules that include expensive materials such as silicon carbide (SiC), high tech ceramics made of silicon nitride (Si3N4), and direct bond metal (DBM) structures, e.g., direct bond copper (DBC) structures used as substrates for the high power modules. When these high power modules are manufactured in large volume, even a small reduction in per unit cost can add up to a substantial saving.
This disclosure relates to implementations of a single side direct cooling (SSDC) package for high-power electronic device modules. The power modules route large currents through a set of metal power tabs instead of passing high currents through a DBM structure. The metal power tabs are about three times thicker than conductive layers that form a current path through the DBM structure. By orienting the power tabs in a mini-heart design, stray inductance and resistance can both be reduced, thereby improving performance while simultaneously reducing the footprint of the high power module. In addition, wire bonds between chip assemblies in a high-power semiconductor device module can be replaced by solid metal clips that can better withstand high currents and voltages. The SSDC package incorporates the metal power tabs and provides heat dissipation via a metal base plate that includes a heat sink. The heat sink can be immersed in a cooling fluid to provide faster heat dissipation.
In some implementations, the DBM 102 is a multi-layer substrate to which various electronic assemblies are mounted, e.g., attached. The DBM 102 includes a die attach pad (DAP) 108 and one or more electronic components, e.g., semiconductor dies or chip assemblies 110 in contact with the DAP 108. The chip assemblies 110 may include high power chip assemblies that generate heat and may cause heat accumulation within the DBM 102. The chip assemblies 110 are electrically coupled to one another by wire bonds 112. Some of the wire bonds 112 may extend through the DAP 108 to make external connections to the chip assemblies 110. The wire bonds 112 can include copper wires and/or aluminum wires. The DAP 108 can be integral to, or attached to, a first conductive layer of the DBM 102. The DBM 102 can further include a second conductive layer and a non-conductive layer (not shown).
In some implementations, the DBM 102 can be a direct bond copper (DBC) type structure, a direct plating copper (DPC) type structure, or a direct bond aluminum (DBA) type structure. The DBM 102 may be referred to as a heat spreader that provides single-sided cooling of the chip assemblies 110. In some implementations, the DBM 102 can have a total thickness in a range of about 0.5 mm to about 3.0 mm. In some implementations, the DBM 102 is designed as a three-layer DBM structure that includes the non-conductive layer sandwiched between the first conductive layer and the second conductive layer. In some implementations, the non-conductive layer serves as a thermal mass disposed between the two outer metal layers to draw in and absorb heat. The non-conductive layer may also provide electrical insulation between the first conductive layer and the second conductive layer of the DBM 102.
In some implementations, the first conductive layer and the second conductive layer of the DBM 102 can be, or can include, a metal layer (e.g., a copper layer, a copper alloy layer) that is formed on (e.g., bonded to, sputtered on, diffused onto to, heat-formed on) the non-conductive layer. The first conductive layer can be coupled to a first side of the non-conductive layer, and the second conductive layer can be coupled to a second side of the non-conductive layer. The first conductive layer can be, or can include, a metal trace as the die attach pad (DAP) 108 on which to mount (or couple) the chip assemblies 110. The first conductive layer or the second conductive layer can be referred to as an upper conductive layer or as a lower conductive layer depending on the orientation of the device. In some implementations, the non-conductive layer of the DBM 102 can include a ceramic material, e.g., silicon nitride (Si3N4) or aluminum oxide (Al2O3), Si3N4 being a significantly more expensive ceramic material than Al2O3.
In some implementations, the die attach pad 108 can be formed by the first conductive layer, e.g., a top conductive layer, of the DBM 102. In some implementations, the non-conductive layer and/or the second conductive layer of the DBM 102 can have a larger footprint than the DAP 108.
The chip assemblies 110 can be attached to, e.g., mounted on, or coupled to, a top surface of the DAP 108 by a copper sputtering process or by a bonding agent, e.g., an epoxy, a solder, a silver (Ag) sintering material, and/or an adhesive. In some implementations that include multiple chip assemblies 110, first and second chip assemblies 110 can be coupled to the DAP 108 by two different bonding agents. For example, in some implementations, a first chip assembly 110 can be attached to the DAP 108 by sintering, while a second chip assembly 110 is attached to the DAP 108 by polyimide tape.
In some implementations that include multiple chip assemblies, the chip assemblies 110 can include, for example, high power semiconductor devices such as an insulated gate bipolar transistor (IGBT) and a controller configured to control the IGBT. The controller can also serve as a protection device for the IGBT. For example, the controller can provide temperature protection and/or over-voltage protection for the IGBT. The controller can also limit the amount of current delivered to the IGBT. In some implementations, the controller can be configured to monitor the IGBT. In some implementations, other types of semiconductor dies, e.g., MOSFETs, diodes, and so forth, can be used as one or more of the chip assemblies 110. In some implementations, fast recovery diodes (FRDs) may be used in conjunction with power transistors.
The chip assemblies 110 can be fabricated on various types of semiconductor substrates, e.g., semiconductor wafers, for example, silicon (Si), silicon carbide (SiC), gallium (Ga), gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), glass substrates, sapphire substrates, and so on. In general, any type of semiconductor chip can be fabricated on any type of substrate.
In some implementations, different chip assemblies 110 can be fabricated on different substrates in a hybrid configuration. For example, an IGBT chip assembly 110 can be fabricated on a SiC substrate, while a controller chip assembly 110 can be fabricated on a silicon substrate. In some implementations as described herein, multiple chip assemblies 110 can be fabricated on the same substrate, e.g., on a SiC substrate, suitable for high power applications.
In some implementations, the power module 100 can include a first power tab 120, a second power tab 122, a third power tab 124, and heat dissipating pins 125 (5 shown). In some implementations, the power tabs 120, 122, and 124 can be made of a thick metal, about 1.0 mm thick, capable of supporting high voltages in a range of about 600 V to about 1700 V and carrying high currents up to about 900 A. In some implementations, the first power tab 120 and the second power tab 122 are disposed on one end of the DBM 102 and the third power tab 124 is disposed on the other end of the DBM 102. In operation, the first power tab 120 can be coupled to a negative direct current terminal (DC−), the second power tab 122 can be coupled to a positive direct current terminal (DC+), and the third power tab 124 can be an output terminal, so that current flows from the second power tab 122 to the third power tab 124, and from the third power tab 124 to the first power tab 120. In the power module 100, current is routed mainly through the power tabs 120 and 124 rather than through the DBM 102. In some implementations, resistance of the power tabs can be about 58% less than resistance in the DBM 102. In some implementations, one or more of the first power tab 120, the second power tab 122, and the third power tab 124 can have rounded ends. The rounded ends can reduce a concentration of electric charge during operation of the power module 100. In some implementations, the power tabs 120, 122, and 124 can have square ends, tapered ends, or ends having another shape.
In some implementations, a proximal end of the first power tab 120 can be aligned with, e.g., can extend in a same direction as, a first longitudinal axis 126; a proximal end of the second power tab 122 can be aligned with a second longitudinal axis 128; and a proximal end of the third power tab 124 can be aligned with a third longitudinal axis 130. A longitudinal axis represents the direction in which the length, e.g., the longest linear dimension, of the power tab extends. In some implementations, the third longitudinal axis 130 can be aligned with a length of the DBM 102, e.g., in the y-direction, as shown in
In some implementations, the first longitudinal axis 126 and the second longitudinal axis 128 can be rotated with respect to the third longitudinal axis 130, for example, at about a 45 degree angle as shown in
In some implementations, the angle θ is less than 90 degrees, or greater than 90 degrees, such that the proximal ends of the first power tab 120 and the second power tab 122 extend out from the DBM 102 in different directions that are not orthogonal to each other. The angle θ determines the amount of overlap between the proximal ends of the first power tab 120 and the second power tab 122. As the angle θ approaches 0, the overlap area between the first and second power tabs 120 and 122 will approach 100%; as the angle θ approaches 180 degrees, the overlap area between the first and second power tabs 120 and 122 will approach zero. The overlap area can affect the size, form factor, packaging, and usage of the power module 100. The overlap may also affect current flow through the power module 100.
It may be desirable to maximize the overlap area of the first power tab 120 and the second power tab 122 to reduce, e.g., minimize, stray inductance and thermal resistance during high frequency operation of the power module 100. In some implementations, it may be desirable to reduce stray inductance below, for example, about 8 nH, and junction-to-fluid thermal resistance, Rthjf, below about 0.1 degree C. per Watt. Use of the power module 100 can reduce stray inductance by about 40% relative to other designs.
An opening 132, e.g., a hole, can be formed in the proximal end of the first power tab 120; an opening 134 can be formed in the proximal end of the second power tab 122; and an opening 136 can be formed in the proximal end of the third power tab 124. The openings 132, 134, and 136 can accommodate fasteners, e.g., screws, for coupling the respective power tabs 120, 122, and 124 to sources of power, e.g., high voltage battery terminals. The openings 132, 134, and 136 can also help to accelerate heat dissipation. by increasing the surface area of the first power tab 120, the second power tab 122, and the third power tab 124, respectively. The openings 132, 134, and 136 are shown as round holes as an example, but the openings can have any shape.
In some implementations, a distal end of the first power tab 120 can include a first set of clips 138 (three shown, 138a, 138b, and 138c); a distal end of the second power tab 122 can include a second set of clips 140 (three shown, 140a, 140b, and 140c); and a distal end of the third power tab 124 can include a third set of clips 142 (two shown, 142a and 142b). The first set of clips 138 extend over the chip assemblies 110 and wire bonds 112 to a center region 144 of the DBM 102, where the first set of clips 138 couple the first power tab 120 to the DAP 108. Likewise, the third set of clips 142 can extend over the chip assemblies 110 and wire bonds 112 to the center region 144 of the DBM 102, where the third set of clips 142 couple the third power tab 124 to the DAP 108. The second set of clips 140 couple the second power tab 122 to an end region 146 of the DAP 108. The second set of clips 140 can therefore have shorter lengths compared with the first set of clips 138 and the third set of clips 142. In some implementations, the widths of the outside clips 138a and 138c can be narrower than the width of the inside clip 138b, which is placed in the center of the DBM 102.
In some implementations, the clips 138 extend parallel to one another in the −y direction as do the clips 140, which are disposed under the clips 138.
The center region 144 and the end region 146 of the DBM 102 can include solder pads 147 that provide electrical connections to circuitry that distributes electrical power delivered by the clips 138, 140, and 142. In some implementations, the clips 138, 140, and 142 can be connected to the DAP 108, e.g., a top conductive layer of the DBM 102, by other methods such as ultrasonic welding. Placement of the clips 138 and 142, or placement of the solder pads 147, can alternate, e.g., be interdigitated, within the center region 144 to make efficient use of space on the DAP 108. In some implementations, the clips 142 are wider than the clips 138. Consequently, the solder pads 147 may be sized differently to match footprints of the various clips.
In some implementations, the heat dissipating pins 125 can extend in a direction perpendicular to the plane of the DBM 102, e.g., in the z-direction. Each of the heat dissipating pins 125 can be attached to the DAP 108 by a platform 148. The heat dissipating pins 125 can be metallic. In some implementations, one or more of the heat dissipating pins 125 can extend through an opening 150 in the first power tab 120. The opening 150 can also extend through an opening in the overlapping second power tab 122 that is aligned with the opening 150.
With reference to
With reference to
The cooling unit 1000 can be used to simulate potential cooling scenarios for the power modules 100 housed in the SSDC package 500. A numerical model used for the simulation can be a three-dimensional (3D) model that uses steady state thermal analysis to test different flow and heat transfer variables and compute a junction-to-fluid thermal resistance (Rthjf). A maximum Rthjf per switch and a mean Rthjf per switch can both be determined. The maximum Rthjf per switch can be computed as (Tj−Tf)/power dissipation per switch, wherein Tj is the maximum junction temperature and Tf is the fluid temperature of the cooling fluid. The mean Rthjf per switch can be computed as (Tj−Tf)/power dissipation per switch, wherein Tj is the mean junction temperature and Tf is the fluid temperature of the cooling fluid. The 3D model can be run for both the wire bond version 102a and the clip version 102b of the DBM 102.
At 1202, the method 1200 includes overlapping proximal ends of the first power tab 120 and the second power tab 122. This step can be performed in conjunction with fabricating the plastic case 501 of the SSDC package 500, as described below. Overlapping the proximal ends of the first and second power tabs 120 and 122, respectively, can include aligning a first hole in the first power tab 120 with a second hole in the second power tab 122 to create the aligned opening 150. The first power tab 120, the second power tab 122, and the third power tab 124 can all be insert molded into the plastic case 501. By incorporating the power tabs as integral parts of the plastic case 501, the desired orientation of the power tabs with respect to one another and the DBM 102 can be fixed. In addition, the desired positions of the clips 138, 140, and 142 will automatically be aligned so as to connect with, e.g., land on, the solder pads 147 of the DBM 102.
At 1204, the method 1200 includes attaching, e.g., coupling, clips 138 at a distal end of the first power tab 120 to the central region 144 of the DBM 102 so as to overlay the clips 138 above circuitry on the underlying DBM 102.
At 1206, the method 1200 includes attaching, e.g., coupling, clips 140 of the second power tab 122 to the end region 146 of the DBM 102.
At 1208, the method 1200 includes attaching, e.g., coupling, clips 142 at a distal end of the third power tab 124 to the central region 144 of the DBM 102.
Operations 1204, 1206, and 11208 can occur automatically as the plastic case 501 is lowered onto the metal base plate 510, as described below.
At 1210, the method 1200 includes attaching a heat dissipating pin 125 to extend through aligned holes in the overlapping first and second power tabs 120 and 122. The heat dissipating pins 125 can be attached to the DBM 102 and can extend through the aligned holes in the plastic case 501, as shown in
Starting with the bottom layer 1300, the pre-formed solder layer 1304 can be deposited onto the metal base plate 510, and patterned to fit the dimensions of the DBMs 102. The DBMs 102 can then be placed onto the pre-formed solder layer 1304 and heated, e.g., cured, to melt the pre-formed solder layer 1304 and also the solder pads 147. While the solder is soft, the plastic case 501 can be lowered onto the metal base plate 510 using the alignment pins 507 as a guide. It is noted that the plastic case 501 includes the power tabs 120, 122, and 124 as embedded elements for each of the three power modules 100. As the plastic case 501 is lowered onto the metal base plate 510, the power tabs 120, 122, and 124 will make electrical contact with the solder pads 147 in the central region 144 and the end region 146 of the DAP 108. The plastic case 501 can then be secured to the metal base plate 510 using the clips 508. Upon cooling, the DBMs 102 will be secured to the base plate 510, and the power tabs 120, 122, and 124 will be coupled to the electronic devices, e.g., the chip assemblies 110, on the DBM 102 via the solder pads 147.
Finally, the lid 506 can be lowered onto the plastic case 501 using the alignment pins 507 as a guide. The lid 506 can be secured using the fasteners 502, e.g., thumbscrews. The heat dissipating pins 125 extend through all of the layers including the lid 506, in which machined holes are formed that align with the positions of the heat dissipating pins 125.
As described above, various implementations of power modules 100 housed in an SSDC package 500 can improve performance of the power modules 100 while increasing heat dissipation of the SSDC package 500. A mini-heart design that overlaps positive and negative power tabs and routes high currents through clips of the power tabs can lower stray inductance and thermal resistance relative to a design that relies on a current path within the conductive layers of the DBM 102. The power tabs can be incorporated into the SSDC package 500, and can be cooled by a heat sink in the base plate 510 of the SSDC package 500. A water jacket can be added to the base plate 510 to provide additional cooling.
It will be understood that, in the foregoing description, when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.
As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, top, bottom, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.
Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor device processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and/or so forth.
While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. For instance, features illustrated with respect to one implementation can, where appropriate, also be included in other implementations. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.
This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63/455,822, filed on Mar. 30, 2023, entitled “Single Side Direct Cooling (SSDC) Device,” the disclosure of which is incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63455822 | Mar 2023 | US |
