The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2013-207370, filed Oct. 2, 2013, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a printed wiring board having metal posts for mounting another printed wiring board (upper substrate) and to a method for manufacturing such a printed wiring board.
2. Description of Background Art
JP2003-8228A describes a method for forming a metal post on a pad of a printed wiring board. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a method for manufacturing a printed wiring board includes forming a resin insulation layer on an interlayer resin insulation layer and conductive circuits such that the resin insulation layer has first opening portions exposing pad portions in a central portion of the interlayer resin insulation layer and second opening portions exposing pad portions in a peripheral portion of the interlayer resin insulation layer, forming a seed layer on the resin insulation layer such that the seed layer is formed on the resin insulation layer, in the first and second opening portions and on the pad portions exposed through the first and second opening portions, forming on the seed layer a plating resist such that the plating resist has resist opening portions exposing the second opening portions and having diameters greater than the second opening portions, respectively, filling the resist opening portions with electrolytic plating material via the seed layer such that metal posts are formed in the resist opening portions, respectively, removing the plating resist from the resin insulation layer, and removing the seed layer exposed on the resin insulation layer by the removing of the plating resist.
According to another aspect of the present invention, a printed wiring board includes an interlayer resin insulation layer, pad portions formed on the interlayer resin insulation layer, a resin insulation layer formed on the interlayer resin insulation layer and the pad portions such that the resin insulation layer has first opening portions exposing the pad portions in a central portion of the interlayer resin insulation layer and second opening portions exposing the pad portions in a peripheral portion of the interlayer resin insulation layer, and metal posts formed on the pad portions in the peripheral portion of the interlayer resin insulation layer, respectively, and having curved side-wall portions forming narrowed portions between the end portions and opposite end portions of the metal posts, respectively.
According to yet another aspect of the present invention, a package-on-package device includes a first substrate, an IC chip mounted on the first substrate, a second substrate mounted on the first substrate, and a mold resin layer filling the space formed between the first substrate and the IC chip. The first substrate includes an interlayer resin insulation layer, pad portions formed on the interlayer resin insulation layer, a resin insulation layer formed on the interlayer resin insulation layer and the pad portions such that the resin insulation layer has first opening portions exposing the pad portions in a central portion of the interlayer resin insulation layer and second opening portions exposing the pad portions in a peripheral portion of the interlayer resin insulation layer, and metal posts formed on the pad portions in the peripheral portion of the interlayer resin insulation layer, respectively, and having curved side-wall portions forming narrowed portions between the end portions and opposite end portions of the metal posts, respectively, the mold resin layer has opening portions exposing the end portions of the metal posts, respectively, the first substrate has first bumps mounting the IC chip on the pad portions in the central portion of the interlayer resin insulation layer, and the second substrate has second bumps connecting to the end portions of the metal posts exposed from the opening portions of the mold resin layer.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
Printed wiring board 10 has pads (first pads) (710FI) for mounting electronic component 90 such as an IC chip, and pads (second pads) (710FP) for mounting another printed wiring board (upper substrate) 110. Electronic component 900 such as a memory is mounted on the other printed wiring board. Pad group (C4) is formed with multiple pads (710FI) (see FIG. 3(A)), and pad group (C4) is formed in an approximate center of printed wiring board 10. Pads (710FP) are formed in peripheral region (P4) surrounding pad group (C4) (see
The printed wiring board of the present embodiment may have a core substrate, or it may be a coreless printed wiring board. A printed wiring board with a core substrate and its manufacturing method are described in JP2007-227512A, for example. The entire contents of JP2007-227512A are incorporated herein by reference. A coreless substrate and its manufacturing method are described in JP2005-236244A, for example.
Such a coreless substrate is formed by alternately laminating an interlayer resin insulation layer and a conductive layer, and all the interlayer resin insulation layers each have a thickness of 60 μm or less, for example.
Printed wiring board 10 of the first embodiment has core substrate 30. The core substrate has insulative base (20z) having first surface (F) and second surface (S) opposite the first surface, first conductive layer (34F) formed on first surface (F) of the insulative substrate and second conductive layer (34S) formed on the second surface of the insulative substrate. The core substrate is further provided with through-hole conductor 36 made by filling plating film in penetrating hole 28 for a through-hole conductor formed in insulative base (20z). Through-hole conductor 36 connects first conductive layer (34F) and second conductive layer (34S). The first surface of the core substrate corresponds to the first surface of the insulative base, and the second surface of the core substrate corresponds to the second surface of the insulative base.
Interlayer resin insulation layer (uppermost interlayer resin insulation layer) (50F) is formed on first surface (F) of core substrate 30. Conductive layer (uppermost conductive layer) (58F) is formed on interlayer resin insulation layer (50F). Conductive layer (58F) is connected to first conductive layer (34F) or a through-hole conductor by via conductor (uppermost via conductor) (60F) which penetrates through interlayer resin insulation layer (50F). Upper buildup layer (55F) is made up of interlayer resin insulation layer (50F), conductive layer (58F) and via conductors (60F). The upper buildup layer in the first embodiment is single layered. The uppermost conductive layer has pads (710FI, 710FP). Top surfaces of conductive circuits included in the uppermost conductive layer and top surfaces of uppermost via conductors make pads (710FI, 710FP).
Interlayer resin insulation layer (lowermost interlayer resin insulation layer) (50S) is formed on second surface (S) of core substrate 30. Conductive layer (lowermost conductive layer) (58S) is formed on interlayer resin insulation layer (50S). Conductive layer (58S) is connected to second conductive layer (34S) or a through-hole conductor by via conductor (lowermost via conductor) (60S) which penetrates through interlayer resin insulation layer (50S). Lower buildup layer (55S) is made up of interlayer resin insulation layer (50S), conductive layer (58S) and via conductors (60S). The lower buildup layer in the first embodiment is single layered. The lowermost conductive layer has BGA pads (71SP) for connection with a motherboard. Top surfaces of conductive circuits included in the lowermost conductive layer and top surfaces of lowermost via conductors make pads (71SP).
Upper solder-resist layer (70F) is formed on the upper buildup layer, and lower solder-resist layer (70S) is formed on the lower buildup layer. Solder-resist layer (70F) has opening (first opening) (71FI) to expose pad (710FI) and opening (second opening) (71FP) to expose pad (710FP). Solder-resist layer (70S) has opening (71S) to expose BGA pad (71SP). On BGA pad (71SP), solder bump (76S) is formed for connection with a motherboard. It is an option not to form a solder bump, and instead of a solder bump to form connection material such as Sn film. Solder bump 94 of IC chip 90 is connected to pad (710FI).
Metal post 77 has top portion (77T) and its opposing bottom portion (77B). Solder-plated film 88 is formed on top portion (77T). Metal post 77 has sidewall (77W) between its top and bottom portions. Sidewall (77W) is made of electrolytic plated film 86. Bottom portion (77B) has beheaded circular cone (77Ba) corresponding to the shape of opening (71FP) in solder-resist layer (70F), and ring portion (77Bb) shaped as a ring abutting the surface of solder-resist layer (70F). Seed layer 84 is formed on the surface of bottom portion (77B). The tip end of beheaded circular cone (77Ba) of a metal post faces pad (710FP).
When pitch (p1) is 0.3 mm or less, height (H) (distance from the top to the bottom end) of metal post 77 including the thickness of solder plated film (dp: 20 μm) is 75 μm˜200 μm, and diameter (d1) of metal post 77 is 75 μm˜150 μm. Connection reliability is enhanced between the printed wiring board of the embodiment and the upper substrate, and insulation reliability is improved between metal posts.
When pitch (p1) is 0.25 mm or less, height (H) of metal post 77 is 100 μm˜200 μm, and diameter (d1) of metal post 77 is 50 μm˜150 μm. Connection reliability is enhanced between the printed wiring board of the embodiment and the upper substrate, and insulation reliability is improved between metal posts.
The aspect ratio (height H/diameter d1) of a metal post is preferred to be greater than 1. A metal post with such a ratio mitigates stress between the printed wiring board of the present embodiment and the upper substrate, resulting in enhanced connection reliability. The aspect ratio (H/d1) is preferred to be 0.6˜3. Stress is mitigated between printed wiring board 10 and the upper substrate. In addition, the metal post will not deteriorate from fatigue, and connection reliability is enhanced between the upper substrate and printed wiring board 10.
Regarding distance (H) from the top surface of pad (710FP) to the top portion of a metal post and thickness (c1) of pad (710FP), the ratio (H/c1) is preferred to be at least 5 but 30 or smaller. When pitch (p1) is 0.3 mm or less, the value of (H/c1) is preferred to be at least 7 but 25 or smaller. Since pad (710FP) is the base of a metal post, if the value of (H/c1) is too great, the metal post may break off from the pad or the reliability of the metal post may decrease. On the other hand, if the value of (H/c1) is too small, it is hard for the metal post to mitigate stress, and connection reliability decreases.
In the first embodiment, pitch (p1) can be reduced. Since there is enough space between adjacent metal posts, insulation reliability between metal posts is high even when pitch (p1) is 0.3 mm or less. Pitch (p1) at 0.25 mm or less makes metal posts thinner. To enhance connection reliability, the aspect ratio (H/d1) of a metal post is preferred to be 0.6 or greater. When the number of pads (710FP) increases, the size of the printed wiring board increases. However, if the aspect ratio (H/d1) of a metal post is 2 or greater, such a metal post can mitigate stress caused by differences in physical properties between the upper substrate and the printed wiring board. When the value of (H/d1) exceeds 3.5, the metal post deteriorates because of heat cycles. Examples of physical properties are a thermal expansion coefficient, Young's modulus and the like.
As shown in
Using a laser, first opening (71FI) is formed in upper solder-resist layer (70F), first pad (710FI) is exposed, second opening (71FP) is formed, and second pad (710FP) is exposed. In the same manner, opening (71SP) is formed in lower solder-resist layer (70S) and pad (710SP) is exposed (
Resist (82S) is formed on the surface of lower solder-resist layer (70S) (
On solder-resist layer (70F) of printed wiring board 10, plating resist (82F) is formed to have resist opening (82A) which exposes second opening (71FP) and has a diameter greater than the second opening (
Seed layer 84, which is formed on solder-resist layer (70F) and is left exposed by metal post 77, is removed, and lower resist (82S) is also removed (
On first pad (710FI) exposed from solder-resist layer (70F) of printed wiring board 10, IC chip 90 is mounted by means of solder bump 94 formed on pad 92 (
Other printed wiring board (upper substrate) 110 is bonded to metal post 77 by means of solder bump 112 so as to be mounted on printed wiring board 10 (
In the method for manufacturing a printed wiring board according to the first embodiment, solder-resist layer (70F) is formed to have first opening (71FI) for connection with an IC chip and a second opening (71FP) for forming a metal post that is subsequently connected to the upper substrate. Metal post 77 is formed first in the second opening, and a solder bump is not formed in the first opening. Since metal post 77 is not affected by a solder bump, reliability is improved during the formation of the metal post, thus enhancing connection reliability between the upper substrate and the metal post.
In the second embodiment, sidewall (77W) of metal post 77 is curved, making the diameter smaller in a portion between the top surface and the bottom surface. Since the metal post has a narrowed portion, the metal post tends to be deformed, and stress is likely to be mitigated. Even when pitch (p1) of pads (710FP) is 0.3 mm or less, connection reliability does not decrease between the printed wiring board of the embodiment and the upper substrate.
In a printed wiring board according to the second embodiment, sidewall (77W) of metal post 77 is curved, forming a narrowed portion between its top and bottom portions. Accordingly, the rigidity of the metal post is reduced and stress is mitigated by the metal post, resulting in enhanced connection reliability between the upper substrate and the metal post. In addition, since the area of sidewall (77W) of metal post 77 increases, the area also increases where the metal post makes contact with mold resin 80 that encapsulates metal post 77, and the reliability of the metal post is enhanced.
The same as in the first embodiment described above with reference to
When a printed wiring board is provided with bumps for mounting an IC chip and metal posts for mounting an upper substrate, the distance between the upper substrate and the printed wiring board is greater than the distance between the IC chip and the printed wiring board. Thus, connection reliability is thought to decrease when the upper substrate is connected to the printed wiring board by tall metal posts.
A printed wiring board according to an embodiment of the present invention and a method for manufacturing such a printed wiring board according to an embodiment of the present invention are capable of enhancing connection reliability between the printed wiring board and an upper substrate mounted on the printed wiring board.
A method for manufacturing a printed wiring board according to an embodiment of the present invention is characterized by the following: on an outermost interlayer resin insulation layer and on conductive circuits, forming a solder-resist layer having a first opening to expose a conductive circuit in a central portion of the printed wiring board as well as a second opening to expose a conductive circuit in a peripheral portion of the printed wiring board; forming a seed layer on the solder-resist layer, in the first and second openings, and on the conductive circuits exposed through the first and second openings; on the seed layer, forming a plating resist to have a resist opening which exposes a second opening and has a diameter greater than the second opening; forming a metal post by filling the resist opening with electrolytic plating by means of the seed layer; removing the plating resist; removing the seed layer left exposed on the solder-resist layer; and forming an antioxidant surface-treatment film on the conductive circuit exposed through the first opening.
A printed wiring board according to an embodiment of the present invention has an uppermost interlayer resin insulation layer, a pad formed on the uppermost interlayer resin insulation layer, and a metal post formed on the pad. The sidewall of the metal post is curved, having a narrowed portion between the top and bottom.
In a method for manufacturing a printed wiring board according to an embodiment of the present invention, a solder-resist layer is formed to have a first opening for connection with an IC chip and a second opening for forming a metal post to be connected with an upper substrate. A metal post is formed first in the second opening, and a solder bump is not formed in the first opening Thus, the metal post is not affected by the solder bump. Accordingly, reliability is improved during a process of forming the metal post, and connection reliability between the upper substrate and the metal post is thereby enhanced.
In a printed wiring board according to an embodiment of the present invention, the sidewall of a metal post is curved, having a narrowed portion between the top and bottom portions. Therefore, the rigidity of the metal post is lowered, and stress is mitigated by the metal post. Accordingly, connection reliability is enhanced between the upper substrate and the metal post. In addition, since the area of the side surfaces of the metal post increases, the contact area of the metal post and mold resin also increases when the metal post is encapsulated by the mold resin, and the reliability of the metal post is thereby enhanced.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
Number | Date | Country | Kind |
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2013-207370 | Oct 2013 | JP | national |