Semiconductor apparatus containing multi-chip package structures

Abstract

The present invention is applied to a semiconductor apparatus using a lead frame as a base frame. A semiconductor apparatus according to the present invention includes a first multi-chip structure, which comprises a plurality of semiconductor chips mounted on the base frame and a terminal region formed on at least one surface of the multi-chip structure, the terminal region being connected electrically to an external component; and a second multi-chip structure, which comprises a plurality of semiconductor chips mounted on the base frame and a terminal region formed on at least one surface of the multi-chip structure, the terminal region being connected electrically to an external component. Inner leads of the base frame are connected to the terminal region of the first multi-chip structure by a wire-bonding process and to the terminal region of the second multi-chip structure by a wire-bonding process.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a semiconductor apparatus according to a first preferred embodiment of the present invention.

FIG. 2 is a plane view illustrating a semiconductor apparatus according to the first preferred embodiment, shown in FIG. 1.

FIGS. 3A-3D are cross-sectional views illustrating fabrication steps of a semiconductor apparatus according to the first preferred embodiment, shown in FIG. 1.

FIG. 4 is a cross-sectional view illustrating a semiconductor apparatus according to a second preferred embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a semiconductor apparatus according to a third preferred embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a semiconductor apparatus according to a fourth preferred embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a semiconductor apparatus according to a fifth preferred embodiment of the present invention.

Claims

1. A semiconductor apparatus using a lead frame as a base frame, comprising: a first multi-chip structure, which comprises a plurality of semiconductor chips mounted on the base frame and a terminal region formed on at least one surface of the multi-chip structure, wherein the terminal region can be connected electrically to an external component; anda second multi-chip structure, which comprises a plurality of semiconductor chips mounted on the base frame and a terminal region formed on at least one surface of the multi-chip structure, wherein the terminal region can be connected electrically to an external component,wherein inner leads of the base frame are connected to the terminal region of the first multi-chip structure by a wire-bonding process and to the terminal region of the second multi-chip structure by a wire-bonding process.

2. A semiconductor apparatus using a lead frame as a base frame, comprising: a first multi-chip structure, which comprises a plurality of semiconductor chips mounted on a first surface of the base frame and a terminal region formed on a surface opposing to the first surface of the multi-chip structure, wherein the terminal region can be connected electrically to an external component; anda second multi-chip structure, which comprises a plurality of semiconductor chips mounted on a second surface opposing to the first surface of the base frame and a terminal region formed on a surface opposing to the second surface of the multi-chip structure, wherein the terminal region can be connected electrically to an external component,wherein inner leads of the base frame are connected to the terminal region of the first multi-chip structure by a wire-bonding process and to the terminal region of the second multi-chip structure by a wire-bonding process.

3. A semiconductor apparatus according to claim 2, wherein at least one of the first multi-chip structure and the second multi-chip structure is of a QFN package, in which a plurality of semiconductor chips are layered and mounted on a lead frame.

4. A semiconductor apparatus according to claim 3, wherein both the first multi-chip structure and the second multi-chip structure are of QFN packages,each of the QFN packages comprises a resin portion sealing the semiconductor chips mounted on the lead frame, andthe resin portion has a first surface located at a side of the lead frame and a second surface located at the counter side of the lead frame.

5. A semiconductor apparatus according to claim 4, wherein the second surface of the resin portion of the QFN structure for the first multi-chip structure is adhered to the first surface of the base frame; andthe second surface of the resin portion of the QFN structure for the second multi-chip structure is adhered to the second surface of the base frame.

6. A semiconductor apparatus according to claim 2, wherein at least one of the first multi-chip structure and the second multi-chip structure is of a LGA package, in which a plurality of semiconductor chips are layered and mounted on a printed-circuit board.

7. A semiconductor apparatus according to claim 2, wherein both the first multi-chip structure and the second multi-chip structure are LGA packages, in which a plurality of semiconductor chips are layered and mounted on a printed-circuit board,the LGA package comprises a resin portion sealing the semiconductor chips mounted on the printed-circuit board, andthe resin portion has a first surface located at a side of the printed-circuit board and a second surface located at the counter side of the printed-circuit board.

8. A semiconductor apparatus according to claim 7, wherein the second surface of the resin portion of the LGA package for the first multi-chip structure is adhered to the first surface of the base frame; andthe second surface of the resin portion of the LGA package for the second multi-chip structure is adhered to the second surface of the base frame.

9. A semiconductor apparatus according to claim 1, wherein the first multi-chip structure and the second multi-chip structure are LGA packages, in which a plurality of semiconductor chips are layered and mounted on a printed-circuit board,the first multi-chip structure is formed to be larger in size than the second multi-chip structure,the base frame comprises a die pad, andthe first multi-chip structure is mounted on the die pad of the base frame, and the second multi-chip structure is mounted on the first multi-chip structure.

10. A semiconductor apparatus according to claim 9, wherein the first multi-chip structure comprises a resin portion sealing the semiconductor chips, which has a first surface located at a side of the printed-circuit board and a second surface located at the counter side of the printed-circuit board to seals the semiconductor chips mounted in the structure,the second multi-chip structure comprises a resin portion sealing the semiconductor chips, which has a first surface located at a side of the printed-circuit board and a second surface located at the counter side of the printed-circuit board to seals the semiconductor chips mounted in the structure,the second surface of the resin portion of the first multi-chip structure is adhered to the die pad of the base frame,the second surface of the resin portion of the second multi-chip structure is adhered to a rear surface of the printed circuit board of the first multi-chip structure,rear surfaces of the printed-circuit boards of the first and second multi-chip structures are electrically connected to each other using bonding wires, andthe rear surface of the printed-circuit board of the first multi-chip structure is electrically connected to the inner leads of the base frame using bonding wires.

11. A semiconductor apparatus according to claim 1, wherein the plural semiconductor chips are arranged to be offset in a horizontal direction from each other, andthe connection between every semiconductor ships is carried out by a wire-bonding process.

12. A semiconductor apparatus according to claim 2, wherein the plural semiconductor chips are arranged to be offset in a horizontal direction from each other, andthe connection between every semiconductor ships is carried out by a wire-bonding process.

13. A semiconductor apparatus according to claim 1, further comprising: a seal resin which seals the first and second multi-chip structures entirely.

14. A semiconductor apparatus according to claim 2, further comprising: a seal resin which seals the first and second multi-chip structures entirely.