Claims
- 1. A layered semiconductor configuration to be soldered to a metal substrate plate, comprising:
- a silicon semiconductor body;
- an aluminum layer disposed on said silicon semiconductor body, said aluminum layer being at least partially tempered before any further layering;
- a titanium layer disposed on said aluminum layer; and
- a titanium nitride layer disposed in said titanium layer and acting as a diffusion barrier layer.
- 2. The semiconductor configuration according to claim 1, including a nickel layer disposed on said titanium layer.
- 3. The semiconductor configuration according to claim 1, including a solder material layer disposed on said titanium layer.
- 4. The semiconductor configuration according to claim 2, including an oxidation protection layer disposed on said nickel layer.
- 5. The semiconductor configuration according to claim 4, including an adhesion promoter layer disposed between said nickel layer and said oxidation protection layer.
- 6. The semiconductor configuration according to claim 3, wherein said solder material layer is selected from the group consisting of a tin layer, a lead layer and a gallium layer.
- 7. A layered semiconductor configuration to be soldered to a metal substrate plate, comprising:
- a silicon semiconductor body;
- an aluminum layer disposed on said silicon semiconductor body;
- a titanium layer disposed on said aluminum layer; and
- a titanium nitride layer disposed in said titanium layer and acting as a diffusion barrier layer;
- a nickel layer disposed on said titanium layer;
- an oxidation protection layer disposed on said nickel layer.
- 8. The semiconductor configuration according to claim 7, including an adhesion promoter layer disposed between said nickel layer and said oxidation protection layer.
- 9. A layered semiconductor configuration to be soldered to a metal substrate plate, comprising:
- a silicon semiconductor body;
- an aluminum layer disposed on said silicon semiconductor body;
- a titanium layer disposed on said aluminum layer; and
- a titanium nitride layer disposed in said titanium layer and acting as a diffusion barrier layer;
- a solder material layer disposed on said titanium layer.
- 10. The semiconductor configuration according to claim 9, wherein said solder material layer is selected from the group consisting of a tin layer, a lead layer and a gallium layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
197 34 434 |
Aug 1997 |
DEX |
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CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation of copending International Application PCT/DE98/02199, filed Jul. 31, 1998, which designated the United States.
US Referenced Citations (7)
Foreign Referenced Citations (4)
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Country |
0 720 231 A2 |
Jul 1996 |
EPX |
38 23 347 A1 |
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DEX |
92 12 486 |
Apr 1993 |
DEX |
196 03 654 C1 |
Jul 1997 |
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Non-Patent Literature Citations (1)
Entry |
"High Reliability Microwave Silicon Power Transistor With Stepped Electrode Structure and TiN Diffusion Barrier" (Kanamori et al.), IEEE Transactions on Electron Devices, vol. ED-33, No. 3, Mar. 1986, pp. 402-408. |
Continuations (1)
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Number |
Date |
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Parent |
PCTDE9802199 |
Jul 1998 |
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