Patent Application
20110215384
This invention relates to a semiconductor device and its manufacturing method and, in particular, relates to a semiconductor device having one or both of a shallow trench isolation (hereinafter abbreviated as STI) structure and an interlayer insulating film structure and to its manufacturing method.
A semiconductor device having an STI structure is configured such that an element isolation region made of an insulating film is formed in a shallow trench (shallow trench) provided on a surface of a semiconductor substrate and semiconductor elements are formed in a plurality of element forming regions isolated from each other by the element isolation region. On the other hand, a semiconductor device having an interlayer insulating film structure is configured such that at least one interlayer insulating film is provided over a surface of a semiconductor substrate and an element isolation region, an electrode layer is formed to penetrate the interlayer insulating film so as to be electrically connected to at least one of a plurality of regions forming each of semiconductor elements, and a wiring layer is formed on the interlayer insulating film so as to be electrically connected to the electrode layer. In general, a normal semiconductor LSI has both of these two structures.
Both structures are common in that a CMP (chemical-mechanical polishing) process is required. That is, in order to form each of the structures, it is essential to perform the CMP process in the manufacture of conventional semiconductor devices. In the formation of the STI structure, the insulating film is formed on the semiconductor substrate including the shallow trench and, since unevenness of the trench appears on a surface of the insulating film, a technique is employed that flattens the surface of the insulating film by CMP to cause the insulating film to remain only in the shallow trench, thereby forming the element isolation region. On the other hand, the interlayer insulating film is often formed by CVD using BPSG (boro-phospho-silicate glass) as a material thereof. In this case, since unevenness of the surface of the semiconductor substrate before the CVD formation (e.g. due to the protrusion of gate electrode portions) appears on a surface of the BPSG film, it is necessary, after forming the BPSG film, to polish its surface by CMP to flatten it. After flattening it, the formation of the penetrating electrode layer and the formation of the wiring layer on the interlayer insulating film are carried out as described above. Further, when a second-layer interlayer insulating film is provided over such an interlayer insulating film, its surface is also flattened by CMP.
In the case of the semiconductor device having the STI structure and the interlayer insulating film structure, it is necessary to repeat CMP a number of times. Since the CMP process itself is a costly process as compared with etching or the like, the repetition of CMP is a cause to increase the cost of semiconductor devices to be manufactured.
Further, when BPSG forming the interlayer insulating film is polished by CMP, since there is no stopper for the BPSG, there is a possibility that the BPSG is excessively polished to damage gate electrodes. Therefore, it is necessary to carry out the CMP in a state with an extra margin and thus there is a drawback that the thickness of the BPSG should be large.
Patent Document 1 discloses, as a process of burying an STI trench with an insulating film, a process that coats a solution of polysilazane or the like on a silicon substrate to bury an STI trench with the solution and then converts the solution to a SiO2 film for element isolation by a high-temperature treatment (Patent Document 1, paragraph 0009).
Patent Document 2 discloses, as a substitute process for a BPSG process, a process that cures a spin-on-glass film containing polysilazane by the use of an oxidant solution and then converts it to a silicon oxide film by a heat treatment, thereby forming the silicon oxide film. In order to improve the flatness of a surface of the formed silicon oxide film, Patent Document 2 also discloses that further processing such as a CMP process, a dry etching process, or a wet etching process is applied to the silicon oxide film.
Patent Document 1: JP-A-2005-285818
Patent Document 2: JP-A-2005-45230
According to Patent Document 1, by the use of the coating film using polysilazane as its material, even if the aspect ratio of the shallow trench is high, the shallow trench can be uniformly buried (Patent Document 1, paragraph 0048). However, Patent Document 1 points out that a CMP process for surface polishing is essential for leaving the element isolation region in the shallow trench. In other words, Patent Document 1 does not point out the problem followed by the CMP process.
Patent Document 2 discloses forming the insulating coating film in the form of the spin-on-glass film containing polysilazane by the coating formation. However, the spin-on-glass film shown in Patent Document 2 has a large number of voids and thus cannot be used as it is, and hence, further processing is essential for improving the flatness. Therefore, various processes are required to increase the cost.
Further, Patent Documents 1 and 2 each only disclose converting the insulating coating film completely to the silicon oxide film, but fail to pay attention to reducing the permittivity of the interlayer insulating film. Further, neither of them suggests anything about producing films with mutually different properties from a single insulating coating film.
Therefore, it is a technical object of this invention to provide a semiconductor device that makes it possible to form an element isolation region and/or an interlayer insulating film without performing CMP, and a method of manufacturing the semiconductor device.
It is a further technical object of this invention to provide a semiconductor device that makes it possible to reduce the manufacturing cost, and a method of manufacturing the semiconductor device.
It is another technical object of this invention to provide a semiconductor device in which an interlayer insulating film having a low permittivity is formed without CMP, and a method of manufacturing the semiconductor device.
It is still another technical object of this invention to provide a semiconductor device in which an element isolation region and an interlayer insulating film having mutually different permittivities are formed from the same composition, and a method of manufacturing the semiconductor device.
According to the invention, therei obtained a semiconductor device comprising an element isolation region, wherein: said element isolation region includes an insulating film made of SiO2 obtained by modifying, by a heat treatment, a coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0).
Moreover, in accordance with the present invention, there is obtained a semiconductor device, wherein said insulating film has a surface flatness of 0.27 μm or less in Ra and 2.6 μm or less in P-V (peak-to-valley) value.
Further, in accordance with the present invention, there is obtained a semiconductor device, wherein said element isolation region has a depth of 0.26 μm or less and a width of 0.22 μm or less.
According to the invention, there is obtained a semiconductor device, wherein said insulating film has a flatness of a degree that does not require CMP.
According to the invention, there is obtained a method of manufacturing a semiconductor device comprising an element isolation region, said method comprising: a step of forming a shallow trench on a semiconductor substrate for forming said element isolation region, a step of coating a coating film on said semiconductor substrate including said shallow trench, and a step of modifying said coating film to an element isolation insulator, wherein said coating film comprises one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0), and said step of modifying is a step of modifying said coating film to a SiO2 film by a heat treatment.
According to the invention, there is obtained a method of manufacturing a semiconductor device, wherein said heat treatment is performed at a temperature of 800 to 900° C.
According to the invention there is obtained a method of manufacturing a semiconductor device, said method further comprising a step of causing a surface of said modified SiO2 film to be equal in height to a surface of said semiconductor substrate without performing CMP.
According to the invention, there is provided a method of manufacturing a semiconductor device, wherein said step of causing a surface of said modified SiO2 film to be equal in height to a surface of said semiconductor substrate is an etching step.
According to the invention, there is obtained a method of manufacturing a semiconductor device, said method further comprising a step of forming an interlayer insulating film, wherein said step of forming an interlayer insulating film comprises a step of coating a coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0) and a step of heat-treating said coating film at a temperature equal to or less than the temperature in said step of modifying.
According to the invention, there is obtained a method of manufacturing a semiconductor device, wherein the temperature equal to or less than the temperature in said step of modifying is a temperature of 600° C. or less.
According to the invention, there is obtained a method of manufacturing a semiconductor device, wherein the temperature equal to or less than the temperature in said step of modifying is a temperature of 400° C. or less.
According to the invention, there is obtained a method of manufacturing a semiconductor device, wherein said step of forming an interlayer insulating film is performed after a step of forming a source region and a drain region in an element forming region of said semiconductor substrate defined by said element isolation region and a step of forming a gate electrode on said element forming region through a gate insulating film and comprises said step of coating a coating film so as to bury said gate electrode.
According to the invention, there is obtained a method of manufacturing a semiconductor device, said method comprising, after said step of forming an interlayer insulating film, a step of forming an electrode reaching at least one of said source region and said drain region, said electrode penetrating said interlayer insulating film.
According to the invention, there is obtained a semiconductor device comprising an interlayer insulating film of a multilayer structure, said semiconductor device wherein a lowermost layer of said interlayer insulating film includes a coating film expressed by a general formula of
((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0).
According to the invention, there is obtained a semiconductor device, wherein an interlayer insulating film as said lowermost layer is an insulating film burying therein a gate electrode of said semiconductor device.
According to the invention, there is obtained a semiconductor device, wherein an electrode reaching at least one of a source region and a drain region of a semiconductor substrate is provided so as to penetrate said interlayer insulating film as said lowermost layer.
According to the invention, there is obtained a semiconductor device, wherein said interlayer insulating film has a permittivity lower than that of SiO2.
According to the invention, there is obtained a semiconductor device, wherein the permittivity of said interlayer insulating film is 2.0 to 2.7.
According to the invention, there is obtained a semiconductor device, wherein the permittivity of said interlayer insulating film is 2.2 to 2.5.
According to the invention, there is obtained a semiconductor device, wherein an element isolation region formed in a semiconductor substrate is provided under said interlayer insulating film as said lowermost layer and said element isolation region includes a SiO2 film formed by modifying a coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0).
According to the invention, there is obtained a semiconductor device manufacturing method comprising a step of forming a plurality of semiconductor elements on a semiconductor substrate, a step of forming a first interlayer insulating film on said semiconductor substrate, a step of forming an electrode layer that penetrates said first interlayer insulating film so as to be electrically connected to at least one of a plurality of regions forming each of said semiconductor elements, and a step of forming a first wiring layer on said first interlayer insulating film so as to be electrically connected to said electrode layer, wherein said step of forming a first interlayer insulating film comprises a step of coating a first coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0) and a step of forming a first insulating film having a predetermined permittivity by heat-treating said first coating film at a predetermined temperature.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said predetermined temperature is a temperature of 400° C. or less.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said predetermined permittivity is a permittivity lower than that of SiO2.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said predetermined permittivity is 2.0 to 2.7.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said predetermined permittivity is 2.2 to 2.5.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said plurality of regions forming each of said semiconductor elements include a source region, a drain region, and a gate electrode.
According to the invention, there is obtained a semiconductor device manufacturing method, further comprising a step of forming a second interlayer insulating film on said first interlayer insulating film so as to cover said first wiring layer, a step of forming a first conductor VIA layer that penetrates said second interlayer insulating film so as to be electrically connected to at least part of said first wiring layer, and a step of forming a second wiring layer on said second interlayer insulating film so as to be electrically connected to said first conductor VIA layer.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said step of forming a second interlayer insulating film comprises a step of coating a second coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0) and a step of forming a second insulating film having a predetermined permittivity by heat-treating said second coating film at a predetermined temperature.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said step of forming a first wiring layer on said first interlayer insulating film is performed without treating a surface of said first interlayer insulating film by CMP.
According to the invention, there is obtained a semiconductor device manufacturing method according to claim 28, wherein said step of forming a second wiring layer on said second interlayer insulating film is performed without treating a surface of said second interlayer insulating film by CMP.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein a step of forming a shallow trench on said semiconductor substrate, a step of forming an element isolation region in said shallow trench, and a step of forming said plurality of regions forming each of said semiconductor elements are performed before said step of forming a first interlayer insulating film on said semiconductor substrate.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said step of forming said plurality of regions forming each of said semiconductor elements comprises a step of forming a source region and a drain region in an element forming region of said semiconductor substrate defined by said element isolation region and a step of forming a gate electrode on said element forming region through a gate insulating film.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said step of forming an element isolation region comprises a step of coating a third coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0) so as to bury at least said shallow trench and a step of modifying said third coating film to SiO2.
According to the invention, there is obtained a semiconductor device manufacturing method, wherein said step of modifying to SiO2 comprises a step of baking and annealing said coated third coating film at 800° C. to 900° C.
According to the invention, there is obtained a method of manufacturing a semiconductor device comprising an element isolation region and an interlayer insulating film, wherein mutually different heat treatments are applied to the same composition, thereby forming said element isolation region and said interlayer insulating film having mutually different permittivities.
According to the invention, there is obtained a method of manufacturing a semiconductor device, wherein said composition comprises one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0).
According to the invention, there is obtained a method of manufacturing a semiconductor device, wherein formation of said element isolation region and said interlayer insulating film includes no CMP process.
According to the invention, there is obtained a semiconductor device comprising a semiconductor substrate, a semiconductor element having a plurality of regions and formed on said semiconductor substrate, a first interlayer insulating film formed on said semiconductor substrate, an electrode layer penetrating said first interlayer insulating film so as to be electrically connected to at least one of said plurality of regions, and a first wiring layer provided on said first interlayer insulating film so as to be electrically connected to said electrode layer, wherein said first interlayer insulating film includes a first coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0).
Preferably, said semiconductor element includes a gate electrode formed on said semiconductor substrate through a gate insulating film and said first interlayer insulating film buries said gate electrode therein.
In a preferred aspect, said plurality of regions include a source region and a drain region and said electrode layer is electrically connected to at least one of said source region and said drain region.
Preferably, said inerlater insulating film has a permittivity lower than that of SiO2.
According to a manufacturing method of this invention, it is possible to form an element isolation region and/or an interlayer insulating film without using CMP and thus to reduce the manufacturing cost of a semiconductor device.
According to this invention, it is possible to form insulating films having different permittivities from a single composition by changing the heat treatment temperature and thus to simplify the manufacturing processes.
Hereinbelow, embodiments of this invention will be described with reference to the drawings.
Further, a shallow trench (ST) 57 for element isolation is formed on a surface of a boundary portion between the n-well 51 and the p-well 52 and surfaces of the n-well and the p-well. The illustrated shallow trench 57 has a width of 0.22 μm and a depth of 0.25 μm.
The surfaces of the n-well 51 and the p-well 52 are formed with a SiO2 film 11 and a bottom surface and side surfaces of the shallow trench 57 are also formed with a SiO2 film 58.
An insulating coating film 110 according to this invention is coated on the illustrated SiO2 films 11 and 58. The insulating coating film 110 is formed by coating a material having a composition of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and 0≦x≦1.0).
As is clear from the composition ((CH3)nSiO2-n/2)x(SiO2)1-x of the insulating coating film 110, the insulating coating film contains Si, C, and O and the ratio of the numbers of these component atoms is O>Si≧C. The insulating coating film 110 contains a methyl group (CH3) and the methyl group is liberated in air at 480° C. but is not liberated in N2 even at 600° C. Herein, if x=1.0, i.e. in a state of only a CH3SiO3/2 component, the relative permittivity k of the insulating coating film is 2.0, if x=0.9, k is 2.1, if x=0.7, k is 2.3, and if x=0.5, k is 2.7. As a coating solution, use is made of one in which 5 wt % or more of the above-mentioned composition is dissolved in a solvent and, after coating it, heating is applied under a reduced pressure to completely remove the solvent.
If heating is applied at 500° C. under a reduced pressure of 1 to 4 Torr, the insulating coating film with k of 2.0 to 2.1 is obtained and, if heating is applied at 400° C. under a reduced pressure of 1 to 5 Torr, the insulating coating film with k of 2.3 to 2.7 is obtained. If heating is applied at 800° C., the methyl group is liberated so that the insulating coating film 110 is modified to SiO2 and, only with the SiO2, the relative permittivity k becomes 4.0. The insulating properties of this SiO2 exhibit excellent values of 1×10 −10 (A/cm2) at 1 (MV/cm), 1×10−9 (A/cm2) at 3 (MV/cm), and 1×10−8 (A/cm2) even at 5 (MV/cm).
Hereinbelow, the above-mentioned insulating coating film and its composition may be abbreviated as a SiCO film and SiCO, respectively. Since the coating solution forming the insulating coating film (SiCO film) 110 is in a liquid state at ordinary temperature, the insulating coating film 110 can be spin-coated on the semiconductor substrate and has fluidity in a coated state so that it does not reflect unevenness of the bottom surface and thus has high flatness.
Herein, when the insulating coating film 110 is baked and annealed at 900° C., it is modified to SiO2 (k=4.0) free of gas generation and thermal contraction and excellent in heat resistance. Therefore, if it is necessary to modify the insulating coating film 110 completely to a SiO2 film, such complete modification is enabled. Thus, by selecting heat treatment conditions of the insulating coating film 110 formed by the SiCO film, it is possible to form a surface-flattened film having a permittivity in the range of k=2.0 to 4.0.
Referring back to
Then, when etching the surface-flattened film obtained by baking the insulating coating film 110 formed of SiCO, since the surface-flattened film can be clearly distinguished from a silicon nitride film (Si3N4), the silicon substrate 100, or the like, it can be etched by providing the silicon nitride film (Si3N4) on the SiO2 film 11 and using it as a stopper or by using the silicon substrate 100 as a stopper. Therefore, the surface-flattened film formed of SiCO can be uniformly removed, while maintaining the flatness of its surface, only by etching without using CMP.
The insulating coating film 110 shown in
Referring to
In this case, an STI element isolation region 2a made of SiO2 obtained by completely modifying SiCO remains in the shallow trench 57.
As shown in
Since the SiCO film according to this invention does not require CMP, not only can it be used as the surface-flattened film having the flat surface, it can also form the STI element isolation region excellent in insulating properties with no voids. The permittivity of the element isolation region 2a is 4.0 equal to that of SiO2.
As is also clear from
The SiCO film according to this invention can obtain not only the effect of forming the STI isolation region 2a, but also an effect of making CMP unnecessary and achieving a low permittivity when applied to formation of an interlayer insulating film. Hereinbelow, a description will be given, as an embodiment 2, the case where the SiCO film according to this invention is used as a lowermost-layer interlayer insulating film.
Referring to
In the structure of
Further, p-type element regions (source and drain regions) 74 formed by implanting p-type impurities are provided at the surface of the n-well 51, while n-type element regions (source and drain regions) 76 formed by implanting n-type impurities are provided at the surface of the p-well 52. A silicide layer 77 for contact is formed at the surface of each of the element regions (source and drain regions) 74 and 76.
In the illustrated example, the distance between the gate electrodes 72 of two MOS transistors formed on each of the n-well 51 and the p-well 52 is 45 nm.
Referring to
Specifically, as shown in
As described above, since the insulating coating film 18 formed of SiCO maintains high flatness, it is not necessary to carry out flattening by CMP. Further, since it is possible to reduce the relative permittivity k of the interlayer insulating film, the high-speed operation of the device is not impaired. By reducing the relative permittivity, it is possible to reduce the parasitic capacitance of the electrodes and wiring and thus to achieve high-speed transmission of signals.
There are a variety of processes after forming the interlayer insulating film 18 shown in
Hereinbelow, processes in the case where a multilayer wiring structure is provided over the interlayer insulating film 18 will be exemplarily described.
Referring to
In the illustrated example, electrode lead-out conductors 78 to the contact layers 77 and gate wirings 19 to the gate electrodes 72 of the MOS transistors are formed by applying normal techniques such as resist coating, exposure, and etching to the lowermost-layer interlayer insulating film 18 and, further, wirings 8 respectively connected to the source/drain regions of the MOS transistors are buried in via holes of the smooth film 21. As a material of the conductors 78, the gate wirings 19, and the wirings 8, Cu or W can be used. When Cu or W is used, a conductive barrier layer 7 of TiN, TaN, or the like is preferably formed in each via hole as an underlayer for Cu or W.
Referring to
Further, in the illustrated example, a second SiCO barrier layer 26 is formed by CVD on the CFx film 25 as the third-layer interlayer insulating film and a low relative permittivity CFx film 27 is formed as a fourth interlayer insulating film on the second barrier layer 26. Further, a third SiCO barrier layer 28 is formed by CVD on the CFx film 27. As in this example, by forming the interlayer insulating films using the CFx films each having the relative permittivity k still lower than that of the SiCO film baked at the low temperature, the relative permittivity of the entire multilayer-structure interlayer insulating film can be further reduced.
Also in the example shown in
Referring to
Also in the example shown in
In an example shown in
Referring to
Referring to
In each of the examples described above, the lowermost-layer interlayer insulating film 18 is formed by the SiCO coating film that does not require flattening by CMP. Accordingly, it is not necessary to flatten the surface of the lowermost-layer interlayer insulating film 18 by CMP or the like.
Therefore, in the manufacturing method according to this invention, since it is possible to minimize the number of times of using CMP, the cost required for CMP can be reduced. Further, since it is possible to reduce the relative permittivity k of the entire multilayer-structure interlayer insulating film, the stray capacitance and the leakage current can be prevented.
Next, a description will be given of the properties of the SiCO insulating coating film used in this invention.
First, referring to
Referring to
Further, the surface roughness when heated to 600° C. at 20° C/min is given by Rah2 and PVh2, while the surface roughness when heated to 600° C. at 2 to 5° C/min is given by Ral2 and PVl2. Further, the surface roughness when heated to 800° C. at 20° C/min is given by Rah3 and PVh3, while the surface roughness when heated to 800° C. at 2 to 5° C/min is given by Ral3 and PVl3.
As is also clear from
Referring to
On the other hand, when the insulating coating film is baked by heating to 400° C. at a heating rate of 5° C/min, Ra and the P-V value of its surface become 0.2145 nm and 2.593 nm, respectively, and, as is also clear from the
AFM and SEM images, the surface roughness can be made smaller than that when heated at 20° C/min. Likewise, when the insulating coating film is baked by heating to 600° C. at a heating rate of 2° C/min, Ra and the P-V value of its surface become 0.2280 nm and 2.720 nm, respectively, and, when heated to 800° C. at a heating rate of 2° C/min, Ra and the P-V value become 0.2539 nm and 2.602 nm, respectively, so that the surface roughness can be improved in both cases as compared with that when heated at 20° C/min.
From the evaluation results described above, it has been found that the surface smoothness (surface roughness) is improved to Ra=0.27 nm or less by reducing the heating rate in baking to 10° C/min or less (preferably 1 to 5° C/min).
The baking temperature is set to 300 to 900° C. (preferably 400° C. to 800° C.). The flatness of a surface-flattened film is improved by high-temperature baking (800° C.), but the film thickness tends to decrease.
Referring to
Referring to
Likewise, a surface-flattened film obtained by baking at 400° C. the insulating coating film coated to a thickness of 270 nm at a rotation speed of 600 rpm exhibits similar current-voltage characteristics.
To sum up the electrical properties of the surface-flattened film, there is obtained the dielectric film with no change in permittivity or smoothness even if the thickness is changed and with a voltage resistance of 10 (MV/cm) even if the thickness is reduced (100 nm) and it has been found that when the thickness is reduced, current variations occur if the electrode area increases.
In the above-mentioned embodiments, the examples are shown in which use is made of the coating film with the composition of (CH3SiO3/2)x(SiO2)1-x (where 0≦x≦1.0). However, in this formula, instead of CH3SiO3/2, use may be made of, for example, (CH3)2SiO, (CH3)3SiO1/2, or the like, or a mixture thereof. That is, this invention is characterized by using a coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x( SiO2)1-x (where n=1 to 3 and 0≦x≦1.0). Herein, the suffix of first “0” in the general formula is 2-(n/2).
A semiconductor device manufacturing method of this invention can reduce the number of times of CMP and thus is applicable to various semiconductor devices including STI and/or an interlayer insulating film of a multilayer structure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-212505 | Aug 2007 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/064573 | 8/14/2008 | WO | 00 | 2/15/2010 |
