Patent Application
20080174026
The entire disclosure of Japanese Patent Application No. 2007-010572, filed Jan. 19, 2007 is expressly incorporated by reference herein.
1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
In recent years, packages called a wafer level CSP (Chip Scale Package) have been developed, in which external terminals are formed upon formation of wirings over semiconductor chips. JP-A-2003-282790 is an example of related art. A resin layer is formed under the wirings to distribute and absorb a stress generated in the wirings. However, a surface as an active face provided with an integrated circuit becomes deteriorated in heat release performance when being covered with the resin layer. The wirings are also covered with a solder mask except for lands to be mounted with solder balls, thereby having difficulty of releasing heat. Therefore, when a semiconductor device is mounted on a motherboard, most heat generated in the integrated circuit is concentrated on the external terminals to thereby be transferred to the motherboard. Thus, the motherboard is adversely affected by heat.
An advantage of the present invention is to reduce an adverse effect on a motherboard by a resin layer.
According to an aspect of the invention, a semiconductor device includes a semiconductor substrate provided with an integrated circuit and an electrode electrically coupled to the integrated circuit, a first resin layer formed on a surface of the semiconductor substrate, the surface provided with the electrode, a wiring electrically coupled to the electrode and formed on the first resin layer, a metallic layer formed on the first resin layer, a second resin layer provided with a first through hole overlapped with the wiring and a second through hole for exposing a part of the metallic layer, and an external terminal formed inside the first through hole on the wiring.
According to an aspect of the invention, not only the external terminal transfers heat through the wiring, but also the metallic layer receives heat and releases heat through the second through hole. Thus, an adverse effect on a motherboard by heat can be reduced when the semiconductor device is mounted on the motherboard.
It is preferable that the second through hole be formed in a manner to expose an end part of the metallic layer and a part of the first resin layer adjacent to the end part of the metallic layer from the second resin layer.
It is preferable that the second through hole be formed in a manner to expose an entire periphery of the metallic layer from the second resin layer.
It is preferable that the metallic layer have a surface in parallel to the first resin layer, the surface formed in a polygonal shape, and that the second through hole be formed in the second resin layer in a manner to expose a corner of the metallic layer.
It is preferable that the second resin layer cover the entire periphery of the metallic layer.
It is preferable that the second resin layer be further provided with a third through hole overlapped with the metallic layer, and a metallic terminal formed inside the third through hole on the metallic layer.
It is preferable that the second resin layer be provided with a plurality of third through holes, the plurality of metallic terminals be formed by forming at least one metallic terminal inside each of the plurality of third through holes, the plurality of metallic terminals be positioned at a plurality of intersection points of a plurality of first parallel straight lines with a plurality of second parallel straight lines perpendicular to the first straight lines, and that the plurality of metallic terminals be arranged in a manner to set uniform intervals between the adjacent metallic terminals in arrays along either of the first and the second straight lines.
The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
The semiconductor device has a semiconductor substrate 10. The semiconductor substrate 10 is defined as a semiconductor chip as shown in
The semiconductor substrate 10 is provided with a first resin layer 18 as a stress relaxation layer on a surface of the passivation film 16 provided with the electrodes 14, in a manner to have at least one part of the electrodes 14 uncovered with the first resin layer 18. For example, the first resin layer 18 may be formed by employing a photolithography with use of photosensitive resins. The first resin layer 18 may be formed with use of thermosetting resins. In the first resin layer 18, a side surface 19 may be inclined in a manner to set the acute angle between a bottom surface and the side surface 19. The side surface 19 is inclined by heat contraction of a thermosetting resin precursor. A cutter or scriber can be prevented from clogging by forming the first resin layer 18 in a manner to avoid cut lines of the semiconductor substrate 10 to be described later. A top surface of the first resin layer 18 is subjected to a surface roughening by means of a dry etching or the like.
Wirings 20 are formed on the top surface of the first resin layer 18. The wirings 20 are electrically coupled to the electrodes 14. Specifically, the wirings 20 are formed in a manner to extend from tops of the electrodes 14 up to the top surface of the first resin layer 18. The roughened top surface of the first resin layer 18, which has been subjected to the surface roughening, enhances intimate contact with the wirings 20 and shapes a contact surface between the wirings 20 and the first resin layer 18 in a manner to correspond to the roughened surface, thereby enabling the contact surface to have a larger area compared with that of a flat surface. The wirings 20 may be formed in contact with the passivation film 16 between the electrodes 14 and the first resin layer 18.
A metallic layer 22 is formed on the top surface of the first resin layer 18. In the metallic layer 22, a surface in parallel to the first resin layer 18 is formed in a polygonal shape such as a square. The metallic layer 22 is not formed on the side surface 19 of the first resin layer 18. The metallic layer 22 may be made from the same material as that of the wirings 20 and may be formed together with the wirings 20. The metallic layer 22 is electrically coupled to neither the wirings 20 nor the integrated circuit 12.
A second resin layer 24 such as a solder mask layer is formed on the first resin layer 18. The second resin layer 24 is mounted on the wirings 20 and the metallic layer 22. The second resin layer 24 is provided with first through holes 26 overlapped with the lands 21 as one part of the wirings 20 and second through holes 28 to expose one part of the metallic layer 22. The second through holes 28 are formed in the second resin layer 24 to expose end parts of the metallic layer 22 and parts of the first layer 18 exposing from the metallic layer 22, which are adjacent to the end parts of the metallic layer 22. The second through holes 28 are formed in the second resin layer 24 to expose corners of the metallic layer 22. In the semiconductor device as a finished product, the second through holes 28 are not filled up to thereby expose parts of the metallic layer 22.
The second resin layer 24 further has a plurality of third through holes 30 overlapped with the metallic layer 22. The third through holes 30 are placed so as not to expose the first resin layer 18. In other words, the metallic layer 22 is placed over an inner area surrounded by the third through holes 30.
Inside the first through holes 26, external terminals 32 are formed on the wirings 20, respectively. The external terminals 32 are set to a signal terminal or a power supply terminal to be electrically coupled to the integrated circuit 12. The external terminals 32 may be formed by means of soldering. For example, cream solder, which is first placed on the lands 21 of the wirings 20, may be melted and ball-shaped by surface tension. In the case of the semiconductor substrate 10 set to the semiconductor wafer, the semiconductor device can be obtained by cutting the semiconductor wafer by means of dicing or scribing.
Inside the plurality of third through holes 30, a plurality of metallic terminals 34 are formed on the metallic layer 22, respectively. The plurality of metallic terminals 34 are formed by forming least one metallic terminal 34 in each of the plurality of third through holes 30. The metallic terminals 34 may be considered as a dummy terminal because they, as a signal terminal or a power terminal, are not electrically coupled to the integrated circuit 12. The metallic terminals 34 may be made from the same material even in the same shape as those of the external terminals 32. The plurality of metallic terminals 34 and/or the plurality of the external terminals 32 are positioned at a plurality of intersection points of a plurality of first parallel straight lines L1 with a plurality of second parallel straight lines L2, which are perpendicular to the first straight lines L1. The plurality of metallic terminals 34 and/or the plurality of the external terminals 32 are arranged in a manner to set uniform intervals between those adjacent terminals in arrays along either of the first and second straight lines L1, L2.
According to this embodiment, not only the external terminals 32 transfer heat through the wirings 20 but also the metallic layer 22 receives heat and the metallic terminals 34 transfer heat, thereby achieving heat release. Furthermore, the metallic layer 22 directly releases heat through the second through holes 28, and thus reduces the adverse effect on the motherboard by heat when the semiconductor device is mounted on the motherboard.
This invention is not limited to the embodiments described above but may be variously modified. For example, this invention includes substantially the same structure including the structure with the same functions, methods, and results or the structure with the same goals and results as that of the embodiments described above. This invention also includes other structures in which non-essential elements of the above embodiments are substituted. This invention also includes the structures that can achieve the same effects or the same goals as those achieved by the above embodiments. Moreover, this invention includes other structures in which known methods and techniques are incorporated into the above embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-010572 | Jan 2007 | JP | national |
