Patent Application
20090039487
1. Field of the Invention
The present invention relates to a semiconductor device capable of reducing a noise factor without changing an external shape.
2. Background Art
A semiconductor device is used in which a semiconductor chip with a high-frequency element such as a GaAs FET formed thereon is mounted on a source frame and sealed with resin (e.g., see Japanese Patent Laid-Open No. 61-16554).
Furthermore, a source terminal 9 of the semiconductor chip 3 and the die pad 2 are electrically connected by a plurality of wires 8, a drain terminal 10 of the semiconductor chip 3 and the bonding pad 7 are electrically connected, and a gate terminal 11 of the semiconductor chip 3 and the bonding pad 6 are electrically connected. The die pad 2, the bonding pads 6 and 7, the semiconductor chip 3 and the plurality of wires 8 are sealed with mold resin 12.
In the conventional semiconductor device, the die pad 2 is cut into a rectangular shape and the bonding pad 6 is cut along the shape of the die pad 2. In this way, the space between the source frame 1 and the gate frame 4 is narrow and the area that both frames face each other is large. As a result, a capacitance between the source frame 1 and gate frame 4 is increased. Moreover, as is seen from following Formulas (1) and (2), there is a problem that as a capacitance Cgs between the source frame 1 and gate frame 4 increases, a noise factor NF increases.
Here, NF is a noise factor, ω is an angular frequency, fT is a current gain cutoff frequency, A is a constant and Cgs is a source-gate capacitance.
A noise factor of a semiconductor device may be reduced by changing the external shape of the semiconductor device, increasing the space between the source frame 1 and the gate frame 4 and reducing the area that both frames face each other. However, it is difficult to change the external shape since the size of the semiconductor device is standardized and from the standpoint of manufacturing cost.
Furthermore, as is understandable from Formula (3) below, a capacitance Cdg between the gate frame 4 and the drain frame 5 may be decreased to increase the gain (maximum effective gain) of the semiconductor device.
Here, MAG is a maximum effective gain, k is a stability factor, B is a constant and Cdg is the capacitance between the drain and the gate.
Electrical coupling between the gate and the drain needs to be weakened to decrease Cdg. This requires the capacitance Cgs between the gate and the source and the capacitance Cds between the drain and the source to be increased. When Cgs is increased, the noise factor is increased according to Formula (I). Therefore, if Cds is increased, the gain can be increased without increasing the noise factor.
Cds may be increased by changing the external shape of the semiconductor device and increasing the area that the source frame 1 and the drain frame 5 face each other. However, it is difficult to change the external shape because the size of the semiconductor device is standardized and from the standpoint of manufacturing cost.
The present invention has been implemented to solve the above described problem and it is a first object of the present invention to obtain a semiconductor device capable of decreasing a noise factor without changing the external shape.
It is a second object of the present invention to obtain a semiconductor device capable of increasing a gain without changing the external shape.
According to one aspect of the present invention, a semiconductor device comprises a source frame having a die pad; a linear gate frame having a bonding pad; a semiconductor chip mounted on the die pad; a plurality of wires which electrically connect a source terminal of the semiconductor chip and the die pad and electrically connect a gate terminal of the semiconductor chip and the bonding pad; and resin which seals the die pad, the bonding pad, the semiconductor chip and the plurality of wires, wherein the die pad is provided at a certain distance from the bonding pad and cut in a direction diagonally to an extending direction of the gate frame in the vicinity of the bonding pad.
The invention can decrease the noise factor of the semiconductor device without changing the external shape.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
Furthermore, a source terminal 9 of the semiconductor chip 3 and the die pad 2 are electrically connected by a plurality of wires 8, a drain terminal 10 of the semiconductor chip 3 and the bonding pad 7 are electrically connected, a gate terminal 11 of the semiconductor chip 3 and the bonding pad 6 are electrically connected. The die pad 2, the bonding pads 6 and 7, the semiconductor chip 3 and the plurality of wires 8 are sealed with mold resin 12 (resin).
According to this embodiment, the die pad 2 is cut in a direction diagonal to the extending direction of the gate frame 4 in the vicinity of the bonding pad 6. That is, the die pad 2 is cut in a direction in which it goes away from the gate frame 4 in the vicinity of the bonding pad 6. On the other hand, the bonding pad 6 is cut in parallel with a diagonally cut portion of the die pad 2 in the vicinity of the die pad 2.
The above described configuration makes it possible to increase the distance between the source frame 1 and the gate frame 4 and reduce the area that both frames face each other. Therefore, it is possible to reduce a capacitance between the source frame 1 and the gate frame 4 and thereby reduce the noise factor of the semiconductor device without changing the external shape.
The above described configuration can increase the area that a source frame 1 and the drain frame 5 face each other. Therefore, since the capacitance between the source frame 1 and the drain frame 5 can be increased, a gain can be increased without changing the external shape. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and the drain frame 5 face each other more than Embodiment 2. This can further increase a gain. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and a drain frame 5 face each other. Therefore, since a capacitance between the source frame 1 and the drain frame 5 can be increased, a gain can be increased without changing the external shape. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and a drain frame 5 face each other. Therefore, since a capacitance between the source frame 1 and the drain frame 5 can be increased a gain can be increased without changing the external shape. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and a drain frame 5 face each other. Therefore, since a capacitance between the source frame 1 and the drain frame 5 can be increased, a gain can be increased without changing the external shape. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and a drain frame 5 face each other. Therefore, since a capacitance between the source frame 1 and the drain frame 5 can be increased, a gain can be increased without changing the external shape. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and the drain frame 5 face each other. Therefore, since a capacitance between the source frame 1 and the drain frame 5 can be increased, a gain can be increased without changing the external shape. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and a drain frame 5 face each other. Therefore, since a capacitance between the source frame 1 and the drain frame 5 can be increased, a gain can be increased without changing the external shape. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and a drain frame 5 face each other. Therefore, since a capacitance between the source frame 1 and the drain frame 5 can be increased, a gain can be increased without changing the external shape. Other effects are the same as those of Embodiment 1.
The above described configuration can increase the area that a source frame 1 and the gate frame 4 face each other. Therefore, since the capacitance between the source frame 1 and the gate frame 4 can be increased, a gain can be increased without changing the external shape.
The above described configuration can increase the area that a source frame 1 and the gate frame 4 face each other more than Embodiment 2. This can further increase a gain.
The above described configuration can increase the area that a source frame 1 and a gate frame 4 face each other. Therefore, since a capacitance between the source frame 1 and the gate frame 4 can be increased, a gain can be increased without changing the external shape.
The above described configuration can increase the area that a source frame 1 and a gate frame 4 face each other. Therefore, since a capacitance between the source frame 1 and the gate frame 4 can be increased, a gain can be increased without changing the external shape.
The above described configuration can increase the area that a source frame 1 and a gate frame 4 face each other. Therefore, since a capacitance between the source frame 1 and the gate frame 4 can be increased, a gain can be increased without changing the external shape.
The above described configuration can increase the area that a source frame 1 and a gate frame 4 face each other. Therefore, since a capacitance between the source frame 1 and the gate frame 4 can be increased, a gain can be increased without changing the external shape.
The above described configuration can increase the area that a source frame 1 and the gate frame 4 face each other. Therefore, since a capacitance between the source frame 1 and the gate frame 4 can be increased, a gain can be increased without changing the external shape.
The above described configuration can increase the area that a source frame 1 and a gate frame 4 face each other. Therefore, since a capacitance between the source frame 1 and the gate frame 4 can be increased, a gain can be increased without changing the external shape.
The above described configuration can increase the area that a source frame 1 and a gate frame 4 face each other. Therefore, since a capacitance between the source frame 1 and the gate frame 4 can be increased, a gain can be increased without changing the external shape.
Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.
The entire disclosure of a Japanese Patent Application No. 2007-209043 filed on Aug. 10, 2007, a Japanese Patent Application No. 2007-328904 filed on Dec. 20, 2007 and a Japanese Patent Application No. 2008-105528 filed on Apr. 15, 2008 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-209043 | Aug 2007 | JP | national |
| 2007-328904 | Dec 2007 | JP | national |
| 2008-105528 | Apr 2008 | JP | national |
