Patent Application
20080079138
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These preferred embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other preferred embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and scope of the present inventions is defined only by the appended claims.
Preferred embodiments according to the present invention are illustrated in more details with reference to the attached drawings hereinafter.
In a semiconductor device according to the present preferred embodiment, a structure as shown in
Inner layer patterns 110 made of Cu are formed on the upper and lower sides of the core substrate 102. Plural inner via holes 112 in the area where a cutout (114) is prepared and dice-bonded are all connected by the inner layer patterns 110, and have a structure where they are made into a same potential. On the surfaces of the prepregs 104, 106, outer layer conductive patterns 108 made of Cu are formed.
Next, as shown in
Herein, since the thickness of the core substrate 102 is larger than the thickness of the prepregs 104, 106, it becomes easy to suspend the cutting in the middle of the core substrate 102, and the processing control of the router becomes easier. Moreover, the plural inner via holes 112 are formed in the dice bond area, and thereby it is possible to make the underside surface of the chip semiconductor chip 120 and the inner layer conductive patterns at a same potential further more reliably.
Next, as shown in
As mentioned above, in the present preferred embodiment, since the cutout processing is stopped in the middle of the inner via holes 112, there is no need to perform the position control of cutting precisely in comparison with the prior art. That is, the margin in the depth direction at the moment of cutting the cutout portion can be secured. As a result, a relatively low-cost (not so highly precise) machine can be used, and it becomes possible to aim at the reduction of the manufacture cost.
Moreover, there is also an advantage that the freedom degree of bottom wiring of the semiconductor chip 120 is improved, by choosing the position of the via holes 112 to be arranged on the bottom of the semiconductor chip 120.
Inner layer patterns 210 made of Cu are formed on the upper and lower sides of the prepreg 202. Plural conductive bumps (extending conductive portions) 212 made of silver paste are formed in the area where a cutout (214) is prepared and dice-bonded, and these conductive bumps 212 are all connected by the inner layer patterns 210, and have a structure where they are made into a same potential. On the surfaces of the core substrates 204, 206, outer layer conductive patterns 208 made of Cu are formed. It is preferable that the height of the conductive bumps 212 is formed as high as possible within the range of the thickness of the prepreg 202.
In the prepregs 204, 206, blind via holes 230 are formed, and the insides thereof are filled up with resin 232.
Next, by use of a router for cutout processing (inner layer cutting), as shown in
Herein, since the thickness of the prepreg 202 is larger than the thickness of the core substrates 204,206, it becomes easy to suspend the cutting in the middle of the prepreg 202, and the processing control of the router becomes further easier. Moreover, the plural conductive bumps 212 are formed in the dice bond area, and thereby it is possible to make the underside surface of the chip semiconductor chip (220) and the inner layer conductive patterns at a same potential further more reliably.
Next, as shown in
As mentioned above, in the present preferred embodiment, since the cutout processing is stopped in the middle of the conductive bumps 212, there is no need to perform the position control of cutting precisely in comparison with the prior art. That is, the margin in the depth direction at the moment of cutting the cutout portion can be secured. As a result, a relatively low-cost (not so highly precise) machine can be used, and it becomes possible to aim at the reduction of the manufacture cost.
Moreover, there is also an advantage that the freedom degree of bottom wiring of the semiconductor chip 220 is improved, by choosing the position of the conductive bumps 212 to be arranged on the bottom of the semiconductor chip 220.
Furthermore, since the blind via holes 230 can be formed between the first layer and the second layer, and between the third layer and the fourth layer, in comparison with the first preferred embodiment mentioned above, it becomes possible to improve the substrate wiring density.
Heretofore, the present invention has been explained with reference to the preferred embodiments thereof, and as is apparent to those skilled in the art, the present invention is not limited to the above preferred embodiments, but the present invention may be embodied by appropriately modifying the structural components thereof without departing from the spirit or essential characteristics thereof.
In the above preferred embodiments, explanations have been made with the multilayer substrate of four layers as an example, however, the present invention may be applied also to substrates of other numbers of layers. Moreover, although the conductive bumps 212 are used in the second preferred embodiment, it is also possible to use a conductive substance on a line. It is important that it is a conductive substance that extends upward in the thickness direction from the inner layer pattern.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-266866 | Sep 2006 | JP | national |
