BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view showing an example of the semiconductor device concerning the present invention;
FIG. 2 is a plan view showing the semiconductor device concerning the first comparative example that did the stack without deflecting a semiconductor chip to a module substrate;
FIG. 3 is a plan view showing the semiconductor device concerning the second comparative example that connected individually to the bonding lead of a module substrate the electrode pad in which direct connection on a function is possible between the semiconductor devices by which the stack was done, and connected these corresponding bonding lead mutually using the wiring in the module substrate;
FIG. 4 is a flow chart which shows the manufacturing process of the semiconductor device of the present invention;
FIG. 5 is a schematic plan view of the module substrate of the present invention;
FIG. 6 is a schematic cross-sectional view which goes along the A-A′ line of FIG. 5;
FIG. 7 is the schematic plan view which mounted the first semiconductor chip on the module substrate;
FIG. 8 is a schematic cross-sectional view which goes along the A-A′ line of FIG. 7;
FIG. 9 is the schematic plan view which mounted the second semiconductor chip on the first semiconductor chip;
FIG. 10 is a schematic cross-sectional view which goes along the A-A′ line of FIG. 9;
FIG. 11 is a schematic plan view which did wire bonding of each of the first and a second semiconductor chip, and the module substrate;
FIG. 12 is a schematic cross-sectional view which goes along the A-A′ line of FIG. 11;
FIG. 13 is a schematic cross-sectional view which goes along the A-A′ line of FIG. 11 in which the sealing body was formed on the module substrate; and
FIG. 14 is a schematic cross-sectional view where many ball electrodes have been arranged at the back surface of a module substrate and which goes along the A-A′ line of FIG. 11.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
An example of the semiconductor device concerning the present invention is shown in FIG. 1 in plan view. Semiconductor device 4 shown in the same drawing has the SIP structure formed by doing the stack of first semiconductor chip 1 and the second semiconductor chip 2 to module substrate (wiring substrate) 3.
Second semiconductor chip 2 is a driver which outputs driver voltage to a CCD camera, and first semiconductor chip 1 is a timing controller which generates the timing control signal which controls operation of a CCD camera. A driver inputs a part of timing control signal which a timing controller generates, and supplies a driving signal to a CCD camera.
Second semiconductor chip 2 of the rectangle by which the stack was done on the first semiconductor chip of a rectangle has a plurality of electrode pads (third electrode pad) 201 arranged along side (fifth side) 200, has a plurality of electrode pads 203 arranged along side 202, and has a plurality of electrode pads (fourth electrode pad) 205 arranged along side (sixth side) 204. Electrode pad 205 interfaces with first semiconductor chip 1, and the function, for example, which inputs a timing control signal or outputs a reply signal is assigned. Although illustration in particular is not done, second semiconductor chip 2 is provided with a voltage generating circuit, an output circuit, etc. as an internal circuit (second circuit) for realizing the function. The electrode pads 201, 203, and 205 are combined with the predetermined node of the internal circuit formed in the inside of semiconductor chip 2 via the wiring layer.
Rectangular first semiconductor chip 1 has a plurality of electrode pads (first electrode pad) 101 arranged along side (third side) 100, has a plurality of electrode pads 103 arranged along side 102, has a plurality of electrode pads (second electrode pad) 105,106 arranged along side (fourth side) 104, and has a plurality of electrode pads 108 along side 107. Electrode pad 105 is combined with corresponding electrode pad 205 of second semiconductor chip 2 by bonding wire (fourth wire) 500. Although illustration in particular is not done, first semiconductor chip 1 is provided with the sequencer for timing control or a program control circuit, a peripheral circuit, etc. as an internal circuit (first circuit) for realizing the function. The electrode pads 101, 103, 105, 106, and 108 are combined with the predetermined node of the internal circuit formed in the inside of semiconductor chip 2 via the wiring layer. Although not restricted in particular, the first semiconductor chip has an input/output interface circuit (for example, analog-digital-conversion circuit) of an analog signal. The electrode pad connected to the analog I/O interface circuitry concerned is collected by electrode pad 108 which went along side 107 in order to avoid mixture with a digital signal as much as possible.
Module substrate 3 is formed by the rectangular wiring substrate made of glass epoxy resin which has a wiring layer, for example. In a back surface, many ball electrodes are arranged in the shape of an array. Two rows of a plurality of bonding leads (second bonding lead) 302 and a plurality of bonding leads (first bonding lead) 303 are formed in a front surface from an outside along side (first side) 301. One row of a plurality of bonding leads 305 which went along side 304, one row of a plurality of bonding leads (third bonding lead) 307 which went along side (second side) 306, and one row of a plurality of bonding leads 309 that went along side 308 are formed. The bonding lead 302 is combined with electrode pad 201 of second semiconductor chip 2 by bonding wire (second wire) 501. The bonding lead 303 is combined with electrode pad 101 of first semiconductor chip 1 by bonding wire (first wire) 502. The bonding lead 305 is combined with corresponding electrode pad 203 of second semiconductor chip 2 by bonding wire 505, and is combined with corresponding electrode pad 103 of first semiconductor chip 1 by bonding wire 506. The bonding lead 307 is combined with electrode pad 106 of first semiconductor chip 1 by bonding wire (third wire) 507. The bonding lead 309 is combined with electrode pad 108 of first semiconductor chip 1 by bonding wire 508. Although illustration in particular is not done, each bonding lead 302,305,307,309 is connected to the corresponding ball electrode via the through hole or the wiring. The first semiconductor chip 1, second semiconductor chip 2, and bonding wires 500, 501, 502, 505, 506, 507, and 508 are sealed and protected by resin on the front surface of module substrate 3.
CL 1 is a central line of module substrate 3, and CL 2 is a central line of semiconductor chips 1 and 2. As clearly from a drawing, semiconductor chips 1 and 2 adjust the central line, and the stack is done. The stack of the semiconductor chips 1 and 2 by which the stack was done is deflected (gets eccentric) to left-hand side to central line CL 1 of module substrate 4. The amount of deflections is EQ. Since it is required for an adjacent wire not to contact in wire bonding, a prescribed minimum pitch must be secured between adjoining bonding leads. Therefore, by making left-hand side deflect semiconductor chips 1 and 2 by which the stack was done to central line CL 1 of module substrate 4, and doing a stack, a space margin is born to the region which must arrange bonding leads 302, 303 by two rows on module substrate 3 to which the arranging space was restricted. A useless open area cannot be generated in the region which should just arrange one row of bonding leads 307 in the opposite side, but it can contribute to realization of a miniaturization of module substrate 3 as a result. Like the first comparative example shown in FIG. 2, when the stack of central line CL 1 of module substrate 3 and central line CL 2 of semiconductor chips 1 and 2 is adjusted and done, as for regions AR1 and AR2 of right and left of semiconductor chip 1 on module substrate 3, area will become the same. It becomes impossible substantially to form a module substrate by arranging the bonding lead of two rows to region AR1, and the module substrate must be formed by width W4 (W1<W4) at least. It is difficult to adopt the module substrate of optional size by the relation with cost or standardization in practice. When there is no W4 in the standardized module substrate size, the module substrate size of bigger size W5 than it must be adopted, and there is a possibility of generating the big futility also in area and also in cost. When making the width size of the first semiconductor chip 1 into W2=3.68 mm and making the width size of second semiconductor chip 2 into W3=2.4 mm, concerning the size of semiconductor device 4 of FIG. 1, by making the amount of deflections into EQ=0.32 mm, module substrate 3 of width size W1=6 mm was employable. On the other hand, in the case of the comparative example of FIG. 2, it is necessary to adopt the module substrate of for example, width size W5=8 mm.
In the example of FIG. 1, as for electrode pad 105 of first semiconductor chip 1 and electrode pad 205 of second semiconductor chip 2, one side is an output terminal and the other side is an input terminal mutually, and they are terminals in which direct connection on a function is possible. In FIG. 1, it is set as the arrangement which can be directly connected with wire 500 by collecting those electrode pads 105, 205 of each semiconductor chip 1 and 2 so that they may come to the side (in the present invention for example, the second side side of a module substrate) of the same side as mutual. In not paying the consideration which links electrode pad 105 of first semiconductor chip 1, and electrode pad 205 of second semiconductor chip 2 directly, as shown in the second comparative example of FIG. 3, electrode pad 105 of first semiconductor chip 1 and electrode pad 205 of second semiconductor chip 2 must be individually combined with corresponding bonding leads 311, 310 with a wire, respectively. The wiring in a module which connects bonding leads 310 and 311 by corresponding things must be formed in a module substrate. In the case of FIG. 3, the wiring in module substrate 3A must not only become complicated, but it must arrange two rows of bonding leads to each of right and left of module substrate 3A. Therefore, the module substrate of big size like W5 must be adopted like the comparative example of FIG. 2. As clearly from the comparative example of FIG. 2 and FIG. 3, it stops in the structure of FIG. 2 only by paying consideration of linking directly electrode pads 105, 205 in which direct connection on a function is possible with wire 500 between different semiconductor chips 1 and 2, and it is occasionally difficult to adopt a module substrate with small size. It becomes possible to adopt a module substrate with small size for the first time by taking a means to deflect mutually a module substrate, and semiconductor chips 1 and 2 by which the stack was done, to make right and left deflect a centre position, and to accumulate them, as further step.
Next, the manufacturing method of semiconductor device 4 of the present invention is explained along the flow chart shown in FIG. 4.
First, at Step S1 of FIG. 4, module substrate 3 shown in FIG. 5 and FIG. 6 is prepared. As for module substrate 3, a plurality of bonding leads 302, 303, 305, 307, 309 are formed along a plurality of sides 301, 304, 306, 308 on the front surface (main surface), respectively.
Next, at Step S2 of FIG. 4, as shown in FIG. 7 and FIG. 8, first semiconductor chip 1 is mounted via a binder (not shown) on the front surface of module substrate 3. The integrated internal circuit (first circuit) is formed in the main surface of first semiconductor chip 1. A plurality of electrode pads 101, 103, 105, 106, and 108 electrically connected with the internal circuit via the wiring layer are formed, respectively along a plurality of sides 100, 102, 104, and 107 of first semiconductor chip 1. First semiconductor chip 1 is mounted in the position where the central line CL 2 shifted from central line CL 1 of the module substrate. Namely, first semiconductor chip 1 is mounted deflecting central line CL 2 of first semiconductor chip 1 to the second side side of module substrate 3 so that the gap of first side 301 of module substrate 3, and third side 100 of first semiconductor chip 1 may become larger than the gap of second side 306 of module substrate 3, and fourth side 104 of first semiconductor chip 1.
Next, at Step S3 of FIG. 4, as shown in FIG. 9 and FIG. 10, second semiconductor chip 2 is mounted via a binder (not shown) on first semiconductor chip 1. The integrated internal circuit (second circuit) is formed in the main surface of second semiconductor chip 2. A plurality of electrode pads 201, 203, and 205 electrically connected with the internal circuit via the wiring layer are formed, respectively along a plurality of sides 200, 202, and 204 of second semiconductor chip 2. Second semiconductor chip 2 is mounted on first semiconductor chip 1 at the position where the central line CL 2 is shifted from central line CL1 of the module substrate, in other words, so that it may overlap with central line CL 2 of first semiconductor chip 1. Thus, when laminating semiconductor chip 2 after the second stage, assembling property can be made easy in making the central line of each semiconductor chip 1 and 2 as a mark of alignment and laminating so that the central line of the semiconductor chip at the side of the upper row may overlap with the central line of the semiconductor chip at the side of a lower row.
Then, as shown in Step S4 of FIG. 4, the above-mentioned adhesives are hardened by doing baking processing of the module substrate 3 which mounted the first and second semiconductor chips 1 and 2 in heat atmosphere.
Next, in Step S5 and Step S6 of FIG. 4, as shown in FIG. 11 and FIG. 12, a plurality of electrode pads 101, 103, 105, 106, and 108 of first semiconductor chip 1 and a plurality of bonding leads 303, 305, 307, and 309 of module substrate 3 are electrically connected via a plurality of bonding wires 502, 506, 507, and 508 which consist of a conductive member, respectively. Then, a plurality of electrode pads 201 and 203 of second semiconductor chip 2, and a plurality of bonding leads 302, 305 of module substrate 3 are electrically connected, respectively by a plurality of bonding wires 501, 505 which consist of a conductive member. A plurality of electrode pads 205 of second semiconductor chip 2, and a plurality of electrode pads 105 of first semiconductor chip 1 are electrically connected, respectively by a plurality of bonding wires 500 which consist of a conductive member. When wire bonding of semiconductor chip 1 at the side of a lower row and module substrate 3 is performed after performing wire bonding of semiconductor chip 2 at the side of the upper row, and module substrate 3, the wire formed previously and the tip of the capillary which is a wire-bonding tool contact, and there is a possibility of causing a disconnection failure. Then, like the present invention, contact of a wire and a capillary can be suppressed by performing wire bonding of semiconductor chip 2 at the side of the upper row, and module substrate 3 after performing wire bonding of semiconductor chip 1 at the side of a lower row, and module substrate 3. This is because the loop shape of the wire formed later is located up rather than the loop shape of the wire formed previously.
Next, in Step S7 of FIG. 4, as shown in FIG. 13, the front surface side of module substrate 3, first semiconductor chip 1, second semiconductor chip 2, and a plurality of bonding wires 500, 501, 502, 505, 506, 507, and 508 are sealed by resin 600, and a sealing body is formed.
Then, at Step S8 of FIG. 4, as shown in FIG. 14, many ball electrodes 601 are formed in the back surface side of module substrate 3. Although not illustrated, many ball electrodes 601 are electrically connected with a plurality of bonding leads 302, 303, 305, 307, and 309 currently formed on the front surface via the wiring layer formed in the internal layer of module substrate 3, respectively.
In the foregoing, the present invention accomplished by the present inventors is concretely explained based on above embodiments, but the present invention is not limited by the above embodiments, but variations and modifications may be made, of course, in various ways in the Limit that does not deviate from the gist of the invention.
For example, the first and a second semiconductor chip are not limited to the timing controller and driver of a CCD camera. They may be the combination of others, such as the driver and display controller of a liquid crystal display, a memory and a memory controller, a microcomputer, a work memory. In the internal circuit of a semiconductor chip, the circuit configuration should just be determined according to the function of the semiconductor chip concerned.
It is not limited to a resin seal being done, for example by an individual mold method, but after mounting a plurality of semiconductor chips on the module substrate which has a plurality of product formation areas, respectively, a plurality of product formation areas may be put in block with a batch molding method (MAP), and a resin seal may be done. In that case, in an individual separation step, a plurality of product formation areas are cut and separated by the dicing blade, and the end portion of the sealing body of the semiconductor device acquired is formed in the same position as the end portion of a module substrate.
Patent Application
20070262431
