This application is a national phase application of PCT Application No. PCT/CN2012/085259, filed on Nov. 26, 2012, entitled “Semiconductor Device and Method for Manufacturing the Same,” which claims priority to Chinese Patent Application No. 201210447361.1, filed on Nov. 9, 2012, entitled “Semiconductor Device and Method for Manufacturing the Same,” which is incorporated herein by reference in its entirety.
The present disclosure relates to the semiconductor technology, and particularly to semiconductor devices and methods for manufacturing the same.
Short channel effects are getting more significant as planar semiconductor devices are increasingly being scaled down. To this end, three-dimensional (3D) semiconductor devices, such as Fin Field Effect Transistors (FinFETs), have been proposed. Generally, a FinFET includes a fin formed vertically on a substrate and a gate stack intersecting the fin. In addition, an isolation layer is formed on the substrate to isolate the gate stack from the substrate. As such, the fin has its bottom surrounded by the isolation layer. Therefore, it is difficult for the gate to effectively control the bottom of the fin. As a result, a leakage current tends to occur between a source and a drain via the bottom of the fin.
The present disclosure aims to provide, among others, semiconductor devices and methods for manufacturing the same.
According to an aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack.
According to another aspect of the present disclosure, there is provided a semiconductor device, comprising: a fin formed on a substrate; an isolation layer formed on the substrate; and a gate stack formed on the isolation layer and crossing over the fins, wherein the fin comprises a portion composed of a first semiconductor layer beneath the gate stack and a portion composed of a second semiconductor layer abutting the first semiconductor layer, wherein the semiconductor device further comprises source/drain regions formed in the portion composed of the second semiconductor layer, and wherein a dielectric layer is interposed between the portion composed of the first semiconductor layer and the substrate.
The above and other objects, features, and advantages of the present disclosure will become apparent from following descriptions of embodiments with reference to the attached drawings, in which:
Hereinafter, the technology disclosed herein is described with reference to embodiments thereof shown in the attached drawings. However, it should be noted that those descriptions are just provided for illustrative purpose, rather than limiting the present disclosure. Further, in the following, descriptions of known structures and techniques are omitted so as not to obscure the concept of the present disclosure.
In the drawings, various structures according to the embodiments are schematically shown. However, they are not drawn to scale, and some features may be enlarged while some features may be omitted for sake of clarity. Moreover, shapes and relative sizes and positions of regions and layers shown in the drawings are also illustrative, and deviations may occur due to manufacture tolerances or technique limitations in practice. Those skilled in the art can also devise regions/layers of other different shapes, sizes, and relative positions as desired.
In the context of the present disclosure, when a layer/element is recited as being “on” a further layer/element, the layer/element can be disposed directly on the further layer/element, or otherwise there may be an intervening layer/element interposed therebetween. Further, if a layer/element is “on” a further layer/element in an orientation, then the layer/element can be “under” the further layer/element when the orientation is turned.
According to an embodiment of the present disclosure, an isolation island may be formed between a source and a drain at the bottom of a fin, to reduce a leakage current between the source and the drain via the bottom of the fin. To form such an isolation island, a sacrificial layer and a fin body layer may be formed by, for example, epitaxy, on a substrate, and then patterned to have a shape corresponding to that of the fin to be formed. Then, the sacrificial layer may be removed by selective etching, and a dielectric material is filled beneath the fin body layer and patterned into an isolation island.
As the isolation island is desired to be between the source and the drain, a gate stack may be used as a mask in patterning the isolation island. Specifically, after the sacrificial layer and the fin body layer are patterned into a fin, an isolation layer may be formed on the substrate and a (sacrificial) gate stack crossing over the fin may formed on the isolation layer. Here, the isolation layer is formed to expose a portion of the sacrificial layer. This is because the isolation layer defines the “bottom” of the fin. In such a case, an isolation subsequently formed at the position of the sacrificial layer will be at the bottom of the fin. Then, the fin body layer may be selectively etched with the (sacrificial) gate stack as a mask (thereby leaving the fin body layer beneath the gate stack), to expose the sacrificial layer. Next, the sacrificial layer may be selectively etched and thus removed (for example, the sacrificial layer may be removed completely). As such, a void is formed beneath the fin body layer. Next, a dielectric material may be deposited and etched back (with the gate stack as a mask), so that the void beneath the fin body layer is filled with the dielectric material to form an isolation island.
On the other hand, after the sacrificial layer is removed as described above, an opening having a shape corresponding to that of the fin is formed in the isolation layer and exposes a portion of the substrate. Then, source/drain regions may be formed by, for example, epitaxy, on the substrate via the opening.
According to another embodiment of the present disclosure, to further reduce the source/drain leakage, a relatively high threshold voltage region may be further formed beneath the isolation island. For example, the high threshold voltage region may comprise a relatively highly-doped region, or a punch-through stopper. This region may be formed by implantation into the substrate before forming the isolation island. Due to the existence of the isolation layer and the (sacrificial) gate stack, the implantation is substantially limited to regions of the portion of the substrate, which is exposed by said opening, on opposite sides of the (sacrificial) gate stack (beneath the source/drain regions to be formed subsequently), and may extend into a portion of the substrate beneath the isolation island due to diffusion.
According to another embodiment of the present disclosure, the formed source/drain regions may comprise a semiconductor material different from that of the fin body layer, and thus can apply stress to the fin body layer (in which a channel region is formed) due to mismatch of lattices between the source/drain regions and the fin body layer, thereby further improving the device performance.
According to an embodiment of the present disclosure, the isolation layer may be formed by depositing a dielectric material on the substrate and then etching it back. The dielectric material may be formed in such way that when the dielectric material substantially covers the fin (i.e., in case of multiple fins, substantially fills up gaps between the fins), a portion of the dielectric material on top of the fin may have a thickness sufficiently less than that of a portion of the dielectric material on the substrate. For example, the portion of the dielectric material on top of the fin may have a thickness less than ⅓, preferably ¼, of the thickness of the portion of the dielectric material on the substrate. This may be implemented by, for example, High Density Plasma (HDP) deposition. In case of forming a plurality of fins, a portion of the dielectric material on top of each of the fins may have a thickness less than half of a spacing between the fin and its neighboring fin. As such, an etching depth may be reduced in the subsequent back-etching, and thus accuracy for controlling the etching may be improved.
The present disclosure may be presented in various forms, and some examples thereof will be described hereafter.
As shown in
An n-type well 1000-1 and a p-type well 1000-2 may be formed in the substrate 1000, so that a p-type device and an n-type device may be formed later therein, respectively. For example, the n-type well 1000-1 may be formed by implanting n-type impurities (such as P or As) into the substrate 1000, and the p-type well 1000-2 may be formed by implanting p-type impurities (such as B) into the substrate 1000. If required, annealing may be performed after the implantation. To those skilled in the art, the n-type and p-type wells may be formed in various methods, and detailed descriptions thereof will be omitted here.
It is to be noted that a process of forming complementary devices in the respective n-type and p-type wells will be described below, but the present disclosure is not limited thereto. The present disclosure is also applicable to a non-complementary process, for example. Further, some of the following processes related to the complementary devices may be not necessary in some implementations.
A first semiconductor layer 1002 may be formed on the substrate 1000 by, for example, epitaxy. In an example, the first semiconductor layer 1002 may comprise SiGe (wherein Ge may have an atomic percentage of about 5-20%), with a thickness about 10-50 nm. Next, a second semiconductor layer 1004 may be formed by, for example, epitaxy on the first semiconductor layer 1002. In an example, the second semiconductor layer 1004 may comprise Si with a thickness of about 20-100 nm.
In an example of the present disclosure, a protection layer 1006 may be formed on the second semiconductor layer 1004. For example, the protection layer 1006 may comprise oxide (for example, silicon oxide) with a thickness about 10-50 nm. Such a protection layer 1006 can protect end portions of fins in subsequent processes.
The formed second semiconductor layer 1004, first semiconductor layer 1002, and substrate may be then patterned to form the fins. For example, this can be done as follows. In particular, photoresist 1008 may be formed and then patterned as designed on the protection layer 1006. The photoresist 1008 is generally patterned into a series of parallel equispaced lines. Then, as shown in
In case of the complementary process, an isolation may be formed between the n-type and p-type regions as shown in
It can be seen that in the process of
In the example of
After the fins are formed in the above processes, gate stacks crossing over the respective fins may be formed to achieve final semiconductor devices.
To isolate the gate stacks from the substrate, an isolation layer may be formed on the substrate. This isolation layer may be formed by, for example, depositing a dielectric material on the substrate, and then etching it back. In addition, in the back-etching, an etching depth may be controlled so that the back-etched isolation layer exposes a portion of the first semiconductor layer (for example, a top surface of the isolation layer may be located between a top surface and a bottom surface of the first semiconductor layer). In an example, the isolation layer may comprise High Density Plasma (HDP) oxide, such as silicon oxide.
To improve uniformity in level of (the top surface of) of the isolation layer after being etched back, and thus improve uniformity in height of finally-formed fins, the dielectric material 1014 may be deposited in such a way that it substantially covers the fin (i.e., in case of multiple fins, substantially fills up gaps between the fins), as shown in
According to an example of the present disclosure, the dielectric material 1014 may comprise oxide (e.g., silicon oxide) formed by High Density Plasma (HDP) deposition. Due to characteristics of HDP, the thickness of the dielectric material on top of the fins (in a direction perpendicular to the substrate) and on side surfaces of the fins (in a direction parallel to the substrate, i.e., a lateral direction) is less than that of the dielectric material between the fins on the substrate (in a direction perpendicular to the substrate) during the deposition. Due to such characteristics, the HDP deposition is conventionally not used to make oxide isolation.
Here, by controlling, for example, deposition conditions, the thickness of the portion of the dielectric material 1014 on top of each of the fins may be less than ½ of a spacing between the fin and its neighboring fin when the dielectric material 1014 substantially covers the fins (i.e., substantially fills up the gaps between the fins). If the spacings between the fins are not the same, the thickness of the portion of the dielectric material 1014 on top of each of the fins may be less than ½ of a narrower one of the spacings between the fin and its neighboring fins.
Next, the dielectric material 1014 is etched back as shown in
In an example, the protection layer 1006 and the dielectric material 1014 comprise the same material, such as oxide. Therefore, in the process of etching back the dielectric material 1014, the protection layer 1016 may be removed at the same time, as shown in
Then, sacrificial gate stacks crossing over the respective fins may be formed on the isolation layer 1014. For example, this may be done as follows.
In particular, as shown in
Next, as shown in
Because the portion of the dielectric layer 1020-1 is relatively thin, a surface thereof may have substantially have the same profile as that of the underlying structure. However, for convenience, the surface profile of the portion of the dielectric layer 1020-1 is not shown in
The spacer 1020-2 includes substantially no portion formed on side walls of the fins when the trenches between the fins have a tapered shape narrowed from top down (it is generally the case due to characteristics of the etching).
Next, as shown in
Next, portions of the second semiconductor layer 1004 exposed due to the removal of the sacrificial gate dielectric layer 1016 may be selectively removed (by, for example, RIE). Due to the existence of the sacrificial gate stack (including the sacrificial gate dielectric layer, the sacrificial gate conductor, and the spacer), the second semiconductor layer 1004 may be left beneath the sacrificial gate stack. As a result, the first semiconductor layer 1002 is exposed.
Next, as shown in
To improve the device performance, after removing the first semiconductor layer, a punch-through stopper 1030 may be formed by implantation, as shown by arrows in
Then, as shown in
Then, a third semiconductor layer 1034 may be formed on the substrate by, for example, epitaxy, as shown in
As such, the second semiconductor layer 1004 together with the third semiconductor layer 1034 located on opposite sides thereof constitute a “fin” for the final device. In the fin, the channel may be formed in the second semiconductor layer 1004 beneath the gate stack, and the source/drain regions may be formed in the third semiconductor layer 1034. In addition, the isolation island 1032 is formed between the source/drain regions at the bottom of the fin. The isolation island can significantly reduce a leakage current between the source and the drain via the bottom of the fin.
It is to be noted that the third semiconductor layer may also include some portions grown on the sacrificial gate conductor layer 1018 during the epitaxial growth if the sacrificial gate conductor layer 1018 comprises polysilicon. Those portions may be removed in subsequent processes such as a planarization process, a gate replacement process or the like. For convenience, those portions are not shown here. In addition, the third semiconductor layer may be grown directly without forming the isolation island. As such, the second semiconductor layer 1004 may also be connected to the substrate via the third semiconductor layer at the bottom.
After the n-type device on the p-type well 1000-2 is processed as described above, similar processes may be performed for the p-type device on the n-type well 1000-1.
Specifically, as shown in
Operations as described above in conjunction with
As shown in
After the source/drain regions of the n-type device and the p-type device are formed respectively as described above, the gate replacement process may be performed, to replace the sacrificial gate stack with a real gate stack for the final devices. For example, this may be done as follows.
Next, as shown in
Subsequently, as shown in
Next, as shown in
Although the gate dielectric layer 1026 is shown in
As shown in
In case of the complementary process as described in the example, the n-type and p-type devices are processed respectively. To do this, the p-type device region on the left side is shielded by the dielectric layer portion 1020-1 to expose the n-type device region on the right side. However, the present disclosure is not limited thereto. For example, in the non-complementary process, such shielding may be omitted.
In addition, in the example, the p-type device region is firstly shielded and then the n-type device region is processed. However, the present disclosure is not limited thereto. An order in which the n-type device region and the p-type device region are processed may be exchanged.
In the above descriptions, details of patterning and etching of the layers are not described. It is to be understood by those skilled in the art that various measures may be utilized to form the layers and regions in desired shapes. Further, to achieve the same feature, those skilled in the art can devise processes not entirely the same as those described above. The mere fact that the various embodiments are described separately does not mean that means recited in the respective embodiments cannot be used in combination to advantage.
The present disclosure is described above with reference to the embodiments thereof. However, those embodiments are provided just for illustrative purpose, rather than limiting the present disclosure. The scope of the disclosure is defined by the attached claims as well as equivalents thereof. Those skilled in the art can make various alternations and modifications without departing from the scope of the disclosure, which all fall within the scope of the disclosure.
Number | Date | Country | Kind |
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2012 1 0447361 | Nov 2012 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2012/085259 | 11/26/2012 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
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WO2014/071661 | 5/15/2014 | WO | A |
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Number | Date | Country | |
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20150287828 A1 | Oct 2015 | US |