A high performance computing (HPC) semiconductor package may include one or more integrated circuit (IC) dies, or chips, from a semiconductor wafer, such as a system-on-chip (SoC) IC die, a dynamic random access memory (DRAM) IC die, or a high bandwidth memory (HBM) IC die. The HPC semiconductor package may include an interposer that provides an interface between the one or more IC dies and a substrate. The HPC semiconductor package further includes one or more connection structures to provide electrical connectivity for signaling between the one or more IC dies, the interposer, and the substrate.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In some cases, a semiconductor package includes one or more IC dies, an interposer, a substrate, and a stiffener structure. The interposer, the substrate, and/or the stiffener structure may each include a different (e.g., mismatched) coefficient of thermal expansion (CTE). In some cases, a size of the interposer in combination with the different CTEs may cause the semiconductor package to warp under a thermal load. For example, a temperature of a surface mount (SMT) process during which the semiconductor package is mounted to a circuit board may introduce lateral stresses that cause the semiconductor package to warp. Such warpage may reduce a coplanarity between the substrate (and connection structures on a bottom surface of the substrate) and the circuit board, causing electrical opens and/or shorts between the connection structures on the bottom surface of the substrate and the circuit board. Additionally, or alternatively, the warpage may cause damage to connection structures between the interposer and the substrate.
Some implementations described herein provide techniques and apparatuses for a semiconductor package. The semiconductor package, which may correspond to a high performance computing (HPC) package, includes a reinforcement structure that is embedded in a substrate of the semiconductor package. The reinforcement structure may increase a rigidity of the substrate, and/or the semiconductor package, so that a coplanarity between the substrate and a circuit board is maintained during an SMT process and so that a warpage of the semiconductor package is reduced.
Maintaining the coplanarity reduces a likelihood that connection structures at a bottom surface of the substrate will fail to adequately solder or attach to lands of the circuit board during the SMT process. Additionally, reducing the warpage may increase a robustness of connection structures formed between the interposer and the substrate. In this way, a likelihood of opens and/or shorts between the semiconductor package and the circuit board is reduced and a robustness of the semiconductor package may be increased to improve an overall yield of a product including the semiconductor package.
In some implementations, the semiconductor processing tool sets 105-150, and operations performed by the semiconductor processing tool sets 105-150, are distributed across multiple facilities. Additionally, or alternatively, one or more of the semiconductor processing tool sets 105-150 may be subdivided across the multiple facilities. Sequences of operations performed by the semiconductor processing tool sets 105-150 may vary based on a type of the semiconductor package or a state of completion of the semiconductor package.
One or more of the semiconductor processing tool sets 105-150 may perform a combination of operations to assemble a semiconductor package (e.g., attach one or more IC dies to a substrate, where the substrate provides an external connectivity to a computing device, among other examples). Additionally, or alternatively, one or more of the semiconductor processing tool sets 105-150 may perform a combination of operations to ensure a quality and/or a reliability of the semiconductor package (e.g., test and sort the one or more IC dies, and/or the semiconductor package, at various stages of manufacturing).
The semiconductor package may correspond to a type of semiconductor package. For example, the semiconductor package may correspond to a flipchip (FC) type of semiconductor package, a ball grid array (BGA) type of semiconductor package, a multi-chip package (MCP) type of semiconductor package, or a chip scale package (CSP) type of semiconductor package. Additionally, or alternatively, the semiconductor package may correspond to a plastic leadless chip carrier (PLCC) type of semiconductor package, a system-in-package (SIP) type of semiconductor package, a ceramic leadless chip carrier (CLCC) type of semiconductor package, or a thin small outline package (TSOP) type of semiconductor package, among other examples.
The RDL tool set 105 includes one or more tools capable of forming one or more layers and patterns of materials (e.g., dielectric layers, conductive redistribution layers, and/or vertical connection access structures (vias), among other examples) on a semiconductor substrate (e.g., a semiconductor wafer, among other examples). The RDL tool set 105 may include a combination of one or more photolithography tools (e.g., a photolithography exposure tool, a photoresist dispense tool, a photoresist develop tool, among other examples), a combination of one or more etch tools (e.g., a plasma-based etched tool, a dry-etch tool, or a wet-etch tool, among other examples), and one or more deposition tools (e.g., a chemical vapor deposition (CVD) tool, a physical vapor deposition (PVD) tool, an atomic layer deposition (ALD) tool, or a plating tool, among other examples). In some implementations, the example environment 100 includes a plurality of types of such tools as part of RDL tool set 105.
The planarization tool set 110 includes one or more tools that are capable of polishing or planarizing various layers of the semiconductor substrate (e.g., the semiconductor wafer). The planarization tool set 110 may also include tools capable of thinning the semiconductor substrate. The planarization tool set 110 may include a chemical mechanical planarization (CMP) tool or a lapping tool, among other examples. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the planarization tool set 110.
The connection tool set 115 includes one or more tools that are capable of forming connection structures (e.g., electrically-conductive structures) as part of the semiconductor package. The connection structures formed by the connection tool set 115 may include a wire, a stud, a pillar, a bump, or a solderball, among other examples. The connection structures formed by the connection tool set 115 may include materials such as a gold (Au) material, a copper (Cu) material, a silver (Ag) material, a nickel (Ni) material, a tin (Sn) material, or a palladium (Pd) material, among other examples. The connection tool set 115 may include a bumping tool, a wirebond tool, or a plating tool, among other examples. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the connection tool set 115.
The ATE tool set 120 includes one or more tools that are capable of testing a quality and a reliability of the one or more IC dies and/or the semiconductor package (e.g., the one or more IC dies after encapsulation). The ATE tool set 120 may perform wafer testing operations, known good die (KGD) testing operations, semiconductor package testing operations, or system-level (e.g., a circuit board populated with one or more semiconductor packages and/or one or more IC dies) testing operations, among other examples. The ATE tool set 120 may include a parametric tester tool, a speed tester tool, and/or a burn-in tool, among other examples. Additionally, or alternatively, the ATE tool set 120 may include a prober tool, probe card tooling, test interface tooling, test socket tooling, a test handler tool, burn-in board tooling, and/or a burn-in board loader/unloader tool, among other examples. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the ATE tool set 120.
The singulation tool set 125 includes one or more tools that are capable of singulating (e.g., separating, removing) the one or more IC dies or the semiconductor package from a carrier. For example, the singulation tool set 125 may include a dicing tool, a sawing tool, or a laser tool that cuts the one or more IC dies from the semiconductor substrate. Additionally, or alternatively, the singulation tool set 125 may include a trim-and-form tool that excises the semiconductor package from a leadframe. Additionally, or alternatively, the singulation tool set 125 may include a router tool or a laser tool that removes the semiconductor package from a strip or a panel of an organic substrate material, among other examples. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the singulation tool set 125.
The die-attach tool set 130 includes one or more tools that are capable of attaching the one or more IC dies to the interposer, the leadframe, and/or the strip of the organic substrate material, among other examples. The die-attach tool set 130 may include a pick-and-place tool, a taping tool, a reflow tool (e.g., a furnace), a soldering tool, or an epoxy dispense tool, among other examples. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the die-attach tool set 130.
The encapsulation tool set 135 includes one or more tools that are capable of encapsulating the one or more IC dies (e.g., the one or more IC dies attached to the interposer, the leadframe, or the strip of organic substrate material). For example, the encapsulation tool set 135 may include a molding tool that encapsulates the one or more IC dies in a plastic molding compound. Additionally, or alternatively, the encapsulation tool set 135 may include a dispense tool that dispenses an epoxy polymer underfill material between the one or more IC dies and an underlying surface (e.g., the interposer or the strip of organic substrate material, among other examples). In some implementations, the example environment 100 includes a plurality of types of such tools as part of the encapsulation tool set 135.
The PCB tool set 140 incudes one or more tools that are capable of forming a PCB having one or more layers of electrically-conductive traces. The PCB tool set 140 may form a type of PCB, such as a single layer PCB, a multi-layer PCB, or a high density connection (HDI) PCB, among other examples. In some implementations, the PCB tool set 140 forms the interposer and/or the substrate using one or more layers of a buildup film material and/or fiberglass reinforced epoxy material. The PCB tool set 140 may include a laminating tool, a plating tool, a photoengraving tool, a laser cutting tool, a pick-and-place tool, an etching tool, a dispense tool, a bonding tool, and/or a curing tool (e.g., a furnace) among other examples. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the PCB tool set 140.
The SMT tool set 145 includes one or more tools that are capable of mounting the semiconductor package to a circuit board (e.g., a central processing unit (CPU) PCB, a memory module PCB, an automotive circuit board, and/or a display system board, among other examples). The SMT tool set 145 may include a stencil tool, a solder paste printing tool, a pick-and-place tool, a reflow tool (e.g., a furnace), and/or an inspection tool, among other examples. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the SMT tool set 145.
The finished goods tool set 150 includes one or more tools that are capable of preparing a final product including the semiconductor package for shipment to a customer. The finished goods tool set 150 may include a tape-and-reel tool, a pick-and-place tool, a carrier tray stacking tool, a boxing tool, a drop-testing tool, a carousel tool, a controlled-environment storage tool, and/or a sealing tool, among other examples. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the finished goods tool set 150.
The transport tool set 155 includes one or more tools that are capable of transporting work-in-process (WIP) between the semiconductor processing tools 105-150. The transport tool set 155 may be configured to accommodate one or more transport carriers such a wafer transport carrier (e.g., a wafer cassette or a front opening unified pod (FOUP), among other examples), a die carrier transport carrier (e.g., a film frame, among other examples), and/or a package transport carrier (e.g., a joint electron device engineering (JEDEC) tray or a carrier tape reel, among other examples). The transport tool set 155 may also be configured to transfer and/or combine WIP amongst transport carriers. The transport tool set 155 may include a pick-and-place tool, a conveyor tool, a robot arm tool, an overhead hoist transport (OHT) tool, an automated materially handling system (AMHS) tool, and/or another type of tool. In some implementations, the example environment 100 includes a plurality of types of such tools as part of the transport tool set 155.
One or more of the semiconductor processing tool sets 105-150 may perform a series of operations to form one or more portions of a semiconductor package. As described in greater detail in connection with
The number and arrangement of tool sets shown in
The semiconductor package 205 may include one or more IC dies (e.g., the system-on-chip (SoC) IC die 210 and/or the dynamic random access memory (DRAM) IC die 215, among other examples). The semiconductor package 205 may include an interposer 220 having one or more layers of electrically-conductive traces 225. The interposer 220 may include one or more layers of a dielectric material, such as a ceramic material or a silicon material. In some implementations, the interposer 220 corresponds to a PCB including layers of a glass-reinforced epoxy laminate material and/or a pre-preg material (e.g., a composite fiber/resin/epoxy material), among other examples. Additionally, or alternatively, one or more layers of the interposer 220 may include a buildup film material.
The electrically-conductive traces 225 may include one or more materials such as a gold (Au) material, a copper (Cu) material, a silver (Ag) material, a nickel (Ni) material, a tin (Sn) material, or a palladium (Pd) material, among other examples. In some implementations, the interposer 220 includes one or more conductive vertical access connection structures (vias) that connect one or more layers of the electrically-conductive traces 225.
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The connection structures 230 may connect lands (e.g., pads) on bottom surfaces of the SoC IC die 210 and the DRAM IC die 215 to lands on a top surface of the interposer 220. In some implementations, the connection structures 230 may include one or more electrical connections for signaling (e.g., corresponding lands of the SoC IC die 210, the DRAM IC die 215, and the interposer 220 are electrically connected to respective circuitry and/or traces of the SoC IC die 210, the DRAM IC die 215, and the interposer 220).
In some implementations, the connection structures 230 may include one or more mechanical connections for attachment purposes and/or spacing purposes (e.g., corresponding lands of the SoC IC die 210, the DRAM IC die 215, and the interposer 220 are not electrically connected to respective circuitry and/or traces of the SoC IC die 210, the DRAM IC die 215, and the interposer 220). In some implementations, one or more of the connection structures 230 may function both electrically and mechanically.
A mold compound 235 may encapsulate one or more portions of the semiconductor package 205, including portions of the SoC IC die 210 and/or the DRAM IC die 215. The mold compound 235 (e.g., a plastic mold compound, among other examples) may protect the SoC IC die 210 and/or the DRAM IC die 215 from damage during manufacturing of the semiconductor package 205 and/or during field use of the semiconductor package 205.
The semiconductor package 205 may include a substrate 240 having one or more layers of electrically-conductive traces 245. The substrate 240 may include one or more layers of a dielectric material, such as a ceramic material or a silicon material. In some implementations, the substrate 240 corresponds to a PCB including layers of a glass-reinforced epoxy laminate material and/or a pre-preg material (e.g., a composite fiber/resin/epoxy material), among other examples. Additionally, or alternatively, one or more layers of the substrate 240 may include a buildup film material.
The electrically-conductive traces 245 may include one or more materials such as a gold (Au) material, a copper (Cu) material, a silver (Ag) material, a nickel (Ni) material, a tin (Sn) material, or a palladium (Pd) material, among other examples. In some implementations, the substrate 240 includes one or more conductive vertical access connection structures (vias) that connect one or more layers of the electrically-conductive traces 245.
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The connection structures 250 may connect lands (e.g., pads) on a bottom surface of the interposer 220 to lands on a top surface of the substrate 240. In some implementations, the connection structures 250 may include one or more electrical connections for signaling (e.g., corresponding lands of the interposer 220 and the substrate 240 are electrically connected to respective circuitry and/or traces of the interposer 220 and the substrate 240). In some implementations, the connection structures 250 may include or more mechanical connections for attachment purposes and/or spacing purposes (e.g., corresponding lands of the interposer 220 and the substrate 240 are not electrically connected to respective circuitry and/or traces of the interposer 220 and the substrate 240). In some implementations, one or more of the connection structures 250 may function both electrically and mechanically.
The semiconductor package 205 may include a plurality of connection structures 255 connected to lands (e.g., pads) on a bottom surface of the substrate 240. The connection structures 255 may include one or more combinations of a stud, a pillar, a bump, or a solderball, among other examples. The connection structures 255 may include one or more materials, such as a gold (Au) material, a copper (Cu) material, a silver (Ag) material, a nickel (Ni) material, a tin (Sn) material, a lead (Pb) material, or a palladium (Pd) material, among other examples. In some implementations, the one or more materials may be lead-free (e.g., Pb-free). In some implementations, the connection structures 255 correspond to C4 connection structures.
The connection structures 255 may be used to attach the semiconductor package 205 (e.g., the substrate 240) to a circuit board (not shown) using a surface mount (SMT) process. In some implementations, the connection structures 255 may provide an electrical connection for signaling (e.g., corresponding lands of the substrate 240 and the circuit board may be electrically connected to respective circuitry and/or traces of the substrate 240 and the circuit board). In some implementations, the connection structures 255 may provide a mechanical connection to the circuit board for attachment purposes and/or spacing purposes (e.g., corresponding lands of the substrate 240 and the circuit board may not be electrically connected to respective circuitry and/or traces of the substrate 240 and the circuit board). In some implementations, one or more of the connection structures 255 may provide both mechanical and electrical connections.
The semiconductor package 205 may include one or more additional features. As described in greater detail in connection with
Additionally, or alternatively, the semiconductor package 205 includes a substrate (e.g., the substrate 240) including a bottom core layer, a top core layer, a binding material layer between the top core layer and the bottom core layer, and a reinforcement structure embedded within the binding material layer to reduce a warpage of the substrate. In some implementations, the reinforcement structure is contiguous. The semiconductor package 205 includes a stiffener structure over the substrate. In some implementations, a portion of the stiffener structure overlaps a portion of the reinforcement structure.
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In some implementations, a body of the reinforcement structure 305 includes a dielectric (e.g., a non-electrically conductive) material. In such implementations, the reinforcement structure 305 may include electrically-conductive structures or electrically-conductive traces to transmit signals within the semiconductor package 205.
In some implementations, the body of the reinforcement structures 305 includes an electrically-conductive material. In such implementations, the reinforcement structure 305 may be electrically-isolated from electrically-conductive structures or electrically-conductive traces within the semiconductor package 205.
Additionally, or alternatively, the reinforcement structure 305 may include a material having a modulus of elasticity (e.g., a Young's modulus of elasticity) that is greater than approximately 50 gigapascals (GPa). If the material has a modulus of elasticity that is less than approximately 50 GPa, a measure of rigidity of the substrate 240 (and/or the semiconductor package 205) may not satisfy a threshold that prevents the substrate 240 (and/or the semiconductor package 205) from an unacceptable warpage during an SMT process.
The reinforcement structure 305 may increase a rigidity of the substrate 240 (and/or the semiconductor package 205) so that warpage and coplanarity thresholds are satisfied during the SMT process. In some implementations, and as an example, a warpage threshold of the substrate 240 (and/or the semiconductor package 205) is included in a range of approximately −0.14 millimeters to approximately +0.23 millimeters during reflow of materials (e.g., solder) during the SMT process. Additionally, or alternatively, a coplanarity threshold of the substrate 240 (and/or the semiconductor package 205) and a circuit board (to which the semiconductor package 205 may be attached) may be less than approximately 0.3 millimeters. However, other values and ranges for the warpage and coplanarity thresholds are within the scope of the present disclosure.
Maintaining such warpage and coplanarity thresholds reduces a likelihood that the connection structures 255 at the bottom surface of the substrate 240 will fail to adequately solder or attach to lands of the circuit board during the SMT process. Additionally, maintaining the warpage and coplanarity thresholds may increase a robustness of the connection structures 250 between the interposer 220 and the substrate 240 during the SMT process and/or a package reliability test (e.g., a thermal cycling test, among other examples).
To embed the reinforcement structure 305 in the substrate 240, one or more tools of the PCB tool set 140 (e.g., the laminating tool, the plating tool, the photoengraving tool, and/or the etching tool, among other examples) may perform a series of operations that include forming a bottom layer 310 (e.g., a bottom core layer) of the substrate 240. The bottom layer 310 of the substrate 240 may include electrically-conductive traces 245a (e.g., first electrically-conductive traces) routed through a first dielectric material (e.g., a fiberglass-epoxy laminate material or a buildup film material, among other examples).
One or more tools of the PCB tool set 140 may form a binding material layer 315 over the bottom layer 310. As an example, one or more tools of the PCB tool set 140 (e.g., the laminating tool) may laminate a layer of a pre-preg material (e.g., a fabric material pre-impregnated with a resin material) onto the bottom layer 310. Additionally, or alternatively, one or more tools of the PCB tool set 140 (e.g., the dispense tool) may dispense an epoxy material onto the bottom layer 310 to form the binding material layer 315.
In some implementations, one or more tools of the PCB tool set 140 (e.g., the laser cutting tool and/or the pick-and-place tool, among other examples) form the reinforcement structure 305 in the binding material layer 315. As an example, forming the reinforcement structure 305 in the binding material layer 315 may include forming a cavity in the binding material layer 315 and depositing the reinforcement structure 305 in the cavity.
As part of embedding the reinforcement structure 305 in the substrate 240, one or more tools of the PCB tool set 140 (e.g., the laminating tool, the plating tool, the photoengraving tool, and/or the etching tool, among other examples) may perform a series of operations that include forming a top layer 320 (e.g., a top core layer) over the binding material layer 315. The top layer 320 of the substrate 240 may include electrically-conductive traces 245b (e.g., second electrically-conductive traces) routed through a second dielectric material (e.g., a fiberglass-epoxy laminate material or a buildup film material, among other examples). The curing tool of the PCB tool set 140 may cure the bottom layer 310, the binding material layer 315, the reinforcement structure 305, and the top layer 320 at an elevated temperature to form the substrate 240.
The reinforcement structure 305 may, as shown in
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The interposer 220 is connected to the substrate 240 using the connection structures 250. In some implementations, one or more tools of the connection tool set 115 perform a combination of operations to form the connection structures 250 on a bottom surface of the interposer 220 and/or a top surface of the substrate 240. In some implementations, a pick-and-place tool and a reflow tool (e.g., the pick-and-place tool and the reflow tool of the die-attach tool set 130, among other examples) may attach the interposer 220 to the substrate 240.
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The semiconductor package 205 further includes a stiffener structure 330 mounted to a top surface of the substrate 240. The stiffener structure 330 may include a plastic material, an aluminum (Al) material, or a copper (Cu) material, among other examples. A pick-and-place tool (e.g., a pick- and place tool of the die-attach tool set 130, among other examples) may attach the stiffener structure 330 to the top surface of the substrate 240. An adhesive material 335 (e.g., an epoxy, among other examples) may be between the stiffener structure 330 and the top surface of the substrate 240.
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The number and arrangement of features of the semiconductor package 205 in
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The one or more of the reinforcement structures 305c may have a length D8 and a width D9. For example, the length D8 is included in a range of approximately 5.0 millimeters to approximately 10.0 millimeters. Additionally, or alternatively, the width D9 is included in a range of approximately 5.0 millimeters to approximately 10.0 millimeters. If one or more of the length D8 and/or the width D9 are less than approximately 5.0 millimeters, an overall rigidity of the substrate 240 (and/or the semiconductor package 205) including the layout pattern 405 may not satisfy a threshold that prevents an unacceptable warpage of the semiconductor package 205 during an SMT process. If one or more of the length D8 and/or the width D9 are greater than approximately 10.0 millimeters, one or more of the reinforcement structures 305a may be mechanically incompatible with the layout pattern 405. However, other values and ranges for the length D8 and the width D9 are within the scope of the present disclosure.
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In the example layout patterns 405-415, and in other layout patterns (not illustrated), the reinforcement structure 305 includes an area that is included in a range of approximately 1% of the area of the substrate 240 to approximately 30% of the area of the substrate 240. The area of the reinforcement structure 305 may be dependent on a layout pattern (e.g., one of the layout patterns 405-415, or another layout pattern). If the area of the reinforcement structure 305 is less than approximately 1% of the area of the substrate 240, a rigidity of the substrate 240 (and/or the semiconductor package 205) may not satisfy a threshold that prevents an unacceptable warpage of the semiconductor package 205 during an SMT process. If the area of the reinforcement structure 305 is greater than approximately 30% of the substrate 240, one or more of the reinforcement structures 305 may be mechanically incompatible with the layout pattern 405-415. However, other percentages or ratios of the area of the reinforcement structure 305 to the area of the substrate 240 are within the scope of the present disclosure.
The number and arrangement of features of the semiconductor package 205 in
Bus 510 includes one or more components that enable wired and/or wireless communication among the components of device 500. Bus 510 may couple together two or more components of
Memory 530 includes volatile and/or nonvolatile memory. For example, memory 530 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). Memory 530 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable via a universal serial bus connection). Memory 530 may be a non-transitory computer-readable medium. Memory 530 stores information, instructions, and/or software (e.g., one or more software applications) related to the operation of device 500. In some implementations, memory 530 includes one or more memories that are coupled to one or more processors (e.g., processor 520), such as via bus 510.
Input component 540 enables device 500 to receive input, such as user input and/or sensed input. For example, input component 540 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and/or an actuator. Output component 550 enables device 500 to provide output, such as via a display, a speaker, and/or a light-emitting diode. Communication component 560 enables device 500 to communicate with other devices via a wired connection and/or a wireless connection. For example, communication component 560 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.
Device 500 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 530) may store a set of instructions (e.g., one or more instructions or code) for execution by processor 520. Processor 520 may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions, by one or more processors 520, causes the one or more processors 520 and/or the device 500 to perform one or more operations or processes described herein. In some implementations, hardwired circuitry is used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally, or alternatively, processor 520 may be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.
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Process 600 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.
In a first implementation, forming the reinforcement structure 305 in the binding material layer 315 includes forming a cavity in the binding material layer 315, and depositing the reinforcement structure 305 in the cavity.
In a second implementation, alone or in combination with the first implementation, forming the cavity in the binding material layer 315 includes forming the cavity using a laser to cut edges of the cavity.
In a third implementation, alone or in combination with one or more of the first and second implementations, process 600 includes connecting the substrate 240 to an interposer 220 of a semiconductor package 205.
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Additionally, or alternatively, the series of operations 705 may include one or more tools of the PCB tool set 140 (e.g., the lamination tool and the etching tool, among other examples) performing a lamination and etching operation to form the binding material layer 315 on the temporary carrier 710.
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In some implementations, the reinforcement structure 305 includes electrically-conductive structures and/or thermally-conductive structures (e.g., the electrically-conductive structures 345 and/or the thermally-conductive structures 355, among other examples). In such implementations, and as shown in
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Some implementations described herein provide techniques and apparatuses for a semiconductor package. The semiconductor package, which may correspond to an HPC package, includes a reinforcement structure that is embedded in a substrate of the semiconductor package. The reinforcement structure may increase a rigidity of the semiconductor package so that a warpage is reduced and a coplanarity between the substrate and a printed circuit board is maintained during a surface mount process.
Maintaining the coplanarity reduces a likelihood that connection structures at a bottom surface of the substrate will fail to adequately solder or attach to lands of the circuit board during a reflow process. Additionally, reducing the warpage may increase a robustness of connection structures formed between the interposer and the substrate. In this way, a likelihood of opens and/or shorts between the semiconductor package and the circuit board is reduced and a robustness of the semiconductor package may be increased to improve an overall yield of a product including the semiconductor package.
As described in greater detail above, some implementations described herein provide a semiconductor package. The semiconductor package includes an interposer including a top surface and a bottom surface. The semiconductor package includes one or more integrated circuit dies, where the one or more integrated circuit dies are electrically connected to the top surface of the interposer. The semiconductor package includes a substrate including a top layer, a bottom layer, and at least one reinforcement structure between the top layer and the bottom layer, where at least one interconnect access structure electrically connects electrically-conductive traces of the top layer to electrically conductive traces of the bottom layer, where an aspect ratio of a width of the at least one reinforcement structure to a thickness of the at least one reinforcement structure is greater relative to an aspect ratio of a width of an interconnect access structure to a length of the interconnect access structure, and where the at least one reinforcement structure is configured to improve a rigidity of the semiconductor package to reduce a warpage of the substrate. The semiconductor package includes a plurality of connection structures that electrically connect the substrate and the interposer.
As described in greater detail above, some implementations described herein provide a method. The method includes forming a bottom layer of a substrate including first electrically-conductive traces routed through a first dielectric material. The method includes forming a binding material layer over the bottom layer. The method includes forming a reinforcement structure in the binding material layer to increase a rigidity of the substrate. The method includes forming a top layer of the substrate including second electrically-conductive traces routed through a second dielectric material over the binding material layer. The method includes curing the bottom layer, the binding material layer, the reinforcement structure, and the top layer to form the substrate.
As described in greater detail above, some implementations described herein provide a semiconductor package. The semiconductor package includes a substrate including a bottom core layer, a top core layer, a binding material layer between the top core layer and the bottom core layer, and a reinforcement structure embedded within the binding material layer to reduce a warpage of the substrate, where the reinforcement structure is contiguous. The semiconductor package includes a stiffener structure over the substrate, where a portion of the stiffener structure overlaps a portion of the reinforcement structure.
As used herein, “satisfying a threshold” may, depending on the context, refer to a value being greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or the like.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.