BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a schematic diagram of a conventional semiconductor device consisting of stacked packages;
FIG. 2 shows a flow chart of the method of making a semiconductor device according to the present invention; and
FIGS. 3 to 8 show schematic step by step diagrams illustrating the method of making a semiconductor device according to the present invention.
DETAILED DESCRIPTION
Please refer to FIG. 2 showing a flow chart of the method of making a semiconductor device according to the present invention. Also refer to FIG. 3. In Step S201, a first substrate 31 is provided. The first substrate 31 has a first surface 311, a second surface 312, a plurality of first pads 313, and a plurality of second pads 314. The first pads 313 are on the first surface 311, and the second pads 314 are on the second surface 312. In Step S202, a first chip 32 is attached to the first surface 311 of the first substrate 31. In this embodiment, a first chip 32 is attached to the first surface 311 of the first substrate 31. In Step S203, a plurality of first connecting elements (such as a plurality of first conductive wires 33) electrically connect the first chip 32 and the first surface 311 of the first substrate 31. In Step 204, a plurality of first conductive bodies (such as a plurality of first solder balls 34) are formed on the first pads 313 on the first surface 311 of the first substrate 31. In this embodiment, the first conductive bodies may be solder balls; however, it may be realized that the first conductive bodies can be solder bumps, gold stud bumps, or metal pins and each in a shape of pillar or column, in addition to a shape of ball.
It should be noted that, in other applications, after Step S201 is performed, Step S204 is performed and followed by Step S202 and Step S203. That is, the first conductive bodies (such as the first solder balls) may be formed on the first pads 313 on the first surface 311 of the first substrate 31 before the first chip 32 is attached to the first surface 311 of the first substrate 31. Thereafter, the first conductive elements (such as the first conductive wires 33) are formed for electrically connecting the first chip 32 and the first surface 311 of the first substrate 31.
Please refer to FIG. 2 and FIG. 4. In Step S205, a first molding compound 35 for encapsulating the first surface 311 of the first substrate 31, the first chip 32, the first conductive wires 33, and the first solder balls 34. It should be noted that the first molding compound 35 encapsulates the entire first surface 311 of the first substrate 31. In this embodiment, the top surface of the first molding compound 35 is higher than the top of the first solder balls 34; however, it may be realized that the top surface of the first molding compound 35 can be at the same height with the top of the first solder balls 34, or the top surface of the first molding compound 35 can be lower than the top of the first solder balls 34.
The included angle between the sidewall of the first molding compound 35 and the first substrate 31 is about 85 to 95 degrees, and preferably 90 degrees, because the draft angle is almost not needed for the mold in the present invention. Furthermore, in the present invention, a plurality of the first chips 32 may be encapsulated with the first molding compound 35 and thereafter divided into a plurality of packages having a shape like tofu. Thereby, the top surface of the first molding compound 35 in the packages will not have a mold insert gate mark.
Please refer to FIG. 2 and FIG. 5. In Step S206, a plurality of second solder balls 36 are formed on the second pads 314 on the second surface 312 of the first substrate 31. It should be noted that this step is an optional step.
Please refer to FIG. 2 and FIG. 6. In Step S207, a part of a border portion of the first molding compound 35 is removed, so that the first molding compound 35 has at least two heights and one end of each of the first solder balls 34 is exposed to make a first package 3. The removal in this step may be accomplished by laser cutting, chemical etching, cutting with a cutting tool, or cutting with a water jet. In this step of this embodiment, the way of cutting with a cutting tool is used to remove the upper part 351 of the border portion of the first molding compound 35, and the lower part 352 of the border portion is remained. The central portion 353 of the first molding compound 35 is not cut away and is entirely remained.
Therefore, after the cutting, the molding compound 35 has a first height H1, a second height H2, a central portion 353, a lower part 352 of a border portion, a first top surface 354, and a second top surface 355. The first height H1 is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33. The second height H2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34. The first height H1 is greater than the second height H2. The first top surface 354 is corresponding to the first height H1, that is, the first top surface 354 is the top surface of the central portion 353. The first top surface 354 has a first surface roughness. The second top surface 355 is corresponding to the second height H2, that is, the second top surface 355 is the top surface of the lower part 352 of the border portion. The second top surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness.
Please refer to FIG. 7 showing a top view of FIG. 6. The second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting. In the embodiment, the upper parts of the first solder balls 34 are removed along with the removal of the upper part 351 of the border portion of the first molding compound 35. Therefore, only the lower parts of the first solder balls 34 are remained to form a hemispherical shape (as shown in FIG. 6). Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37. As shown in FIG. 7, the cutting lines 37 located at each of the four sides of the second top surface 355 are substantially parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
Please still refer to FIG. 6 showing a schematic diagram the first package of the present invention. The first package 3 comprises a first substrate 31, a first chip 32, a plurality of first connecting elements (such as a plurality of first conductive wires 33), a plurality of first conductive bodies (such as a plurality of first solder balls 34), a first molding compound 35, and a plurality of second solder balls 36. The first substrate 31 has a first surface 311, a second surface 312, a plurality of first pads 313 on the first surface 311, and a plurality of second pads 314 on the second surface 312. The first chip 32 is attached to the first surface 311 of the first substrate 31. In this embodiment, the first chip 32 is attached to the first surface 311 of the first substrate 31. The first conductive wires 33 electrically connect the first chip 32 and the first substrate 31. The first solder balls 34 are in a hemispherical shape and disposed on the first pads 313 of the first surface 311 of the first substrate 31. The second solder balls 36 are disposed on the second pads 314 of the second surface 312 of the first substrate 31.
The molding compound 35 encapsulates the first surface 311 of the first substrate 31, the first chip 32, the first conductive wires 33, and the first solder balls 34. The molding compound 35 has a first height H1, a second height H2, a central portion 353, a lower part 352 of a border portion, a first top surface 354, and a second top surface 355. The first height H1 is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33. The second height H2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34. The first height H1 is greater than the second height H2. The first top surface 354 is corresponding to the first height H1, that is, the first top surface 354 is the top surface of the central portion 353. The first top surface 354 has a first surface roughness. The second top surface 355 is corresponding to the second height H2, that is, the second top surface 355 is the top surface of the lower part 352 of the border portion. The second top surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness.
Please refer to FIG. 7. In this embodiment, the second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting. Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37. As shown in FIG. 7, the cutting lines 37 located at each of the four sides of the second top surface 355 are parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
Please refer to FIG. 2 and FIG. 8. In Step S208, a second package 4 is stacked on the first solder balls 34 and electrically connected to the first solder balls 34, to make a semiconductor device 5. The second package 4 may be any kind of semiconductor packages. In this embodiment, the second package 4 comprises a second substrate 41, a second chip 42, a plurality of second conductive wires 43, a second molding compound 44, and a plurality of third solder balls 45. The second substrate 41 has a first surface 411 and a second surface 412. The second chip 42 is attached to the first surface 411 of the second substrate 41. The second conductive wires 43 electrically connect the second chip 42 and the second substrate 41. The second molding compound 44 encapsulates the first surface 411 of the second substrate 41, the second chip 42, and the second conductive wires 43. The third solder balls 45 are disposed on the second surface 412 of the second substrate 41 and electrically connected to the first solder balls 34.
In this embodiment, the size of the second molding compound 44 of the second package 4 is the same as that of the first molding compound 35 of the first package 3. Thus, only one molding machine is required to perform both the molding processes for the second package 4 and the first package 3. As a result, the production cost can be reduced. In addition, in the molding process for the first package 3, the first molding compound encapsulates the entire first surface 311 of the first substrate 31, and accordingly the pads on the first surface 311 are not polluted.
Please still refer to FIG. 8, showing a schematic diagram of the semiconductor device according to the present invention. The semiconductor device 5 comprises a first package 3 and a second package 4. The second package 4 is stacked on the first package 3. The first package 3 comprises a first substrate 31, a first chip 32, a plurality of first connecting elements (such as a plurality of first conductive wires 33), a plurality of first conductive bodies (such as a plurality of first solder balls 34), a first molding compound 35, and a plurality of second solder balls 36. The first substrate 31 has a first surface 311, a second surface 312, a plurality of first pads 313 on the first surface 311, and a plurality of second pads 314 on the second surface 312. The first chip 32 is attached to the first surface 311 of the first substrate 31. The first conductive wires 33 electrically connect the first chip 32 and the first substrate 31. The first solder balls 34 are in a hemispherical shape and disposed on the first pads 313 of the first surface 311 of the first substrate 31.
The molding compound 35 encapsulates the first surface 311 of the first substrate 31, the first chip 32, the first conductive wires 33, and the first solder balls 34. The molding compound 35 has a first height H1, a second height H2, a central portion 353, a lower part 352 of a border portion, a first top surface 354, and a second top surface 355. The first height H1 is the height of the central portion 353 corresponding to the positions of the first chip 32 and the first conductive wires 33. The second height H2 is the height of the lower part 352 of the border portion corresponding to the positions of the first solder balls 34. The first height H1 is greater than the second height H2. The first top surface 354 is corresponding to the first height H1, that is, the first top surface 354 is the top surface of the central portion 353. The first top surface 354 has a first surface roughness. The second top surface 355 is corresponding to the second height H2, that is, the second top surface 355 is the top surface of the lower part 352 of the border portion. The second top surface 355 has a second surface roughness. The first surface roughness is different from the second surface roughness.
Please also refer to FIG. 7. In this embodiment, the second top surface 355 is a cutting surface and has a plurality of cutting lines 37 after the cutting. Furthermore, all the part of the molding compound 35 and the parts of the first solder balls 34 included in the second top surface 355 have the cutting lines 37. As shown in FIG. 7, the cutting lines 37 located at each of the four sides of the second top surface 355 are parallel, and the cutting lines 37 located in each of the four corners of the second top surface 355 perpendicularly cross each other, since the four corners of the second top surface 355 are cut twice.
The second package 4 comprises a second substrate 41, a second chip 42, a plurality of second conductive wires 43, a second molding compound 44, and a plurality of third solder balls 45. The second substrate 41 has a first surface 411 and a second surface 412. The second chip 42 is attached to the first surface 411 of the second substrate 41. The second conductive wires 43 electrically connect the second chip 42 and the second substrate 41. The second molding compound 44 encapsulates the first surface 411 of the second substrate 41, the second chip 42, and the second conductive wires 43. The third solder balls 45 are disposed on the second surface 412 of the second substrate 41 and electrically connected to the first solder balls 34.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Patent Application
20080073769
