BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross-sectional diagram illustrating a conventional semiconductor package;
FIG. 2 is a schematic cross-sectional diagram illustrating a semiconductor package according to the first embodiment of the present invention;
FIGS. 3A to 3E are schematic cross-sectional diagrams illustrating the semiconductor package during a manufacturing process according to the first embodiment of the present invention;
FIG. 4 is a schematic cross-sectional diagram illustrating a semiconductor package according to the second embodiment of the present invention; and
FIGS. 5A to 5D are schematic cross-sectional diagrams illustrating the semiconductor package during a manufacturing process according to the second embodiment of the present invention.
DETAILED DESCRIPTION
Please refer to FIG. 2, illustrating a semiconductor package 200 disclosed in the first embodiment according to the present invention. The semiconductor package 200 at least comprises a carrier 210, a package 220, a chip 230, and a plurality of bonding wires 240. The carrier 210 has an upper surface 211, a lower surface 212, an opening 213 penetrating the upper surface 211 and the lower surface 212, and a plurality of conductive pads 214 disposed on the lower surface 212. The package 220 is disposed on the upper surface 211 of the carrier 210 and electrically connected to the carrier 210. The package 220 has a first surface 221, a second surface 222, and a plurality of conductive elements 223. The package 220 may be a substrate type package or a leadframe type package, such as a BGA (Ball Grid Array) package or a TSOP (Thin Small Outline Package). In this embodiment, the package 220 has a structure of TSOP. The conductive elements 223 may be outer leads of a leadframe. The package 220 is electrically connected to the carrier 210 through the conductive elements 223. The chip 230 is disposed on the second surface 222 of the package 220. In this embodiment, the chip 230 is adhered to the second surface 222 of the package 220 through an adhesive. The chip 230 may be a memory chip, microprocesser, logic chip, or other chip such as DRAM, SRAM, SDRAM, ROM, EPROM, flash, Rambus or DDR memory chip. As shown in FIG. 2, the chip 230 has an active surface 231 and a plurality of bonding pads 232 on the active surface 231. The active surface 231 of the chip 230 faces to the carrier 210. The bonding pads 232 are corresponding to the opening 213 of the carrier 210. The bonding wires 240 connect the bonding pads 232 of the chip 230 and the conductive pads 214 on the lower surface 212 of the carrier 210, for electrically connecting the chip 230 and the carrier 210. Since the chip 230 is adhered to the second surface of the package 220, there is no need to further provide a substrate for carrying the chip 230. Accordingly, the height of the semiconductor package can be reduced. Furthermore, since the package 220 is disposed on the upper surface 211 of the carrier 210 and the chip 230 is electrically connected to the conductive pads 214 on the lower surface 212 of the carrier 210 through the bonding wires 240, the space for the circuit layout on the upper surface 211 and the lower surface 212 of the carrier 210 becomes relatively capacious. The semiconductor package 200 may further comprise a molding compound 250 sealing the package 220, the chip 230, and the bonding wires 240. The molding compound 250 may expose the first surface 221 of the package 220. The semiconductor package 200 may further comprise a plurality of solder balls 260 disposed on the lower surface 212 of the carrier 210, for connecting to an external circuit board (not shown). In this embodiment, a plurality of solder ball pads 215 are formed on the lower surface 212 of the carrier 210 for bonding the solder balls 260.
Please refer to FIGS. 3A to 3E illustrating the manufacturing process for the semiconductor package 200. First, referring to FIG. 3A, a carrier 210 is provided. The carrier 210 has an upper surface 211, a lower surface 212, an opening 213 penetrating the upper surface 211 and the lower surface 212, and a plurality of conductive pads 214 formed on the lower surface 212. Next, referring to FIG. 3B, a package 220 is disposed on the upper surface 211 of the carrier 210 and electrically connected to the carrier 210. The package 220 has a first surface 221, a second surface 222, and a plurality of conductive elements 223. The package 220 is electrically connected to the carrier 210 through the conductive elements 223. The package 220 may be a substrate type package or a leadframe type package, such as a BGA (Ball Grid Array) package or a TSOP (Thin Small Outline Package). In this embodiment, the package 220 has a structure of TSOP. The conductive elements 223 may be outer leads of a leadframe. Next, referring to FIG. 3C, the chip 230 is disposed on the second surface 222 of the package 220. In this embodiment, the chip 230 is adhered to the second surface 222 of the package 220 through an adhesive. The chip 230 has an active surface 231 and a plurality of bonding pads 232 on the active surface 231. The active surface 231 of the chip 230 faces to the carrier 210. The bonding pads 232 are corresponding to the opening 213 of the carrier 210. Next, referring to FIG. 3D, the bonding wires 240 are formed to connect the bonding pads 232 of the chip 230 and the conductive pads 214 on the lower surface 212 of the carrier 210, for electrically connecting the chip 230 and the carrier 210. Thereafter, please refer to FIG. 3E. A molding compound 250 is further formed to seal the package 220, the chip 230, and the bonding wires 240. Finally, a plurality of solder balls 260 are disposed on the lower surface 212 of the carrier 210, to form the semiconductor package 200 as shown in FIG. 2. In this embodiment, a plurality of solder ball pads 215 are formed on the lower surface 212 of the carrier 210 for bonding the solder balls 260.
Please refer to FIG. 4, showing a semiconductor package 300 in the second embodiment according to the present invention, which comprises a carrier 310, a package 320, a chip 330, and a plurality of bonding wires 340. The carrier 310 has an upper surface 311, a lower surface 312, an opening 313 penetrating the upper surface 311 and the lower surface 312, and a plurality of conductive pads 314 disposed on the lower surface 312. The package 320 is disposed on the upper surface 311 of the carrier 310. The package 320 has a first surface 321, a second surface 322, and a plurality of conductive elements 223. The package 320 is electrically connected to the carrier 310 through the conductive elements 323. The package 320 may be a substrate type package or a leadframe type package, such as a BGA (Ball Grid Array) package or a TSOP (Thin Small Outline Package). In this embodiment, the package 320 has a structure of BGA (Ball Grid Array). The conductive elements 323 are solder balls. The chip 330 is disposed on the second surface 322 of the package 320. The chip 330 may be adhered to the second surface 322 of the package 320 through an adhesive. The chip 330 has an active surface 331 and a plurality of bonding pads 332 on the active surface 331. The active surface 331 of the chip 330 faces to the carrier 310. The bonding pads 332 are corresponding to the opening 313 of the carrier 310. The bonding wires 340 connect the bonding pads 332 of the chip 330 and the conductive pads 314 on the lower surface 312 of the carrier 310, for electrically connecting the chip 330 and the carrier 310. The semiconductor package 300 may further comprise a molding compound 350 sealing the package 320, the chip 330, and the bonding wires 340 and a plurality of solder balls 360 disposed on the lower surface 312 of the carrier 310. In this embodiment, a plurality of solder ball pads 315 are formed on the lower surface 312 of the carrier 310 for bonding the solder balls 360.
Please refer to FIGS. 5A to 5D illustrating the manufacturing process for the semiconductor package 300. First, referring to FIG. 5A, a carrier 310 is provided. The carrier 310 has an upper surface 311, a lower surface 312, an opening 313 penetrating the upper surface 311 and the lower surface 312, and a plurality of conductive pads 314 formed on the lower surface 312. Next, referring to FIG. 5B, a package 320 is disposed on the upper surface 311 of the carrier 310. The package 320 has a first surface 321, a second surface 322, and a plurality of conductive elements 323. The package 320 is electrically connected to the carrier 310 through the conductive elements 323. The package 320 may be a substrate type package or a leadframe type package, such as a BGA (Ball Grid Array) package or a TSOP (Thin Small Outline Package). In this embodiment, the package 320 has a structure of BGA. The conductive elements 323 are solder balls. Next, referring to FIG. 5C, the chip 330 is disposed on the second surface 322 of the package 320. The chip 330 may be adhered to the second surface 322 of the package 320 through an adhesive. The chip 330 has an active surface 331 and a plurality of bonding pads 332 on the active surface 331. The active surface 331 of the chip 330 faces to the carrier 310. The bonding pads 332 are corresponding to the opening 313 of the carrier 310. A plurality of bonding wires 340 connect the bonding pads 332 of the chip 330 and the conductive pads 314 on the lower surface 312 of the carrier 310, for electrically connecting the carrier 310 and the chip 330. Thereafter, please refer to FIG. 5D. A molding compound 350 is further formed to seal the package 320, the chip 330, and the bonding wires 340. Finally, a plurality of solder balls 360 are disposed on the lower surface 312 of the carrier 310, to form the semiconductor package 300 as shown in FIG. 4. In this embodiment, a plurality of solder ball pads 315 are formed on the lower surface 312 of the carrier 310 for bonding the solder balls 360.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Patent Application
20080023816
