This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0036624, filed on Apr. 9, 2012, the entirety of which is incorporated by reference herein.
The inventive concept relates to semiconductor devices and, more particularly, to semiconductor packages and method for manufacturing the same.
Image sensors such as a charge coupled device (CCD) sensor or a complementary metal-oxide semiconductor (CMOS) image sensor have been employed in the manufacture of various electronic products, including, for instance, mobile phones, digital cameras, optical mice, security cameras, and biometric devices. As electronic products become smaller and more multi-functional, it is desirable for semiconductor packages with image sensors to have characteristics such as small size/high density, multi-function operation, high speed signal processing, high reliability, low manufacturing costs, and high definition. Research has been conducted for satisfying the above requirements.
Embodiments of the inventive concept may provide semiconductor packages capable of substantially reducing the distortion of an image which may be caused by contamination of a pixel part of a semiconductor chip used as an image sensor chip.
Embodiments of the inventive concept may also provide method for manufacturing a semiconductor package capable of preventing distortion of an image which is caused by contamination of a pixel part.
In one aspect, a semiconductor package may include: a package substrate; a semiconductor chip disposed on the package substrate and including a pixel part and an edge part; a holder covering at least a region of the edge part and exposing the pixel part; and a transparent substrate disposed adjacent to the top surface of the holder.
In some embodiments, the holder may include an inner cover part and an upper cover part; the inner cover part may be adjacent to the edge part and may further be inclined with respect to the top surface of the semiconductor chip; and the upper cover part may be connected to a top end of the inner cover part and be arranged adjacent to the transparent substrate.
In other embodiments, the holder may further include an outer cover part connected to the upper cover part and adjacent to the package substrate.
In still other embodiments, the semiconductor package may further include: an adhesive layer disposed between the outer cover part and the package substrate and/or between the inner cover part and the semiconductor chip.
In even other embodiments, an angle between a sidewall of the inner cover part and the top surface of the semiconductor chip adjacent to the pixel part may be greater than about 90 degrees.
In yet other embodiments, the upper cover part may be spaced apart from an end portion of the semiconductor chip to provide a space.
In yet still other embodiments, the semiconductor package may further include: a first adhesive layer filling the space.
In further embodiments, the first adhesive layer may extend between a bottom surface of the inner cover part and the top surface of the semiconductor chip.
In still further embodiments, the semiconductor package may further include: a second adhesive layer disposed between an end portion of the transparent substrate and the upper cover part.
In even further embodiments, the second adhesive layer may cover at least a portion of a sidewall of the transparent substrate and at least a portion of a sidewall of the upper cover part.
In yet further embodiments, a surface roughness of a top surface of the upper cover part may be greater than a surface roughness of a sidewall of the inner cover part.
In yet further embodiments, a width of a lower portion of the inner cover part may be smaller than a width of an upper portion of the inner cover part.
In yet further embodiments, the semiconductor package may further include: a wire connecting the edge part to the package substrate. The holder may cover the wire.
In yet further embodiments, the semiconductor chip may be mounted on the package substrate by a flip-chip bonding method.
In another aspect, a method for manufacturing a semiconductor package may include: mounting a semiconductor chip including a pixel part and an edge part on a package substrate; bonding a holder on the edge part, the holder covering at least a region of the edge part and exposing the pixel part, and the holder having a top surface spaced apart from a top surface of the semiconductor chip; and bonding a transparent substrate on the holder.
In some embodiments, the method may further include: performing a cleaning process after bonding the holder on the edge part.
In other embodiments, bonding the holder on the edge part may include applying a first adhesive layer covering an end portion of the semiconductor chip; locating a bottom surface of the holder on the first adhesive layer; and pressing the holder.
In still other embodiments, bonding the transparent substrate may include: applying a second adhesive layer to a top surface of the holder; locating an edge portion of the transparent substrate on the second adhesive layer; and pressing the transparent substrate.
The inventive concept will become more apparent in view of the attached drawings and accompanying detailed description.
The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The advantages and features of the inventive concept and methods of achieving them will be apparent from the following exemplary embodiments that will be described in more detail with reference to the accompanying drawings. It should be noted, however, that the inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose the inventive concept and let those skilled in the art know the category of the inventive concept. In the drawings, embodiments of the inventive concept are not limited to the specific examples provided herein and are exaggerated for clarity.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present. In contrast, the term “directly” means that there are no intervening elements. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Additionally, the embodiment in the detailed description will be described with sectional views as ideal exemplary views of the inventive concept. Accordingly, shapes of the exemplary views may be modified according to manufacturing techniques and/or allowable errors. Therefore, the embodiments of the inventive concept are not limited to the specific shape illustrated in the exemplary views, but may include other shapes that may be created according to manufacturing processes. Areas exemplified in the drawings have general properties, and are used to illustrate specific shapes of elements. Thus, this should not be construed as limited to the scope of the inventive concept.
It will be also understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present invention. Exemplary embodiments of aspects of the present inventive concept explained and illustrated herein include their complementary counterparts. The same reference numerals or the same reference designators denote the same elements throughout the specification.
Moreover, exemplary embodiments are described herein with reference to cross-sectional illustrations and/or plane illustrations that are idealized exemplary illustrations. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etching region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
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The semiconductor chip 20 may include a pixel part PA and an edge part EA. For example, the semiconductor chip 20 may be an image sensor chip. Although not shown in the drawings, a plurality of photoelectric conversion parts and a plurality of transistors may be disposed on the pixel part PA. The plurality of transistors may transmit and/or process signals transferred from the photoelectric conversion parts. A micro lens array 25 may be disposed on the pixel part PA. Peripheral circuits may be disposed on the edge part EA. Chip connection terminals 23 may be disposed on the edge part EA of the semiconductor chip 20.
In some embodiments, the edge part EA may be a portion of the semiconductor chip 20 near an edge of the semiconductor chip that may or may not include chip connection terminals 23 or peripheral circuits thereon. Also, the edge part EA may be a portion of the semiconductor chip outside of the pixel part PA. The edge part EA may substantially surround the semiconductor chip 20.
The semiconductor chip 20 may be bonded to the first surface la with a first adhesive layer 21 therebetween. For example, the first adhesive layer 21 may be a double-sided tape. In some embodiments, the semiconductor chip 20 may be mounted on the package substrate 10 by a wire bonding method. Thus, the chip connection terminal 23 may be connected to the first substrate connection terminal 3 through a wire 30.
The edge part EA of the semiconductor chip 20 may be covered by a holder 40. The holder 40 covers at least a region of the edge part EA and exposes the pixel part PA. The holder 40 has a top surface 40fs spaced apart from a top surface of the semiconductor chip 20. In more detail, the holder 40 includes an inner cover part 40a and an upper cover part 40b. The inner cover part 40a may be adjacent to the edge part EA and inclined or disposed at an angle with respect to the top surface of the semiconductor chip 20. The upper cover part 40b may be connected to a top end of the inner cover part 40a and adjacent to a transparent substrate 50. The holder 40 may further include an outer cover part 40c which is connected to the upper cover part 40b and adjacent to the package substrate 10. The inner cover part 40a, the upper cover part 40b, and the outer cover part 40c may be connected to each other to constitute one body. In other words, the inner cover part 40a, the upper cover part 40b, and the outer cover part 40c may be integrally formed into a single body. The holder 40 may have a closed loop shape in plan view. The holder 40 may be formed of a polymer material such as polyimide. An angle θ between a sidewall of the inner cover part 40a and the top surface of the semiconductor chip 20 adjacent to the pixel part PA may greater than about 90 degrees.
Thus, contaminants deposited on the sidewall of the inner cover part 40a and the top surface of the semiconductor chip 20 may be easily removed as compared with the case that the angle θ is equal to or less than 90 degrees.
The upper cover part 40b may be spaced apart from an end portion of the semiconductor chip 20 to provide a space therebetween. The space may be filled with a second adhesive layer 35. The second adhesive layer 35 may include a photosensitive adhesive polymer, a thermosetting polymer, and/or an epoxy-based mixture. The second adhesive layer 35 may be in contact with a bottom surface of the upper cover part 40b, an inner sidewall of the inner cover part 40a, and an inner sidewall of the outer cover part 40c. Additionally, the second adhesive layer 35 may be in contact with the end portion or side surface of the semiconductor chip 20 and the package substrate 10. Thus, it is possible to stably bond the holder 40 to the semiconductor chip 20 and the package substrate 10. The second adhesive layer 35 may also protect the wire 30. Additionally, the second adhesive layer 35 may protect a joint between the wire 30 and the chip connection terminal 23 and a joint between the wire 30 and the first substrate connection terminal 3. The second adhesive layer 35 may prevent joint cracks between the wire 30 and the chip connection terminal 23 and joint cracks between the wire 30 and the first substrate connection terminal 3. The second adhesive layer 35 may extend between a bottom surface of the inner cover part 40a and the top surface of the semiconductor chip 20 and between a bottom surface of the outer cover part 40c and the top surface of the package substrate 10.
Since the holder 40 covers the edge part EA of the semiconductor chip 20 to isolate the edge part EA from the pixel part PA, it is possible to substantially prevent contaminants which may exist on the edge part EA and in the holder 40 from moving to the pixel part PA. Thus, it is possible to substantially prevent distortion of an image which may be caused by such contaminants.
The transparent substrate 50 may be disposed on the upper cover part 40b, so that an empty space S is provided between the semiconductor chip 20 and transparent substrate 50. The transparent substrate 50 may be formed of a transparent glass or a transparent plastic. A third adhesive layer 45 may be disposed between an edge portion of the transparent substrate 50 and the top surface 40fs of the holder 40. The third adhesive layer 45 may include the same material as the second adhesive layer 35. The third adhesive layer 45 may extend to cover at least a portion of a sidewall of the transparent substrate 50 and at least a portion of a sidewall of the upper cover part 40b. Thus, a contact area between the third adhesive layer 45 and the transparent substrate 50 and/or a contact area between the third adhesive layer 45 and the holder 40 may become wider to improve an adhesive force therebetween.
Solder bumps or conductive bumps 55 may be bonded to the second substrate connection terminals 7, respectively.
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Additionally, a process for hardening the second adhesive layer 35 may further be performed. Ultraviolet rays may be irradiated to the second adhesive layer 35 or a heating process may be performed on the second adhesive layer 35 to perform the hardening process. When the holder 40 is bonded to the semiconductor chip 20, the pixel part PA may be less impacted by the holder 40. Thus, it may be possible to substantially prevent the pixel part PA from being damaged and/or contaminated. After the holder 40 is bonded to the semiconductor chip 20, a cleaning process may be performed using a cleaning solution. At this time, the angle θ between a sidewall of the inner cover part 40a and the top surface of the semiconductor chip 20 adjacent to the pixel part PA may be greater than approximately 90 degrees as described with reference to
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According to some embodiments, the holder 40 may cover the edge part EA of the semiconductor chip 20 such that the edge part EA is isolated from the pixel part PA. Thus, contaminants which may exist on the edge part EA and/or in the holder 40 may be substantially prevented from moving onto the pixel part PA. As a result, it is possible to reduce distortion of an image which may be caused by the contaminants.
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Other elements of the semiconductor package 104 may be the same as/similar to corresponding elements of the semiconductor package 100 according to the first embodiment.
In some embodiments, the top surface 40fs of the upper cover part 40b may be substantially coplanar with the top surface of the transparent substrate 50. Other elements of the semiconductor package 101 may be the same as/similar to corresponding elements of the semiconductor package 100 according to the first embodiment.
[Application Examples]
Since the semiconductor package according to embodiments of the inventive concept includes the holder covering the edge part of the semiconductor chip, it is possible to isolate the edge part on which the contaminants may easily exist from the pixel part. As a result, the contaminants of the edge part do not contaminate the pixel part, so that the distortion of the image may be prevented.
In the method for manufacturing the semiconductor package according to some embodiments of the inventive concept, the sidewall of the inner cover part is inclined with respect to the top surface of the pixel part by the angle greater than about 90 degrees. Thus, the cleaning process may be more easily performed. As a result, it is possible to easily remove the contaminants existing between the inner cover part and the top surface of the semiconductor chip.
While the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.
Number | Date | Country | Kind |
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10-2012-0036624 | Apr 2012 | KR | national |