The present disclosure relates to semiconductor structures and, more particularly, to semiconductor gate structures with gate height scaling and methods of manufacture.
Transistor scaling has been enabled by pitch scaling and other factors. For example, current scaling elements mainly focus on items that impact foot-print of the transistors, such as gate pitch, channel length, spacer thickness, contact critical dimension (CD), metal pitches and, for advanced technology, fin pitch. However, as the transistor further scales down to a gate pitch of about 50 nm and beyond, different factors (other than foot-print) start to play more significant roles. For example, initial gate height at the 50 nm and beyond starts to play a significant role in scaling.
Due to processes of record, the initial gate height needs to be very tall, e.g., 85 nm and more. This is due mainly to gate height loss resulting from oxide material loss during dummy gate removal and gate pre-clean process, and self aligned gate contact etch processes, as well as subsequent cleaning processes. More specifically, processes of record use interlevel dielectric (ILD) material between adjacent gate structures. This ILD material is an oxide material which is used with the initial gate structure, e.g., dummy gate structure. That is, the initial height of the oxide will correspond with the height of replacement gate structure, after several etching and cleaning processes to remove oxide material.
Due to the processes of record, though, a large budget (thick layer) of ILD is needed for the initial gate height due to oxide material loss during dummy gate removal processes, e.g., using DHF chemistries, and cleaning processes which may damage the surface of the ILD. Moreover, in subsequent processes, e.g., such as self-aligned contact etch processes, it is necessary to etch the oxide ILD with a chemistry selective to a gate cap material (e.g., SiN material); however, the oxide etch selectivity to nitride is not very good which results in additional oxide loss. Accordingly, due to this material loss, the initial height of the replacement gate structure needs to be very tall, which can result in bending and other fabrication issues.
In an aspect of the disclosure, a method comprises: forming at least one dummy gate structure with hardmask material; forming a plurality of materials over source and drain regions on sides of the at least one dummy gate structure; removing upper materials of the hardmask material such that a first material of the hardmask material remains on the dummy gate structure and in combination with a blocking material of the plurality of materials maintains a uniform gate height; forming a replacement gate structure by removing remaining material of the dummy gate structure to form a trench and depositing replacement gate material in the trench; and forming contacts to the source and drain regions.
In an aspect of the disclosure, a method comprises: forming at least one dummy gate structure comprising a sacrificial material of a predetermined height and a stack of hardmask materials on the sacrificial material; forming a plurality of materials on source and drain regions on sides of the at least one dummy gate structure; removing upper materials from the stack of hardmask materials, wherein a first material of the stack of hardmask materials remains on the sacrificial material and in combination with a blocking material of the plurality of materials maintains a uniform gate height; exposing the sacrificial material of the at least one dummy structure by removing the first material, while the blocking material maintains the uniform gate height; forming a replacement gate structure which comprises removing the sacrificial material to form a trench and depositing replacement gate material in the trench; and forming contacts to the source and drain regions.
In an aspect of the disclosure, a structure comprises: a fin structure; a replacement gate structure on the fin structure and comprising a capping material on a surface thereof and sidewalls of a same material as the capping material; a raised source region and a raised drain region on sides of the replacement gate structure; a liner material on the sidewalls of the replacement gate structure and above the raised source and drain regions; and a contact in direct electrical contact with the raised source and drain regions and positioned between the liner material of adjacent replacement gate structures.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to semiconductor gate structures with gate height scaling and methods of manufacture. More specifically, the present disclosure provides a gate height smaller than 85 nm of a-Si and 75 nm hardmask material. In more specific embodiments, the present disclosure allows a-Si to be scaled from 85 nm to about 60 nm or less, resulting in replacement gate heights of 60 nm or less.
The semiconductor gate structures of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the semiconductor gate structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the semiconductor gate structures uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
In embodiments, the dummy gate structures 12 include a stack of materials 12a-12d deposited by conventional chemical vapor deposition (CVD) processes and patterned by conventional lithography and etching (reactive ion etching (RIE)) processes. For example, the stack of material includes, e.g., amorphous silicon (a-Si) material 12a, oxide material 12b, nitride material (e.g., SiN) 12c and oxide material 12d. In embodiments, the a-Si material 12a is a sacrificial material that is removed in later processes when forming a replacement gate structure. Also, in embodiments, the stack of materials can include a thin layer of dummy gate oxide below the a-Si material 12a (also represented by reference numeral 12a).
The thin layer of dummy gate oxide can have a thickness of about 3 nm. In embodiments, the a-Si material 12a can have a height of about 60 nm (compared to a height of >80 nm for conventional processes of record). In addition, the oxide material 12b can have a height of about 5 nm to 15 nm, the nitride material (e.g., SiN) 12c can have a height of about 10 nm to 30 nm and the oxide material 12d can have a height of about 0 to 50 nm. In embodiments, the combination of the oxide material 12b, the nitride material (e.g., SiN) 12c and the oxide material 12d can be about a hardmask module on the order of about 50 nm to 100 nm.
The fin structure 14 can be fabricated using a sidewall image transfer (SIT) technique. In an example of a SIT technique, a mandrel material, e.g., SiO2, is deposited on the substrate material using conventional CVD processes. A resist is formed on the mandrel material, and exposed to light to form a pattern (openings). A reactive ion etching is performed through the openings to form the mandrels. In embodiments, the mandrels can have different widths and/or spacing depending on the desired dimensions between the fin structures 14. Spacers are formed on the sidewalls of the mandrels which are preferably material that is different than the mandrels, and which are formed using conventional deposition processes known to those of skill in the art. The spacers can have a width which matches the dimensions of the fin structures 14, for example. The mandrels are removed or stripped using a conventional etching process, selective to the mandrel material. An etching is then performed within the spacing of the spacers to form the sub-lithographic features. The sidewall spacers can then be stripped. In embodiments, the wide fin structures can also be formed during this or other patterning processes, or through other conventional patterning processes, as contemplated by the present disclosure.
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Following the CMP process, a layer of a-Si material 26 is deposited on the planarized surface, followed by deposition of hardmask materials 28 and a photoresist material 29. In embodiments, the layer of a-Si material 26 will be used to prevent damage to underlying layers during subsequent etching and cleaning processes. The a-Si material 26 can be deposited by a conventional CVD process. The hardmask materials 28 can include, e.g., optical sensitive material, e.g., (OPL) and low temperature oxide (e.g., SiCOH) or SiARC, or SiON, with the photoresist material 29 formed on a surface of the low temperature oxide material.
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Following the deposition processes for replacement gate formation, the upper material layer of the replacement gate structure 36 can be recessed, followed by a deposition of a capping layer 38. In embodiments, the recess can be about 10 nm to about 25 nm, in depth. The capping material 38 is preferably a nitride material deposited by a conventional ALD and PECVD overfill process. Any excess capping material (or other materials) on the top surface of the structure can be removed by a CMP process. An interlevel dielectric material 40 can then be deposited on the planarized surface. In embodiments, the interlevel dielectric material 40 can be an oxide material deposited by a conventional CVD process.
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In embodiments, the liner material 22 can be removed over the capping material 38 and the surface of the raised source and drain regions 20 to expose the raised source and drain regions 20. In embodiments, the liner material 22 can be removed over the raised source and drain regions 20 and upper surface of the capping material 38 by an anisotropic etching process. The removal of the liner material 22 using an anisotropic etching process also will not result in significant loss of material.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.