Patent Application
20160043108
Integrated circuits (ICs) vertical integration techniques utilize multiple active/device layers on a single die. These techniques allows for a significant increase in the number of components per IC without increasing the required die area. The die thickness may be increased, but it is the die area that is usually more of a limiting design consideration, and the overall result can be a reduced total die volume and IC package weight. The development of vertical integration techniques is, thus, of paramount importance for technologies in which electronic devices must be relatively small and lightweight, e.g. cell/smart phones, notebook/tablet PCs, etc.
Embodiments of the present invention involve a semiconductor structure with multiple active layers formed from an SOI wafer. The typical SOI wafer has an insulator layer (e.g. a buried oxide) between a substrate layer and a semiconductor layer. A first active layer is formed in and on the semiconductor layer. A second active layer is formed in and on the substrate layer. In some embodiments, a handle wafer is bonded to the SOI wafer, and the substrate layer is thinned before forming the second active layer. In some embodiments, a third active layer may be formed in the substrate of the handle wafer. In some embodiments, the first and second active layers include a MEMS device in one of these layers and a CMOS device in the other.
A more complete appreciation of the present disclosure and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.
According to some embodiments, the present invention achieves vertical integration of active layers in a monolithically formed IC semiconductor structure (e.g. semiconductor structure 100 of
In the example shown in
Additionally, the SOI wafer 101 generally includes interconnect layers 108 and 109, through which electrical connections may be made between the various components of the active layers 103 and 104. The components that are shown within the interconnect layers 108 and 109 are provided for illustrative purposes only and do not necessarily depict limitations on the present invention. In some embodiments, for example, one of the active layers (e.g. 104) may include an RF/MEMS device 110 (among other components), and the other active layer (e.g. 103) may include CMOS devices 111 (among other components) for circuitry that controls operation of the MEMS device 110.
The handle wafer 102 generally includes a handle substrate layer 112, a bonding layer 113, and an optional trap rich layer (TRL) 114. The handle wafer 102 is bonded to a top surface of the SOI wafer 101 (inverted as shown) after the formation of the first active layer 103 and the first interconnect layer 108. The handle wafer 102 is generally used to provide structural stability for the semiconductor structure 100 while processing the substrate layer 107 of the SOI wafer 101 and the formation of the second active layer 104 and second interconnect layer 109. In some embodiments, the structural stability aspect enables the substrate layer 107 of the SOI wafer 101 to be thinned before formation of the second active layer 104.
The first and second active layers 103 and 104 and the first and second interconnect layers 108 and 109 are described herein as being built up both into and onto the semiconductor layer 106 and substrate layer 107, respectively. This type of fabrication technique is known as a “monolithic” style of fabrication. A different technique of active layer fabrication is known as a “layer transfer” style, which involves the formation of the active layers in and on multiple separate wafers, followed by transferring one of the active layers onto the wafer of the other. There are various advantages and disadvantages for both of these techniques. The monolithic style, for example, generally requires serial processing for each of the manufacturing steps; whereas, the layer transfer style allows for parallel processing of the multiple wafers, thereby potentially reducing the overall time to manufacture the final semiconductor structure. However, the monolithic style generally does not require the expense of multiple substrates, does not require wafer bonding or wafer cleavage steps, does not require significant grinding or etching back steps, does not require precision wafer-aligning for bonding, and does not require a capital investment for fabrication machines that can perform the wafer-bonding-related steps. Some general exceptions to these advantages may occur in some situations, such as the wafer bonding of the handle wafer 102. However, since the handle wafer 102 does not have additional circuitry prior to bonding, there is no need for a high-precision alignment of the wafers 101 and 102. Thus, the bonding step for the handle wafer 102 can be relatively simple and cheap compared to approaches where multiple active layers on multiple wafers are integrated via a layer transfer process.
A simplified example manufacturing process, according to some embodiments for forming the semiconductor structure 100 of
The first interconnect layer 108 is then formed on the “top” or “upper” surface of the first active layer 103. Since the SOI wafer 101 is subsequently inverted from the orientation shown in
Additionally, for purposes of description herein, when material or layers are added to a wafer, the added material or layers are considered to become part of the wafer. Also, when material or layers are removed from the wafer, the removed material or layers are no longer considered to be part of the wafer. Therefore, for example, the element designated as the SOI wafer 101 or the handle wafer 102 in the Figs. may increase or decrease in size or thickness as it is being processed.
Also, for purposes of description herein, a surface referred to as the “top surface” or “bottom surface” of a wafer may change during processing when material or layers are added to or removed from the wafer. For example, the first active layer 103 is formed by front side processing in and on the top surface of the SOI wafer 101, but the material that is placed on the SOI wafer 101 creates a new top surface. Thus, the first interconnect layer 108 is formed on the new top surface. Then when the handle wafer 102 is bonded to the SOI wafer 101, it is bonded to yet another new top surface thereof.
Furthermore, various layers of materials are described herein. However, there is not necessarily a distinct demarcation line between some of the layers. For example, some materials formed during fabrication of the interconnect layers 108 or 109 may extend into other layers. Through semiconductor vias (TSVs), for example, may be formed through the active layers 103 or 104 and the insulator layer 105. Other examples of overlapping layers may also become apparent.
The simplified example manufacturing process, according to some embodiments for forming the semiconductor structure 100 of
As shown in
A portion of the substrate layer 107 is removed, thereby thinning the substrate layer 107, as shown in
In some embodiments, since the MEMS device 110 is to be formed in the second active layer 104, a cavity 115 may be formed in the substrate layer 107. The cavity 115 at least partly surrounds the MEMS device 110. The cavity 115 may be formed by any appropriate technique, e.g. orientation dependent etch, anisotropic etch, isotropic etch, etc. The cavity 115 provides isolation, improved thermal performance and/or a material for release of the MEMS device 110. A fill material is then placed inside the cavity 115 and planarized, e.g. by CMP. The fill material may be selective to the material that forms second active layer 104, so the fill material can be removed later to release the MEMS device 110. In some embodiments, the cavity 115 may extend into the insulator layer 105, so the fill material may have to be selective to the insulator material.
The second active layer 104 is then formed in and on the remaining portion of the substrate layer 107. In some embodiments, fabrication of the MEMS device 110 within the second active layer 104 is done in reverse order from the conventional process. This reverse process may aid in simplifying the bonding and interconnection for low temperatures (e.g. less than 200° C.).
The second interconnect layer 109 is then formed on the second active layer 104 (and through the two active layers 103 and 104) to produce the semiconductor structure 100 shown in
An alternative semiconductor structure 200 incorporating an alternative embodiment of the present invention is shown in
In some embodiments, a MEMS device 202 is formed in the third active layer 201, such that a cavity 203 may need to be formed in the handle substrate layer 112. The cavity 203 may be formed by any appropriate technique, e.g. orientation dependent etch, anisotropic etch, isotropic etch, etc. The cavity 203 provides isolation, improved thermal performance and/or a material for release of the MEMS device 202. A fill material is then placed inside the cavity 203 and planarized, e.g. by CMP. The fill material may be selective to the material of third active layer 201, so the fill material can be removed later to release the MEMS device 202.
The third active layer 201 is then formed in and on the remaining portion of the handle substrate layer 112.
A third interconnect layer 204 is then formed on the third active layer 201 (and through to the first active layer 103) to produce the semiconductor structure 200 shown in
Although embodiments of the present invention have been discussed primarily with respect to specific embodiments thereof, other variations are possible. Various configurations of the described system may be used in place of, or in addition to, the configurations presented herein. For example, additional components may be included where appropriate. As another example, configurations were described with general reference to certain types and combinations of semiconductor components, but other types and/or combinations of semiconductor components could be used in addition to or in the place of those described.
Those skilled in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the present invention. Nothing in the disclosure should indicate that the present invention is limited to systems that have the specific type of semiconductor components shown and described, unless otherwise indicated in the claims. Nothing in the disclosure should indicate that the present invention is limited to systems that require a particular form of semiconductor processing or integrated circuits, unless otherwise indicated in the claims. In general, any diagrams presented are only intended to indicate one possible configuration, and many variations are possible. Those skilled in the art will also appreciate that methods and systems consistent with the present invention are suitable for use in a wide range of applications.
While the specification has been described in detail with respect to specific embodiments of the present invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. These and other modifications and variations to the present invention may be practiced by those skilled in the art, without departing from the spirit and scope of the present invention, which is more particularly set forth in the appended claims.
