Claims
- 1. A method for attaching an integrated circuit (IC) wafer to a substrate, wherein said IC wafer having a plurality of input/output terminals each having a flip-chip pad, comprising:
a) securely placing a plurality of solder attaching means on said substrate with each of said solder attaching means corresponding to a location of one of said input/output terminals on said integrated circuit wafer for soldering and attaching to said flip-chip pad; b) flipping said integrated circuit wafer and aligning each flip-chip pad of the IC wafer to one of the solder attaching means; and c) mounting said IC wafer onto said substrate for placing each of said I/O terminals on a corresponding solder attaching means and applying a reflow temperature for soldering and attaching said IC wafer to said substrate.
- 2. The method of claim 1 wherein:
said step a) of securely placing a plurality of solder attaching means on said substrate is a step of securely placing a plurality of solder balls on said substrate.
- 3. The method of claim 1 wherein:
said step a) of securely placing a plurality of solder attaching means on said substrate is a step of securely placing a plurality of solder columns on said substrate.
- 4. The method of claim 1 wherein:
said step a) of securely placing a plurality of solder attaching means on said substrate is a step of securely placing a plurality of coated column each having a high-melting-point hourglass-shaped core with a predetermined standoff height.
- 5. The method of claim 1 wherein:
said step a) of securely placing a plurality of solder attaching means on said substrate is a step of securely placing a plurality of coated solder balls each having a high-melting-point ball-shaped core with a predetermined standoff height.
- 6. The method of claim 3 wherein:
said step a) of securely placing a plurality of solder columns is a step of placing a plurality of I-shaped solder column on said substrate with predetermined standoff height.
- 7. The method of claim 1 further comprising a step of:
a1) placing a photo-imageable layer between said solder attaching means wherein said photo-imageable layer is provided to sustain a reflow temperature.
- 8. The method of claim 7 wherein:
said step a1) of placing a photo-imageable layer is a step of placing a solvent dissolvable photo-imageable layer.
- 9. The method of claim 8 wherein:
said step a1) of placing a photo-imageable layer is a step of placing an organic photo-imageable layer.
- 10. The method of claim 1 wherein:
said step a) of securely placing a plurality of solder attaching means on said substrate comprising steps of: a2) forming a photo-imageable layer on said substrate; a3) opening a plurality of holes for placing said solder attaching means by photo-processing and etching said photo-imageable layer; a4) forming said solder attaching means by filling said holes with a soldering material.
- 11. The method of claim 10 wherein:
said step a4) of forming said solder attaching means by filling said holes with a soldering material is a step of employing a plating process with a solder paste for filling said holes.
- 12. The method of claim 10 wherein:
said step a) of securely placing a plurality of solder attaching means on said substrate comprising steps of further comprising a step of a5) removing said photo-imageable layer after said step a4) of forming said solder attaching means by filling said holes with a soldering material.
- 13. The method of claim 7 wherein:
said a1) of placing a photo-imageable layer between said solder attaching means is a step of employing said photo-imageable layer as an under-fill layer.
- 14. The method of claim 13 wherein:
said step of employing said photo-imageable layer as an under-fill layer further comprising a step of photo-processing said photo-imageable layer into two stratified under-fill layers with two different thermal expansion coefficients.
- 15. A substrate provided for mounting an integrated circuit (IC) wafer thereon, wherein said IC wafer having a plurality of input/output terminals each having a flip-chip pad, comprising:
a plurality of solder attaching means disposed on top said substrate with each of said solder attaching means corresponding to a location of one of said input/output terminals on said integrated circuit wafer for soldering and attaching to said flip-chip pad.
- 16. The substrate of claim 15 wherein:
said plurality of solder attaching means on said substrate are a plurality of solder balls disposed on top of said substrate.
- 17. The substrate of claim 15 wherein:
said plurality of solder attaching means on said substrate are a plurality of solder columns disposed on top of said substrate.
- 18. The substrate of claim 15 wherein:
said plurality of solder attaching means on said substrate are a plurality a plurality of coated column each having a high-melting-point hourglass-shaped core with a predetermined standoff height.
- 19. The substrate of claim 15 wherein:
said plurality of solder attaching means on said substrate are a plurality of coated solder balls each having a high-melting-point ball-shaped core with a predetermined standoff height.
- 20. The substrate of claim 18 wherein:
said plurality of solder columns are a plurality of I-shaped solder column disposed on top of said substrate with predetermined standoff height.
- 21. The substrate of claim 15 further comprising:
a photo-imageable layer disposed between said solder attaching means wherein said photo-imageable layer is provided to sustain a reflow temperature.
- 22. The substrate of claim 21 wherein:
said photo-imageable layer disposed between said solder attaching means is a solvent dissolvable photo-imageable layer.
- 23. The substrate of claim 21 wherein:
said photo-imageable layer is an organic photo-imageable layer.
- 24. A substrate provided for mounting an integrated circuit (IC) wafer thereon comprising:
a photo-imageable layer disposed on said substrate having a plurality of holes opened in locations corresponding to a plurality of input/output terminals of said IC wafer.
- 25. The substrate of claim 24 further comprising:
a plurality of solder attaching means filled in said holes with a soldering material.
- 26. The substrate of claim 25 wherein:
said solder attaching means filling said holes are solder pastes plated into said holes.
- 27. The method of claim 24 wherein:
said photo-imageable layer constituting an under-fill layer for packaging said IC wafer on said substrate.
- 28. The substrate of claim 27 wherein:
said under-fill layer further comprising at least two stratified under-fill layers wherein said layers having at least two different thermal expansion coefficients.
- 29. A substrate provided for mounting an integrated circuit (IC) wafer thereon comprising:
a plurality of solder attaching means disposed on top said substrate placed at locations corresponding to a plurality of input/output terminals of said IC wafer.
Parent Case Info
[0001] This Formal Application claims a Priority date of Jan. 13, 1998 benefited from a Provisional Application No. 60/071,177 filed by the same Applicant of this Application on Jan. 13, 1998.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60071177 |
Jan 1998 |
US |