The disclosed embodiments relate generally integrated circuit devices and, more particularly, to the cooling of stacked die packages.
To meet the demands for greater integration and reduced form factors, semiconductor device manufacturers are turning to die stacking architectures and system in package (SIP) solutions. Such architectures may combine a number of electrically interconnected die arranged in a stack, and the die stack may include both memory and logic die. These stacked die packages may find use in, for example, hand-held devices such as cell phones and personal digital assistants (PDA's), as well as other computing and/or consumer electronic devices. One challenge facing manufacturers of these SIP systems is the dissipation of heat from the die stack. Operating frequencies are increasing and available features expanding and, therefore, power consumption is rising. At the same time, however, the number of stacked die may be increasing while die sizes (and overall package size) may be decreasing, resulting in higher power densities and increased thermal resistance. A failure to address these thermal loads in stacked die packages may lead to a deterioration in package performance and reliability.
Referring to
Substrate 110 may be electrically coupled with the board 5 and, according to one embodiment, the substrate 110 provides electrical connections between the die stack 130 and the board 5. Electrical connections between the substrate 110 and board 5 may be provided by a number of interconnects 115, such as an array of solder bumps (as shown in
Substrate 110 may comprise any suitable substrate or other die carrier upon which the die stack 130 can be disposed. In one embodiment, the substrate 110 comprises a multilayer substrate including a number of alternating layers of metallization and dielectric material. Each layer of metallization comprises a number of conductors (e.g., traces), and these conductors may comprise any suitable conductive material, such as copper. Further, each metal layer is separated from adjacent metal layers by the dielectric layers, and adjacent metal layers may be electrically interconnected by conductive vias. The dielectric layers may comprise any suitable insulating material—e.g., polymers, including both thermoplastic and thermosetting resins or epoxies, ceramics, etc.—and the alternating layers of metal and dielectric material may be built-up over a core layer of a dielectric material.
Thermally conductive block 120 may comprise any suitable thermally conductive material. In one embodiment, the block 120 comprises copper or a copper alloy. However, the composition of the thermally conductive block 120 is not limited to copper (or to metals), and the block may comprise any other suitable material (or combination of materials), such as aluminum, silicon, thermally conductive composite materials, etc. Also, the thermally conductive block may have any suitable size and shape. In one embodiment, the thickness of block 120 is sufficient to provide a thermally conductive path between the die stack 130 and the board 5. According to another embodiment, the shape of the block 120 provides a periphery that lies, at least in part, within a periphery of a lower die in the die stack 130, such that electrical connections can be established between the die stack and substrate 110. Any suitable technique and/or device may be utilized to thermally couple the block 120 with board 5, including, by way of example, a thermally conductive epoxy (or other thermally conductive polymer), a composite material, or solder (this material layer not shown in the figures). The block 120 may be secured in the substrate 110 using any suitable technique and/or device. According to one embodiment, an aperture 112 is formed in substrate 110, and the thermally conductive block 120 is inserted into and secured within this aperture (e.g., by an adhesive, using a press fit, etc.). In another embodiment, the substrate 110 may be built-up around the block 120.
Die stack 130 may comprise any suitable number and combination of integrated circuit die. In one embodiment, the die stack 130 includes a lower die 132 and a number of upper die 134 (including, for example, upper die 134a, 134b, 134c, 134d) disposed on the lower die. The lower die 132 is thermally coupled with the thermally conductive block 120. Any suitable technique and/or device may be employed to thermally couple the lower die 132 with block 120, including, for example, a layer 131 of a thermally conductive epoxy (or other thermally conductive polymer), a composite material, or a solder. A layer of adhesive 136 may be used to attach the upper die 134 to one another as well as to the lower die 132 and, in one embodiment, the adhesive 136 is thermally conductive. Also, in one embodiment, a molding material 180 (shown by dashed lines) may be disposed over the die stack 130 and substrate 110.
According to one embodiment, a number of thru-vias 140 extend through and eletrically interconnect the upper die 134a-d. The thru-vias 140 may terminate at the lower die 132 and may be electrically coupled to the lower die. Any suitable number of thru-vias 140 (e.g., one or more) may be used to interconnect the upper die 134. Thru-vias 140 may be formed using any suitable process, such as, for example, etching, laser drilling, or mechanical drilling, and these vias may be formed either before or after the upper die are secured to one another. In one embodiment, as shown in
The die stack 130 is electrically coupled with the substrate 110 by one or more conductors 150. As noted above, the substrate 110 may, in turn, electrically couple the stacked die package 100 to the board 5. Any suitable number, combination, and/or configuration of conductors 150 may be employed to electrically couple the die stack 130 with the substrate 110, and various embodiments of these conductors are described below in
As previously noted, die stack 130 may comprise any suitable number and combination of die. According to one embodiment, the lower die 132 comprises a logic device and the upper die 134 comprise memory devices (e.g., flash memory). In one embodiment, the lower die 132 includes a memory controller unit for the upper die 134. It should be understood, however, that these are but a few examples of the types of die that can be combined in die stack 130 and, further, that other combinations of die and/or circuitry may be utilized, as desired. For example, in other embodiments, the lower die 132 may comprise a processing device (e.g., a microprocessor, a network processor, etc.) and each of the upper die 134 a type of dynamic random access memory (DRAM), such as double data rate DRAM (DDRDRAM) or synchronous DRAM (SDRAM), and/or a type of static random access memory (SRAM). According to other embodiments, the die stack 130 may include RF and other wireless devices and/or circuits.
Turning now to
The redistribution layer 160 may include any suitable structure capable of electrically coupling the die stack 130 to substrate 110. According to one embodiment, the redistribution layer 160 comprises multiple alternating layers of metallization and dielectric material. Each layer of metallization comprises a number of conductors (e.g., traces), and these conductors may comprise any suitable conductive material, such as copper. Further, each metal layer is separated from adjacent metal layers by the dielectric layers, and adjacent metal layers may be electrically interconnected by conductive vias. The dielectric layers may comprise any suitable insulating material—e.g., polymers, including both thermoplastic and thermosetting resins or epoxies, ceramics, etc.—and the alternating layers of metal. The redistribution layer 160 may be formed separately and disposed over and/or around the lower die 132 or, alternatively, the redistribution layer 160 may be built-up around and/or over the lower die 132.
Referring next to
Illustrated in
Referring now to
Disposed on the board 405 is a stacked die package 100 including a thermally conductive block 120, as described above. The block 120 provides a thermally conductive path between the die stack 130 and the board 405. In turn, the board 405, conductive epoxy 403, and housing 402 may provide a thermally conductive path out of the housing 402 (see arrow 409), where heat can be dissipated to the ambient environment (e.g., by convection and/or radiation). It should be understood that the apparatus 400 may employ other modes of cooling in addition to the above-described thermal conduction.
In addition to stacked package 100, other components may be disposed on the board 405. For example, as shown in
The foregoing detailed description and accompanying drawings are only illustrative and not restrictive. They have been provided primarily for a clear and comprehensive understanding of the disclosed embodiments and no unnecessary limitations are to be understood therefrom. Numerous additions, deletions, and modifications to the embodiments described herein, as well as alternative arrangements, may be devised by those skilled in the art without departing from the spirit of the disclosed embodiments and the scope of the appended claims.