Patent Application
20250062285
Various features relate to stacked integrated circuit devices.
Electrical connections exist at each level of a system hierarchy. This system hierarchy includes interconnection of active devices at a lowest system level all the way up to system level interconnections at the highest level. For example, interconnect layers can connect different devices together on an integrated circuit. As integrated circuits become more complex, more interconnect layers are used to provide the electrical connections between the devices. More recently, the number of interconnect levels for circuitry has substantially increased due to the large number of devices that are now interconnected in a modern electronic device. The increased number of interconnect levels for supporting the increased number of devices involves more intricate manufacturing processes.
During the design of modern integrated circuit devices, there is often a conflict between various design goals. For example, in some applications, it is desirable to limit integrated circuit package size, and it is desirable to improve heat dissipation. However, generally, smaller integrated circuit packages have less area for removal of heat. Thus, reducing package size can tend to reduce heat dissipation. Similar conflicts can arise between heat dissipation and processing performance because higher performance processors tend to generate more heat. Further, the goal of reducing cost can conflict with almost any other improvement goal. Thus, it is challenging to provide high performance integrated circuit devices that can meet the various design goals. These challenges are especially significant for mobile applications where power constraints, device size, processing performance, heat dissipation, cost, and many other factors come into play simultaneously.
Various features relate to integrated circuit (IC) devices.
One example provides a stacked IC device that includes a first die having a first face, a first active region adjacent to the first face, first circuitry disposed in the first active region, and first die-interconnect contacts disposed on the first face and electrically connected to the first circuitry. The stacked IC device also includes a second die having a second face, a second active region adjacent to the second face, second circuitry disposed in the second active region, and second die-interconnect contacts disposed on the second face and electrically connected to the second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are electrically connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.
Another example provides a device that includes a stacked IC device on a first side of a substrate, where the substrate has a set of external contacts on a second side. The stacked IC device includes a first die having a first face, a first active region adjacent to the first face, first circuitry disposed in the first active region, and first die-interconnect contacts disposed on the first face and electrically connected to the first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, second circuitry disposed in the second active region, and second die-interconnect contacts disposed on the second face and electrically connected to the second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are electrically connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device includes interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to the set of external contacts.
Another example provides a method for fabricating a stacked IC device. The method includes electrically connecting a first die face-to-face with a second die using first die-interconnect contacts disposed on a first face of the first die and second die-interconnect contacts disposed on a second face of the second die, where a face of a die corresponds to a surface of the die bounding an active region of the die, the active region including circuitry. The method includes forming a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The method includes forming interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.
Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.
Particular aspects of the disclosure describe integrated circuit (IC) devices and methods of fabrication that use a face-to-face stacked die configuration to achieve various IC design goals. In this context, a “face” of a die refers to the surface of the die adjacent to an active region of the die that includes active circuitry. For example, the active region can include various layers and structures that define circuit elements, such as transistors, conductors, passive circuit elements (e.g., resistors, inductors, capacitors, etc.). In this example, the face of the die corresponds to the side of the die that bounds this active region. In contrast, a “back” of the die refers to an opposite side of the die which bounds an inactive region of the die. For example, the inactive region typically includes undoped monocrystalline semiconductive material and other inactive layers (e.g., passivation layers).
Stacking dies face-to-face enables the use of short, high-density (e.g., small pitch) interconnections between the dies. Shorter interconnections are generally subject to less resistive loss, resulting in improved power efficiency and less heat generation. Additionally, shorter interconnections enable faster signal exchange than longer interconnections. Further, high-density interconnections between the dies results in smaller IC package size and/or an increase in area available for heat exchange.
In particular implementations described herein, two or more dies are stacked face-to-face, and circuitry of the two or more dies is electrically interconnected via die-interconnect conductors. External connections to either or both of the dies are provided via external contacts of a package substrate (e.g., an array of solder balls). For example, the external contacts can be electrically connected to one or more of the stacked dies via interconnect conductors (e.g., through-mold vias or vias of an interposer device) and a set of redistribution layers. In this arrangement, the stacked dies can be devoid of through silicon vias, which simplifies fabrication of the dies. Avoiding the use of through silicon vias for die-to-die signaling also uses the footprint area of each die more efficiently since no areas of the die are dedicated to accommodating through silicon vias.
In various implementations, the face-to-face stacked die arrangement disclosed herein is a low cost and technically achievable way to provide a packaged IC with a small form factor while also achieving other technical benefits, such as improved die interconnect density, simplified die fabrication, improved thermal management, improved power distribution network performance, etc. For example, electrically connecting the faces of the dies enables use of small, densely packed die-interconnect contacts and conductors therebetween. For example, microbumps or similar technology can be used to interconnect the dies, providing short, high-density interconnection between the dies. As another example, electrically connecting the dies to external contacts through a set of redistribution layers coupled to the faces of the dies avoids the need for through-silicon vias in one or more of the dies, which reduces die fabrication cost, enables more efficient use of die footprint area, improves die yield, and simplifies die design. As yet another example, when the dies are stacked face-to-face in an offset arrangement, heat generating portions of the dies can be offset from one another, providing improved thermal management. Further, in this example, devices that provide additional benefits can be disposed in offset regions adjacent to the dies. To illustrate, a device that includes one or more capacitors can be disposed in such an offset region and electrically connected to a power distribution network of a die of the die stack, which provides a short signal path between the power distribution network and the capacitor(s), which improves the performance of the power distribution network. The face-to-face stacked die arrangements disclosed herein can also enable shorter signal paths between one or more dies and one or more other devices, such as between a processing die and a memory device, thereby improving performance of the packaged IC device.
In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.
Particular aspects of the present disclosure are described below with reference to the drawings. In the description, common features are designated by common reference numbers. As used herein, various terminology is used for the purpose of describing particular implementations only and is not intended to be limiting of implementations. For example, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, some features described herein are singular in some implementations and plural in other implementations. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optional plural (as indicated by “(s)”) unless aspects related to multiple of the features are being described.
As used herein, the terms “comprise,” “comprises,” and “comprising” may be used interchangeably with “include.” “includes,” or “including.” As used herein, “exemplary” indicates an example, an implementation, and/or an aspect, and should not be construed as limiting or as indicating a preference or a preferred implementation. As used herein, an ordinal term (e.g., “first,” “second,” “third,” etc.) used to modify an element, such as a structure, a component, an operation, etc., does not by itself indicate any priority or order of the element with respect to another element, but rather merely distinguishes the element from another element having a same name (but for use of the ordinal term). As used herein, the term “set” refers to one or more of a particular element, and the term “plurality” refers to multiple (e.g., two or more) of a particular element.
Improvements in manufacturing technology and demand for lower cost and more capable electronic devices has led to increasing complexity of ICs. Often, more complex ICs have more complex interconnection schemes to enable interaction between ICs of a device. The number of interconnect levels for circuitry has substantially increased due to the large number of devices that are now interconnected in a state-of-the-art mobile application device.
These interconnections include back-end-of-line (BEOL) interconnect layers, which may refer to the conductive interconnect layers for electrically coupling to front-end-of-line (FEOL) active devices of an IC. The various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, in which lower BEOL interconnect levels generally use thinner metal layers relative to upper BEOL interconnect levels. The BEOL interconnect layers may electrically couple to middle-of-line (MOL) interconnect layers, which interconnect to the FEOL active devices of an IC.
State-of-the-art mobile application devices demand a small form factor, low cost, a tight power budget, and high electrical performance. Mobile package design has evolved to meet these divergent goals for enabling mobile applications that support multimedia enhancements. For example, fan-out (FO) wafer level packaging (WLP) or FO-WLP process technology is a development in packaging technology that is useful for mobile applications. This chip first FO-WLP process technology solution provides flexibility to fan-in and fan-out connections from a die to package balls. In addition, this solution also provides a height reduction of a first level interconnect between the die and the package balls of mobile application devices. These mobile applications, however, are susceptible to power and signal routing issues when multiple dies are arranged within the small form factor.
Stacked die schemes and chiplet architectures are becoming more common as significant power performance area (PPA) yield enhancements are demonstrated for stacked die and chiplet architecture product lines. As used herein, “stacked dies” and/or “stacked ICs” refer to arrangements in which one die (e.g., a first die) is disposed over (including directly over) another die (e.g., a second die). In a stacked die or stacked IC device, the one or more of the dies can also be positioned over one or more other devices, such as an integrated capacitor device, as described further below. Unfortunately, stacked die schemes can involve high power density targets, which impose significant power distribution inefficiencies. Various aspects of the present disclosure provide a stacked IC device arranged to provide improved integration of a capacitor with a power distribution network (PDN), resulting in improved PDN performance.
As used herein, the term “layer” includes a film, and is not construed as indicating a vertical or horizontal thickness unless otherwise stated. As used herein, the term “chiplet” may refer to an integrated circuit block, a functional circuit block, or other like circuit block specifically designed to work with one or more other chiplets to form a larger, more complex chiplet architecture.
A 3D integrated circuit (3D IC) includes a set of stacked and interconnected dies. Generally, a 3D IC architecture can achieve higher performance, increased functionality, lower power consumption, and/or smaller footprint, as compared to providing the same circuitry in a monolithic die or in a two-dimensional (2D) IC structure. Unfortunately, capacitive decoupling for power distribution networks (PDNs) of 3D ICs to suppress power distribution noise is challenging. In particular, the available space for landside capacitors (LSCs) under a die shadow in a 3D IC is limited due to the smaller footprint of 3D ICs. For example, different logic blocks of a 3D IC may be placed to overlap each other in the stacked dies, making it even more challenging to provide decoupling for the circuitry in the stacked dies. In addition, an electrical path of the traditional landside capacitor placement on a package substrate may exhibit larger inductance parasitics, which may degrade the landside capacitor decoupling performance.
The first die 110 includes a first active region 116 adjacent to a first face 112 of the first die 110 and a first inactive region 118 adjacent to a back 114 of the first die 110. The first active region 116 includes first circuitry, such as conductors, passive components, transistors, etc. For example, the first circuitry can include conductors arranged to form a power distribution network (PDN) and a plurality of transistors and/or other circuit elements arranged and interconnected to form logic cells, memory cells, etc. In the first active region 116, the components of the first circuitry can be formed in and/or over a semiconductor substrate by formation of various insulating layers, conductive layers, and doped/undoped regions. Different implementations can use different types of transistors, such as a field effect transistor (FET), planar FET, finFET, a gate all around FET, or mixtures of transistor types. In some implementations, a front end of line (FEOL) process may be used to fabricate the first circuitry in and/or over the semiconductor substrate. In contrast, the first inactive region 118 can include, for example, an undoped semiconductor material, oxide or passivation layers, or another material that does not include circuit elements. To illustrate, in some implementations, the first inactive region 118 is devoid of conductors, devoid of vias, devoid of contacts, or devoid of each of these.
The second die 130 includes a second active region 136 adjacent to a second face 132 of the second die 130 and a second inactive region 138 adjacent to a back 134 of the second die 130. The second active region 136 includes second circuitry, such as conductors, passive components, transistors, etc. For example, the second circuitry can include conductors arranged to form a PDN and a plurality of transistors and/or other circuit elements arranged and interconnected to form logic cells, memory cells, etc. In the second active region 136, the components of the second circuitry can be formed in and/or over a semiconductor substrate by formation of various insulating layers, conductive layers, and doped/undoped regions. Similar to the first inactive region 118, the second inactive region 138 can include, for example, an undoped semiconductor material, oxide or passivation layers, or another material that does not include circuit elements. To illustrate, in some implementations, the second inactive region 138 is devoid of conductors, devoid of vias, devoid of contacts, or devoid of each of these.
The first circuitry of the first die 110 and the second circuitry of the second die 130 are configured to cooperate to perform various operations. For example, in some implementations, the first circuitry includes one or more first functional circuit blocks and the second circuitry includes one or more second functional circuit blocks, and the first and second functional circuit block(s) are operationally dependent upon one another. In some such implementations, the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet. In other examples, one of the dies 110, 130 includes circuitry arranged to form logic blocks and the other of the dies 110, 130 includes circuitry arranged to form functional blocks to support the logic blocks, such as memory cells, additional logic blocks, etc. In one illustrative example, the first circuitry of the first die 110 includes functional blocks arranged to operate as one or more cores of a central processing unit (CPU) (e.g., configured to perform general processing tasks using sequential instructions), and the second circuitry of the second die 110 includes functional blocks arranged to operate as one or more cores of a graphics processing unit (GPU) (e.g., configured to perform high-throughput parallel processing tasks).
The first face 112 of the first die 110 includes a set of electrical contacts connected to the first circuitry, and the second face 132 of the second die 130 includes a set of electrical contacts connected to the second circuitry. In
In the stacked IC device 100, the first die-interconnect contacts 122 are electrically connected to the second die-interconnect contacts 142 to provide a set of conductive paths (such as exemplary signal path 168) between the first circuitry and the second circuitry. For example, one or more first transistors of the first circuitry can be connected to one or more second transistors of the second circuitry through the first die-interconnect contacts 122 and the second die-interconnect contacts 142. As another example, a PDN of the first circuitry can be connected to a PDN of the second circuitry through the first die-interconnect contacts 122 and the second die-interconnect contacts 142.
In a particular aspect, a set of redistribution layers 150 is electrically connected to the first redistribution contacts 124 on the first face 112, to the second redistribution contacts 144 on the second face 132, or both. Further, interconnect conductors 152 external to the first die 110 and external to the second die 130 are electrically connected to the redistribution layers 150 to provide signal paths from the first die 110, the second die 130, or both, to the external contacts 162. For example, in
Stacking the dies 110, 130 face-to-face as illustrated in
The diagram illustrated in
As noted above, in some implementations, the dies 110, 130 include chiplets. For example, in some implementations, the first die 110 is a first chiplet and the second die 130 is a second chiplet designed to operate in conjunction with the first chiplet. To illustrate, in some implementations, the circuitry of the first chiplet/first die 110 includes one or more first functional circuit blocks and the circuitry of the second chiplet/second die 130 includes one or more second functional circuit blocks, where the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one another.
Forming the stacked IC device 100 using chiplets arranged and interconnected as a 3D stacked IC can provide various benefits as compared to providing the same functional circuitry in one monolithic chip. For example, each chiplet is smaller than a single monolithic die including all of the same functional circuit blocks would be. Since yield loss (and costs due to yield lost) in IC manufacturing tends to increase as the die size increases, using smaller dies can reduce yield loss (i.e., increase yield) of the IC manufacturing process. Another benefit is that the chiplets can be fabricated in different locations and/or by different manufacturers, and in some cases, using different fabrication technologies (e.g., different fabrication technology nodes). As an example, one die of a chiplet-based integrated device (e.g., the first die 110 of the stacked IC device 100) can include components (e.g., interconnects, transistors, etc.) that have a first minimum size, and another die of the chiplet-based integrated device (e.g., the second die 130 of the stacked IC device 100) can include components (e.g., interconnects, transistors, etc.) that have a second minimum size, where the second minimum size is greater than the first minimum size. In contrast, all of the circuitry of a monolithic die is fabricated using the same fabrication technologies and equipment. As a result, when manufacturing a monolithic die, the entire die may be subject to the tightest manufacturing constraint of the most complex component of the monolithic die. In contrast, when using chiplets, different chiplets can be manufactured using different fabrication technologies (e.g., different fabrication technology nodes), and only the chiplet or chiplets that include the most complex components are subjected to the tightest manufacturing constraints. In this arrangement, chiplets fabricated using less expensive and/or higher yield fabrication technologies can be integrated with chiplets fabricated using more expensive and/or lower yield fabrication technologies to form an IC (e.g., the stacked IC device 100), resulting in overall savings. Still further, in some cases, as technology improves, the design of a chiplet can be changed. Chiplet stacking allows such new chiplet designs to be integrated with older chiplet designs to form stacked IC devices, which improves manufacturing flexibility and reduces design costs.
In
In some implementations, the PDN 212 of the first die 110 is electrically connected to the PDN 232 through the first die-interconnect contacts 122 and the second die-interconnect contacts 142. For example, the signal path 168 can connect a ground rail of the PDN 212 to a ground rail of the PDN 232. As another example, the signal path 168 can connect a power rail of the PDN 212 to a power rail of the PDN 232. In the same or different implementations, the PDN 212 of the first die 110, the PDN 232 of the second die 130, or both, are electrically connected, via the redistribution layers 150 and the interconnect conductors 152 to the external contacts 162 (e.g., to provide a power and a ground path to the stacked IC device 200).
In the example illustrated in
The ICD(s) 220, 240 include one or more capacitors formed on or embedded within a substrate. For example, in some implementations, the capacitor(s) include one or more trench capacitors (e.g., deep trench capacitors (DTCs)) in a semiconductor substrate. As another example, the capacitor(s) include or correspond to one or more multilayer ceramic capacitors. In implementations in which the stacked IC device 200 includes an ICD (e.g., one or more of the ICD(s) 220, 240), the ICD can be electrically connected to one or both of PDNs 212, 232 to suppress power distribution noise of the PDN. In conventional implementations, a PDN can be coupled to one or more landside capacitors disposed on the second side 158 of the substrate 154, to one or more embedded capacitors within the substrate 154, or both, to provide power distribution noise suppression. While one benefit of using stacked IC devices (such as the stacked IC device 200) is reduced footprint of such devices as compared to comparable monolithic IC devices, this reduced footprint can give rise to challenges with positioning of noise suppression capacitors. For example, noise suppression capacitors should be positioned as close to a PDN as possible to provide a low inductance electrical connection between the noise suppression capacitors and the PDN. Higher inductance leads to inefficient use of capacitors leading to degraded PDN performance, and thus, lower inductance electrical connections are generally preferred, especially in low-power devices (e.g., mobile communication devices or other battery powered devices). However, disposing ICD(s) adjacent to the dies 110, 130 of the stacked IC device 200 enable use of short, low inductance electrical connections between the capacitors of the ICD(s) and one or both of the PDNs 212, 232. For example, capacitor(s) of the ICD(s) 240 can be connected via a signal path 264 to the PDN 212 of the first die 110, capacitor(s) of the ICD(s) 220 can be connected via a signal path 266 to the PDN 232 of the second die 130, or both, providing improved PDN performance.
In some implementations, the transistor(s) 214 of the first die 110 are electrically connected to the transistor(s) 234 of the second die 130 through the first die-interconnect contacts 122 and the second die-interconnect contacts 142. For example, the signal path 168 can connect one or more of the transistor(s) 214 and one or more of the transistor(s) 234.
The diagram illustrated in
In
An additional device disposed adjacent to the second die 130, such as one of the additional device(s) 310, can be electrically connected, through the substrate 154, to one or more of the external contacts 162. For example, in
Additionally, or alternatively, the additional device(s) 310 can be electrically connected, through the redistribution layers 150, to the first die 110, the second die 130, the additional device(s) 320, the additional device(s) 330, or a combination thereof. For example, in
An additional device disposed adjacent to the first die 110, such as one of the additional device(s) 320, can be electrically connected, through the second substrate 350 to the additional device(s) 330. For example, in
Additionally, or alternatively, the additional device(s) 320 can be electrically connected, through the redistribution layers 150, to the first die 110, the second die 130, the additional device(s) 310, or a combination thereof. For example, in
Although
As another example, in some implementations, the contacts 324 of the additional device(s) 320 are omitted, and the signal paths to the additional device(s) 320 are routed through the redistribution layers 150. In some such implementations, signal paths between the contacts 322 of the additional device(s) 320 and the additional device(s) 330 are routed through the interconnect conductors 362. As yet another example, in some implementations, the contacts 322 of the additional device(s) 320 are omitted and the signal paths to the additional device(s) 320 are routed through the second substrate 350. In some such implementations, signal paths between the contacts 324 of the additional device(s) 320 and the first die 110, the second die 130, the additional device(s) 310, or the external contacts 162 are routed through the interconnect conductors 362.
In the example illustrated in
The diagram illustrated in
Further, although
Although
In some implementations, fabricating a stacked IC device (e.g., any of the stacked IC devices 100, 200, or 300) includes several processes.
It should be noted that the sequence of
Stage 1 of
Stage 2 illustrates a state after contacts 406 and interconnect conductors 408 have been formed on the redistribution layers 404 (or on the substrate 402 if the redistribution layers 404 are omitted). For example, one or more plating processes and one or more patterning processes can be used to form the contacts 406, the interconnect conductors 408, or both. In some implementations, the contacts 406 are formed as part of forming the redistribution layers 404 at Stage 1. The contacts 406 and the interconnect conductors 408 include a metal, such as copper, silver, tin, another conductor, or an alloy or combination thereof. In implementations in which no redistribution layers or top substrate are disposed over a stacked IC device in the final device, the contacts 406 and the interconnect conductors 408 can be omitted. For example, the contacts 406 and the interconnect conductors 408 can be omitted during formation of the stacked IC devices 100 and 200 of
Stage 3 illustrates a state after a first die 410 and optionally one or more additional devices 416 are disposed on (e.g., attached to) the redistribution layers 404 (or on the substrate 402 if the redistribution layers 404 are omitted). The first die 410 is positioned such that an active region 412 of the first die 410 faces away from the substrate 402 and an inactive region 414 of the first die 410 faces toward the substrate 402. The first die 410, the additional device(s) 416, or a combination thereof, can be positioned as illustrated at Stage 3 using an automated process, such as using a robot performing pick-and-place operations. In some implementations, the first die 410, is adhered to a surface of the redistribution layers 404 (or on the substrate 402). If signal paths to the additional device(s) 416 are routed through the contacts 406, the additional device(s) 416 can be coupled to the contacts 406 using solder. However, if signal paths to the additional device(s) 416 are not routed through the contacts 406 (e.g., during formation of the stacked IC devices 100 and 200 of
Stage 4 of
Stage 5 illustrates a state after formation of redistribution layers 420 and formation of contacts 422 and optionally interconnect conductors 424. The redistribution layers 420 correspond to the redistribution layers 150 of any of
Stage 6 illustrates a state after a second die 430 and optionally one or more additional devices 436 are disposed on (e.g., attached to) the redistribution layers 420. The second die 430 is positioned such that an active region 432 of the second die 430 faces the redistribution layers 420 (i.e., such that the first die 410 and the second die 430 are face-to-face) and an inactive region 434 is oriented away from the redistribution layers 420. The second die 430, the additional device(s) 436, or a combination thereof, can be positioned as illustrated at Stage 6 using an automated process, such as using a robot performing pick-and-place operations. In some implementations, the second die 430 is electrically connected to at least a first subset of the contacts 422 of the redistribution layer 420 (e.g., using solder, copper pillars, pad-to-pad bonding, or a similar process) to provide signal paths between circuitry in the active region 432 of the second die 430 and circuitry in the active region 412 of the first die 410. The second die 430 is also electrically connected to at least a second subset of the contacts 422 of the redistribution layer 420 (e.g., using solder, copper pillars, pad-to-pad bonding, or a similar process) to provide signal paths between circuitry in the active region 432 of the second die 430 and other components. For example, the second die 430 may be electrically connected to contacts 422 that provide signal path(s) between the second die 430 and the additional device(s) 436, the additional device(s) 416, the interconnect conductors 424, the interconnect conductors 408, one or more interposer devices, or any combination thereof.
Stage 7 of
Stage 8 illustrates a state after a substrate 442 including external contacts 444 is formed on or coupled to the assembled components of Stage 7. In some implementations, the substrate 442 is preformed and the state illustrated at Stage 8 is achieved by physically and electrically connecting the preformed substrate 442 to the assembled components of Stage 7. For example, the interconnect conductors 424 can be electrically connected to conductors of the substrate 442 to provide signal paths from the interconnect conductors 424 to appropriate ones of the external contacts 444. In other implementations, the substrate 442 is formed using various deposition and patterning operations to form alternating dielectric layers and metal layers where the metal layers are patterned to form traces and selected traces of one metal layer are electrically connected to corresponding selected traces of another metal layer to form signal paths.
Stage 9 illustrates a state after the substrate 402 is removed from the device 400 and optionally, after solder balls have been attached to the external contacts 444 to form a ball grid array 450. If multiple instances of the device 400 are being formed concurrently, individualization operations (e.g., cutting to separate the devices) can also be performed between Stages 8 and 9. In some implementations, the device 400 includes a second substrate, in which case the substrate 402 may not be removed between Stages 8 and 9. Formation of the devices 400 is complete after Stage 9 of
Exemplary Packaged Devices that Include a Stacked IC Device
The specific examples illustrated in
While each of
In some implementations, fabricating a stacked IC device includes several processes.
It should be noted that the method 1000 of
The method 1000 includes, at block 1002, electrically connecting a first die face-to-face with a second die via a first set of die-interconnect contacts disposed on a first face of the first die and a second set of die-interconnect contacts disposed on a second face of the second die, where a face of a die corresponds to a surface of the die bounding an active region of the die, the active region including circuitry. For example, the first die 110 of any of
The method 1000 also includes, at block 1004, forming one or more redistribution layers electrically connected to a set of redistribution contacts on the first face, the second face, or both. For example, the redistribution layers 150 of any of
Stages 4 to 6 illustrate and describe examples of operations that can be used to electrically connect a first die face-to-face with a second die via a first set of die-interconnect contacts disposed on a first face of the first die and a second set of die-interconnect contacts disposed on a second face of the second die and to form one or more redistribution layers electrically connected to a set of redistribution contacts on the first face, the second face, or both. For example, the first die 410 can be positioned face up (in the orientation illustrated in
The method 1000 also includes, at block 1006, forming a set of interconnects external to the first die and external to the second die and electrically connected to the redistribution layer to provide signal paths from the first die, the second die, or both, to a set of external contacts. For example, the set of interconnects external to the first die and external to the second die can include or correspond to the interconnect conductors 152 of
In some implementations, the method 1000 includes coupling a back of the second die (where the back of the second die is opposite the second face) to a first side of a substrate. In such implementations, the external contacts are coupled to a second side of the substrate. For example, in
In some implementations, the first die is devoid of through-silicon vias. In some such implementations, the first die includes a first back and a first inactive region adjacent to the first back, and the first back is devoid of electrical contacts. Further, in some implementations, the second die is also, or alternatively, devoid of through-silicon vias. In some such implementations, the second die includes a second back and a second inactive region adjacent to the second back, and the second back is devoid of electrical contacts.
In some implementations, the method 1000 also includes electrically connecting the first die, the second die, or both, to one or more additional devices. In some such implementations, signal paths between the first die and one of the additional device(s), signal paths between the second die and one of the additional device(s), or both, can be routed through the redistribution layers. For example, the first die 110, the second die 130, or both, can be electrically connected to any of the additional device(s) 310, 320, 330 via conductors of the redistribution layers 150. In some such implementations, signal paths between the first die and one of the additional device(s), signal paths between the second die and one of the additional device(s), or both, can be routed through a substrate. For example, the first die 110, the second die 130, or both, can be electrically connected to any of the additional device(s) 310, 320, 330 via conductors of the substrate 154 or the substrate 350. The additional device(s) 310, 320, 330 can include, for example, additional dies (e.g., memory), passive components (e.g., integrated capacitive devices), interposer devices, etc.
In some implementations, the method 1000 also includes at least partially encapsulating the first die, the second die, the one or more redistribution layers, and the set of interconnects in a mold compound. Examples of operations to form the mold compound 418 and 440 are described with reference to Stages 4 of
One or more of the components, processes, features, and/or functions illustrated in
It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another-even if they do not directly physically touch each other. An object A, that is coupled to an object B, may be coupled to at least part of object B. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The use of the terms “first,” “second,” “third,” and “fourth” (and/or anything above fourth) is arbitrary. Any of the components described may be the first component, the second component, the third component or the fourth component. For example, a component that is referred to as a second component, may be the first component, the second component, the third component or the fourth component. The terms “encapsulate.” “encapsulating” and/or any derivation means that the object may partially encapsulate or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component that is located on top may be located over a component that is located on a bottom. A top component may be considered a bottom component, and vice versa. As described in the disclosure, a first component that is located “over” a second component may mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located over (e.g., above) a first surface of the second component, and a third component may be located over (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. A first component that is located “in” a second component may be partially located in the second component or completely located in the second component. A value that is about X-XX, may mean a value that is between X and XX, inclusive of X and XX. The value(s) between X and XX may be discrete or continuous. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure means within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1. A “plurality” of components may include all the possible components or only some of the components from all of the possible components. For example, if a device includes ten components, the use of the term “the plurality of components” may refer to all ten components or only some of the components from the ten components.
In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and/or an under bump metallization (UBM) layer/interconnect. In some implementations, an interconnect may include an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground and/or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and/or sequences for forming the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.
Also, it is noted that various disclosures contained herein may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.
In the following, further examples are described to facilitate the understanding of the disclosure.
According to Example 1, a stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, first circuitry disposed in the first active region, and first die-interconnect contacts disposed on the first face and electrically connected to the first circuitry; a second die having a second face, a second active region adjacent to the second face, second circuitry disposed in the second active region, and second die-interconnect contacts disposed on the second face and electrically connected to the second circuitry, wherein the first face is oriented toward the second face, and wherein the first die-interconnect contacts are electrically connected to the second die-interconnect contacts; a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both; and interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.
Example 2 includes the stacked IC device of Example 1, further comprising a substrate, wherein a back of the second die is coupled to a first side of the substrate and the external contacts are coupled to a second side of the substrate, and wherein the back of the second die is opposite the second face.
Example 3 includes the stacked IC device of Example 1 or Example 2, wherein the first die is devoid of through-silicon vias.
Example 4 includes the stacked IC device of any of Examples 1 to 3, wherein the first die further comprises a first back and a first inactive region adjacent to the first back, and wherein the first back is devoid of electrical contacts.
Example 5 includes the stacked IC device of any of Examples 1 to 4, wherein the second die is devoid of through-silicon vias.
Example 6 includes the stacked IC device of any of Examples 1 to 5, wherein the second die further comprises a second back and a second inactive region adjacent to the second back, and wherein the second back is devoid of electrical contacts.
Example 7 includes the stacked IC device of any of Examples 1 to 6, wherein the first circuitry includes one or more first transistors and a first power distribution network (PDN), and wherein the second circuitry includes one or more second transistors and a second PDN.
Example 8 includes the stacked IC device of Example 7, wherein the first PDN is electrically connected to the second PDN through the first die-interconnect contacts and the second die-interconnect contacts.
Example 9 includes the stacked IC device of Example 7 or Example 8, wherein the one or more first transistors are electrically connected to the one or more second transistors through the first die-interconnect contacts and the second die-interconnect contacts.
Example 10 includes the stacked IC device of any of Examples 7 to 9 and further includes at least one first integrated capacitor device (ICD) disposed between the first face and the set of external contacts and electrically connected to the first PDN.
Example 11 includes the stacked IC device of any of Examples 7 to 10 and further includes at least one second ICD disposed adjacent to the first die and electrically connected to the second PDN.
Example 12 includes the stacked IC device of any of Examples 1 to 11 and further includes an interposer device comprising a plurality of conductive vias electrically connected to the redistribution layers and to a plurality of the external contacts.
Example 13 includes the stacked IC device of any of Examples 1 to 12 and further includes mold compound at least partially encapsulating the first die, the second die, the redistribution layers, and the interconnect conductors.
Example 14 includes the stacked IC device of Example 13, wherein at least one of the interconnect conductors includes a through-mold via.
Example 15 includes the stacked IC device of any of Examples 1 to 14 and further includes at least one additional device disposed adjacent to the first die and electrically connected to the first circuitry, the second circuitry, or both, through the redistribution layers.
Example 16 includes the stacked IC device of any of Examples 1 to 15 and further includes at least one additional device disposed adjacent to the second die and electrically connected to the first circuitry, the second circuitry, or both, through the interconnect conductors and the redistribution layers.
Example 17 includes the stacked IC device of any of Examples 1 to 16 and further includes at least one additional device and second interconnect conductors, wherein the first die is disposed between the at least one additional device and the redistribution layers, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuitry, the second circuitry, or both, through the second interconnect conductors and the redistribution layers.
Example 18 includes the stacked IC device of any of Examples 1 to 17, wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet.
Example 19 includes the stacked IC device of Example 18, wherein the first circuitry includes one or more first functional circuit blocks and the second circuitry includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one another.
According to Example 20, a method includes electrically connecting a first die face-to-face with a second die using first die-interconnect contacts disposed on a first face of the first die and second die-interconnect contacts disposed on a second face of the second die, wherein a face of a die corresponds to a surface of the die bounding an active region of the die, the active region including circuitry; forming a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both; and forming interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.
Example 21 includes the method of Example 20, further comprising coupling a back of the second die to a first side of a substrate, wherein the external contacts are coupled to a second side of the substrate, and wherein the back of the second die is opposite the second face.
Example 22 includes the method of Example 20 or Example 21, wherein the first die is devoid of through-silicon vias.
Example 23 includes the method of any of Examples 20 to 22, wherein the first die further comprises a first back and a first inactive region adjacent to the first back, and wherein the first back is devoid of electrical contacts.
Example 24 includes the method of any of Examples 20 to 23, wherein the second die is devoid of through-silicon vias.
Example 25 includes the method of any of Examples 20 to 24, wherein the second die further comprises a second back and a second inactive region adjacent to the second back, and wherein the second back is devoid of electrical contacts.
Example 26 includes the method of any of Examples 20 to 25, wherein a first active region of the first die includes first circuitry including one or more first transistors and a first power distribution network (PDN), and wherein a second active region of the second die includes second circuitry including one or more second transistors and a second PDN.
Example 27 includes the method of Example 26, wherein electrically connecting the first die face-to-face with the second die includes electrically connecting the first PDN to the second PDN through the first die-interconnect contacts and the second die-interconnect contacts.
Example 28 includes the method of Example 26 or Example 27, wherein electrically connecting the first die face-to-face with the second die includes electrically connecting the one or more first transistors to the one or more second transistors through the first die-interconnect contacts and the second die-interconnect contacts.
Example 29 includes the method of any of Examples 26 to 28 and further includes electrically connecting at least one first integrated capacitor device (ICD) disposed between the first face and the set of external contacts to the first PDN.
Example 30 includes the method of any of Examples 26 to 29 and further includes electrically connecting at least one second ICD disposed adjacent to the first die to the second PDN.
Example 31 includes the method of any of Examples 26 to 30 and further includes electrically connecting an interposer device to the redistribution layers and to a plurality of the external contacts, wherein the interposer device comprises a plurality of conductive vias.
Example 32 includes the method of any of Examples 20 to 31 and further includes at least partially encapsulating the first die, the second die, the redistribution layers, and the interconnect conductors in a mold compound.
Example 33 includes the method of Example 32 and further includes forming one or more through-mold vias, wherein at least one of the interconnect conductors includes a through-mold via.
Example 34 includes the method of any of Examples 20 to 33 and further includes electrically connecting at least one additional device to first circuitry of the first die, second circuitry of the second die, or both, through the redistribution layers.
According to Example 35, a device includes a substrate having a set of external contacts on a second side; and a stacked integrated circuit (IC) device on a first side of the substrate, the stacked IC device includes a first die having a first face, a first active region adjacent to the first face, first circuitry disposed in the first active region, and first die-interconnect contacts disposed on the first face and electrically connected to the first circuitry; a second die having a second face, a second active region adjacent to the second face, second circuitry disposed in the second active region, and second die-interconnect contacts disposed on the second face and electrically connected to the second circuitry, wherein the first face is oriented toward the second face, and wherein the first die-interconnect contacts are electrically connected to the second die-interconnect contacts; a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both; and interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to the set of external contacts.
Example 36 includes the device of Example 35, wherein a back of the second die is coupled to the first side of the substrate, and wherein the back of the second die is opposite the second face.
Example 37 includes the device of Example 35 or Example 36, wherein the first die is devoid of through-silicon vias.
Example 38 includes the device of any of Examples 35 to 37, wherein the first die further comprises a first back and a first inactive region adjacent to the first back, and wherein the first back is devoid of electrical contacts.
Example 39 includes the device of any of Examples 35 to 38, wherein the second die is devoid of through-silicon vias.
Example 40 includes the device of any of Examples 35 to 39, wherein the second die further comprises a second back and a second inactive region adjacent to the second back, and wherein the second back is devoid of electrical contacts.
Example 41 includes the device of any of Examples 35 to 40, wherein the first circuitry includes one or more first transistors and a first power distribution network (PDN), and wherein the second circuitry includes one or more second transistors and a second PDN.
Example 42 includes the device of Example 41, wherein the first PDN is electrically connected to the second PDN through the first die-interconnect contacts and the second die-interconnect contacts.
Example 43 includes the device of Example 41 or Example 42, wherein the one or more first transistors are electrically connected to the one or more second transistors through the first die-interconnect contacts and the second die-interconnect contacts.
Example 44 includes the device of any of Examples 41 to 43, wherein the stacked IC device further comprises at least one first integrated capacitor device (ICD) disposed between the first face and the first side of the substrate and electrically connected to the first PDN.
Example 45 includes the device of any of Examples 41 to 44, wherein the stacked IC device further comprises at least one second ICD disposed adjacent to the first die and electrically connected to the second PDN.
Example 46 includes the device of any of Examples 41 to 45, wherein the stacked IC device further comprises an interposer device comprising a plurality of conductive vias electrically connected to the redistribution layers and to a plurality of the external contacts.
Example 47 includes the device of any of Examples 35 to 46, wherein the stacked IC device further comprises mold compound at least partially encapsulating the first die, the second die, the redistribution layers, and the interconnect conductors.
Example 48 includes the device of Example 47, wherein at least one of the interconnect conductors includes a through-mold via.
Example 49 includes the device of any of Examples 35 to 48, wherein the stacked IC device further comprises at least one additional device disposed adjacent to the first die and electrically connected to the first circuitry, the second circuitry, or both, through the redistribution layers.
Example 50 includes the device of any of Examples 35 to 49, wherein the stacked IC device further comprises at least one additional device disposed adjacent to the second die and electrically connected to the first circuitry, the second circuitry, or both, through the interconnect conductors and the redistribution layers.
Example 51 includes the device of any of Examples 35 to 50 and further includes at least one additional device coupled to the stacked IC device through second interconnect conductors, wherein the first die is disposed between the at least one additional device and the redistribution layers, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuitry, the second circuitry, or both, through the second interconnect conductors and the redistribution layers.
Example 52 includes the device of any of Examples 35 to 51, wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet.
Example 53 includes the device of Example 52, wherein the first circuitry includes one or more first functional circuit blocks and the second circuitry includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one another.
The various features of the disclosure described herein can be implemented in different systems without departing from the disclosure. It should be noted that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the disclosure. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.
