Patent Application
20170162545
This U.S. Non-provisional Patent Application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0172996, filed on Dec. 7, 2015, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference herein in its entirety.
Exemplary embodiments of the inventive concept relate to semiconductor integrated circuits, and more particularly, to a stacked semiconductor device and a method of manufacturing the same.
Stacked semiconductor devices, in other words, three-dimensional semiconductor integrated circuits, have been introduced to reduce sizes of devices and/or systems. In the stacked semiconductor device, circuits are distributed and integrated in different semiconductor dies and then the semiconductor dies are stacked vertically. The stacked semiconductor device may include various types of semiconductor dies and at least one of the semiconductor dies may produce an excessive amount of heat during a normal operation. The excess heat may degrade the performance of the stacked semiconductor device.
According to an exemplary embodiment of the inventive concept, a stacked semiconductor device includes a plurality of semiconductor dies and a plurality of thermal-mechanical bumps. The semiconductor dies are stacked in a vertical direction. The thermal-mechanical bumps are disposed in bump layers between the semiconductor dies. Fewer thermal-mechanical bumps are disposed at a location near a heat source included in the semiconductor dies than at other locations, or a structure of the thermal-mechanical bumps at the location near the heat source is different from a structure of the thermal-mechanical bumps at other locations.
According to an exemplary embodiment of the inventive concept, a method of manufacturing a stacked semiconductor device includes stacking a plurality of semiconductor dies in a vertical direction, disposing a plurality of thermal-mechanical bumps in bump layers between the semiconductor dies and changing a location or a structure of the thermal-mechanical bumps in view of a location of a heat source included in the semiconductor dies.
According to an exemplary embodiment of the inventive concept, a method of manufacturing a stacked memory device includes integrating a plurality of function blocks forming a memory device in a plurality of semiconductor dies, stacking the semiconductor dies in a vertical direction, disposing a plurality of thermal-mechanical bumps in bump layers between the semiconductor dies and changing a disposition or a structure of the thermal-mechanical bumps depending on a location of a heat source included in the semiconductor dies.
According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a first semiconductor die disposed on a substrate; a layer disposed on the first semiconductor die; a second semiconductor die disposed on the substrate, wherein the first semiconductor die, the layer and the second semiconductor die are sequentially arranged in a direction perpendicular to an upper surface of the substrate; a heat source disposed in the first semiconductor die; a heat vulnerable region disposed in the second semiconductor die and near the heat source; and a plurality of thermal-mechanical bumps disposed in the layer, wherein a number of the thermal-mechanical bumps near the heat source is less than that away from the heat source, or a characteristic of the thermal-mechanical bumps near the heat source is different from that of those away from the heat source.
The above and other features of the inventive concept will become more clearly understood by describing in detail exemplary embodiments thereof with reference to the accompanying drawings.
Referring to
A plurality of thermal-mechanical bumps are disposed in bump layers between the semiconductor dies for mechanical support and heat transfer of the semiconductor dies (S300). In an exemplary embodiment of the inventive concept, a thermal-mechanical bump may be differentiated from a signal bump. The signal bump is a bump for transferring an electrical signal or a power between the stacked semiconductor dies or between the stacked semiconductor dies and an external device. The thermal-mechanical bump is a bump for transferring heat between the stacked semiconductor dies or between the stacked semiconductor dies and an external device or for supporting the stack structure of the semiconductor dies. The thermal-mechanical bump may not be needed for the signal transfer.
If a bump performs functions of transferring a signal or a power, it is referred to as a signal bump, even if the bump also provides functions of heat transfer and/or mechanical support. The signal bump may be electrically connected to a vertical contact such as a through-silicon via or a through-substrate via (TSV). The thermal-mechanical bump may not be electrically connected to the vertical contact. Depending on the need, the thermal-mechanical bump may be connected to the vertical contact to increase heat transfer efficiency.
Based on a location of a heat source included in the semiconductor dies, a disposition or structure of the thermal-mechanical bumps is changed (S500). The disposition of the thermal-mechanical bumps may represent a number or density of the bumps, an arrangement shape of the bumps, etc. The structure of the thermal-mechanical bumps may represent a size, a material, a shape of each bump, etc. In addition, the disposition and the structure may include a bump pad formed between the bump and the surface of the semiconductor die.
In an exemplary embodiment of the inventive concept, the number or the density of the thermal-mechanical bumps may be decreased or increased to decrease or increase heat transfer from the semiconductor die including the heat source. In an exemplary embodiment of the inventive concept, the thermal conductivity of the material forming the thermal-mechanical bumps may be decreased or increased to decrease or increase heat transfer from the semiconductor die including the heat source. As a result, with respect to at least two bump layers of the bump layers, the disposition or the structure of the thermal-mechanical bumps may be different per bump layer.
The heat source represents a local portion of the semiconductor die that consumes power consistently and generates an excessive amount of heat. For example, the heat source may include a circuit using a clock signal toggling at a high frequency, a phase-locked loop, etc. If the homogeneous semiconductor dies are stacked, the heat source may not be considered and the thermal-mechanical bumps may be disposed uniformly in all of the bump layers between the stacked semiconductor dies. The overall performance of the stacked semiconductor device may be increased by dissipating the heat uniformly through the thermal-mechanical bumps. However, the overall performance of the stacked semiconductor device may be decreased by the heat transfer if a region vulnerable to heat exists near the heat source. For example, the memory device has to perform the refresh operation more frequently as the operation temperature increases because the data retention time of the memory cells decreases as the operation temperature increases. The speed of read and write operations of the memory device may then be decreased due to increase in time taken to perform the refresh operations. Consequently, excessive heat may be transferred to the memory cells through the thermal-mechanical bumps, thereby degrading the performance of the memory device.
The stacked semiconductor device and the method of manufacturing the stacked semiconductor device according to exemplary embodiments of the inventive concept may efficiently dissipate the excessive amount of heat from the heat source by changing the disposition or the structure of the thermal-mechanical bumps based on the location of the heat source. The thermal characteristics may be optimized through the dissipation of the excessive amount of heat, and thus, performance and productivity of the stacked semiconductor device may be increased.
Hereinafter, a vertical direction may be represented by Z and two horizontal directions perpendicular to each other and to the vertical direction Z may be represented by X and Y. The vertical direction Z may include an upward direction +Z and a downward direction −Z.
Referring to
The signal bumps SBMP may transfer electrical signals and/or power between the semiconductor dies 10, 20 and 30. For example, the signal bumps SBMP may be electrically connected to vertical contacts such as through-substrate vias STSV.
The thermal-mechanical bumps TMBMP may be disposed in first and second bump layers 15, 25 between the semiconductor dies 10, 20 and 30 for the heat transfer and the mechanical support of the semiconductor dies 10, 20 and 30.
According to an exemplary embodiment of the inventive concept, in designing the stacked semiconductor device STC1, the thermal-mechanical bumps TMBMP may be disposed uniformly regardless of the heat source, and then, the disposition and the structure of the thermal-mechanical bumps TMBMP may be changed based on the location of the heat source.
For example, the disposition DST1 of
As another example, the disposition DST2 of
Referring to
The signal bumps SBMP may transfer electrical signals and/or power between the semiconductor dies 10, 20, 30, 40 and 50. For example, the signal bumps SBMP may be electrically connected to vertical contacts such as through-substrate vias STSV. The thermal-mechanical bumps TMBMP may be disposed in bump layers between the semiconductor dies 10, 20, 30, 40 and 50 for the heat transfer and the mechanical support of the semiconductor dies 10, 20, 30, 40 and 50. As illustrated in
In an exemplary embodiment of the inventive concept, the number of the thermal-mechanical bumps TMBMP in the bump layer in the upward direction +Z or in the downward direction −Z from the semiconductor die including the heat source may be decreased at an area near the heat source HS to be lower than the number of the thermal-mechanical bumps TMBMP in other areas. For example, as illustrated in
Referring to
In an exemplary embodiment of the inventive concept, the number of the thermal-mechanical bumps TMBMP in the bump layer in the upward direction +Z or in the downward direction −Z from the semiconductor die including the heat source may be decreased at an area near the heat source to be lower than the number of the thermal-mechanical bumps TMBMP in other areas.
For example, as illustrated in
An exemplary embodiment of the inventive concept in which the thermal-mechanical bumps TMBMP are removed is described with reference to
Referring to
In an exemplary embodiment of the inventive concept, the number of the thermal-mechanical bumps TMBMP in the bump layer in the upward direction +Z or in the downward direction −Z from the semiconductor die including a heat source HS may be decreased at an area near the heat source to be lower than the number of the thermal-mechanical bumps TMBMP in other areas. Further the number of the thermal-mechanical bumps TMBMP in the bump layer in the upward direction +Z or in the downward direction −Z from the semiconductor die including a heat-vulnerable region HVR may be increased at an area corresponding to the heat source HS to be lower than in other areas.
For example, as described with reference to
Referring to
The dispositions of a first bump layer 11, 12, a second bump layer 21, 22, a third bump layer 31, 32 and a fourth bump layer 41, 42 may be the same as the basic disposition DST1 of
In an exemplary embodiment of the inventive concept, the thermal conductivity of the thermal-mechanical bumps TMBMP in the bump layer in the upward direction +Z or in the downward direction −Z from the semiconductor die including a heat source HS may be decreased at an area near the heat source HS to be lower than the number of the thermal-mechanical bumps TMBMP in other areas.
For example, as illustrated in
Referring to
The dispositions of a first bump layer 11, 12 and a second bump layer 21, 22 may be the same as one of the dispositions DST3 and DST4 of
In an exemplary embodiment of the inventive concept, the density of the thermal-mechanical bumps TMBMP in the bump layers in the upward direction +Z and in the downward direction −Z from the semiconductor die including a heat source HS may be decreased at an area near the heat source HS to be lower than the number of the thermal-mechanical bumps TMBMP in other areas.
For example, as illustrated in
Referring to
The dispositions of a first bump layer 11, 12, a second bump layer 21, 22, a third bump layer 31, 32 and a fourth bump layer 41, 42 may be the same as the basic disposition DST1 of
In an exemplary embodiment of the inventive concept, the thermal conductivity of the thermal-mechanical bumps in the bump layers in the upward direction +Z and in the downward direction −Z from the semiconductor die including a heat source HS may be decreased at an area near the heat source HS to be lower than the number of the thermal-mechanical bumps TMBMP in other areas.
For example, as illustrated in
Referring to
The disposition of a first bump layer 11, 12 may be the same as the disposition DST5 of
In an exemplary embodiment of the inventive concept, the number of the thermal-mechanical bumps TMBMP in the bump layer in the upward direction +Z or in the downward direction −Z from the semiconductor die including a heat source HS may be decreased at an area near the heat source HS to be lower than the number of the thermal-mechanical bumps TMBMP in other areas. Further the number of the thermal-mechanical bumps TMBMP in the bump layer in the upward direction +Z or in the downward direction −Z from the semiconductor die including a heat-vulnerable region HVR may be increased at an area corresponding to the heat source HS to be lower than the number of the thermal-mechanical bumps TMBMP in other areas.
For example, as illustrated in
Referring to
The substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds, e.g., GaP, GaAs, GaSb, etc. In an exemplary embodiment of the inventive concept, the substrate 100 may be a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.
The substrate 100 may have a first surface 101 and a second surface 102 opposite thereto. The substrate 100 may include a first region REG1, a second region REG2 and a third region REG3. The first region REG1 may be a circuit region in which the circuit elements may be formed, the second region REG2 may be a via region in which the via structure 230 may be formed and the third region REG3 may be a thermal-mechanical region in which the thermal-mechanical bumps TMBMP may be formed.
In the first region REG1, an isolation layer 110 including an insulating material, e.g., silicon oxide, may be formed at a portion of the substrate 100 adjacent to the first surface, and circuit elements, e.g., a transistor, may be formed on the first surface 101 of the substrate 100. The transistor may include a gate structure 140 having a gate insulation layer pattern 120 and a gate electrode 130 sequentially stacked on the first surface 101 of the substrate 100, and an impurity region 105 at a portion of the substrate 100 adjacent to the gate structure 140. A gate spacer 150 may be formed on a sidewall of the gate structure 140.
The gate insulation layer pattern 120 may include an oxide, e.g., silicon oxide or a metal oxide, the gate electrode 130 may include, e.g., doped polysilicon, a metal, a metal nitride and/or a metal silicide, and the gate spacer 150 may include a nitride, e.g., silicon nitride.
In an exemplary embodiment of the inventive concept, a plurality of transistors may be formed on the first surface 101 of the substrate 100 in the first region REG1. The circuit elements may not be limited to the transistors, but various types of circuit elements, e.g., diodes, resistors, inductors, capacitors, etc., may be formed in the first region REG1.
The first, second and third insulating interlayers 160, 180 and 240 may be sequentially formed on the first surface 101 of the substrate 100 and the forth insulating interlayer 270 may be formed on the second surface 102 of the substrate 100.
The first insulating interlayer 160 may cover the circuit elements, and the contact plug 170 contacting the impurity region 105 may be formed through the first insulating interlayer 160. Alternatively, the contact plug 170 may be formed through the first insulating interlayer 160 to contact the gate structure 140. The first insulating interlayer 160 may include an oxide, e.g., silicon oxide, and the contact plug 170 may include, e.g., a metal, a metal nitride, a metal silicide, doped polysilicon, etc.
The second insulating interlayer 180 may contain the wiring 190 passing therethrough, which may contact the contact plug 170. The second insulating interlayer 180 may include a low-k dielectric material, e.g., silicon oxide doped with fluorine or carbon, a porous silicon oxide, spin on organic polymer, or an inorganic polymer, e.g., hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc.
In an exemplary embodiment of the inventive concept, the wiring 190 may include a first conductive pattern 194 and a first barrier pattern 192 partially covering the first conductive pattern 194. The first conductive pattern 194 may include a metal, e.g., copper, aluminum, tungsten, titanium, tantalum, etc., and the first barrier pattern 192 may include a metal nitride, e.g., titanium nitride, tantalum nitride, tungsten nitride, copper nitride, aluminum nitride, etc. In an exemplary embodiment of the inventive concept, the wiring 190 may be formed by a double damascene process, and thus, upper and lower portions of the wiring 190 may have different widths from each other. Alternatively, the wiring 190 may be formed by a single damascene process, and thus, the wiring 190 may have a substantially constant width regardless of the height thereof.
The via structure 230 may be formed through the first and second insulating interlayers 160 and 180 and the substrate 100, and a portion of the via structure 230 may be exposed over the second surface 102 of the substrate 100. The via structure 230 may have a top surface of which a central portion may be concave.
In an exemplary embodiment of the inventive concept, the via structure 230 may include a via electrode and an insulation layer pattern 200 surrounding a sidewall of the via electrode. The via electrode may include a second conductive pattern 220 and a second barrier layer pattern 210 surrounding a sidewall of the second conductive pattern 220. The second conductive pattern 220 may include a metal, e.g., copper, aluminum, tungsten, etc., or doped polysilicon, and the second barrier pattern 210 may include a metal nitride, e.g., titanium nitride, tantalum nitride, tungsten nitride, copper nitride, aluminum nitride, etc. The insulation layer pattern 200 may include an oxide, e.g., silicon oxide, or a nitride, e.g., silicon nitride.
The third insulating interlayer 240 and the fourth insulating interlayer 270 may contain the pad structures 260 and 280, respectively. The third insulating interlayer 240 and the fourth insulating interlayer 270 may include a low-k dielectric material, e.g., silicon oxide doped with fluorine or carbon, a porous silicon oxide, a spin on organic polymer, or an inorganic polymer, e.g., HSSQ, MSSQ, etc.
The pad structures 260 and 280 may be formed by a double damascene process or a single damascene process similarly as the wiring 190. In an exemplary embodiment of the inventive concept, the pad structures 260 and 280 may include conductive patterns 264 and 284 and barrier layer patterns 262 and 282 partially covering the conductive pattern 264 and 284, respectively.
The signal bump SBMP and the thermal-mechanical bumps TMBMP may contact the pad structures 260. For example, and the bumps SBMP and TMBMP may include a metal, e.g., silver, copper, etc., or an alloy, e.g., solder. As illustrated in
Referring to
The substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds, e.g., GaP, GaAs, GaSb, etc. In an exemplary embodiment of the inventive concept, the substrate 100 may be a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 100 may have a first surface 101 and a second surface 102 opposite thereto.
In an exemplary embodiment of the inventive concept, the isolation layer 110 may be formed by a shallow trench isolation (STI) process, and include an insulating material, e.g., silicon oxide.
A transistor serving as the circuit element may be formed by the following method.
For example, after sequentially forming a gate insulation layer and a gate electrode layer on the first surface 101 of the substrate 100 having the isolation layer 110 thereon, the gate electrode layer and the gate insulation layer may be patterned by a photolithography process to form a gate structure 140 including a gate insulation layer pattern 120 and a gate electrode 130 sequentially stacked on the first surface 101 of the substrate 100 in the first region REG1. The gate insulation layer may be formed to include an oxide, e.g., silicon oxide or a metal oxide, and the gate electrode layer may be formed to include, e.g., doped polysilicon, a metal, a metal nitride and/or a metal silicide.
A gate spacer layer may be formed on the substrate 100 and the isolation layer 110 to cover the gate structure 140, and may be anisotropically etched to form a gate spacer 150 on a sidewall of the gate structure 140. The gate spacer layer may be formed to include a nitride, e.g., silicon nitride.
Impurities may be implanted into an upper portion of the substrate 100 to form a first impurity region 105, so that the transistor including the gate structure 140 and the first impurity region 105 may be formed.
In an exemplary embodiment of the inventive concept, a plurality of transistors may be formed on the substrate 100 in the first region REG1. The circuit elements may not be limited to the transistor, but various types of circuit elements, e.g., diodes, resistors, inductors, capacitors, etc. may be formed.
A first insulating interlayer 160 may be formed on the substrate 100 to cover the circuit elements, and the contact plug 170 may be formed through the first insulating interlayer 160 to contact the first impurity region 105. Alternatively, the contact plug 170 may be formed through the first insulating interlayer 160 to contact the gate structure 140.
The first insulating interlayer 160 may be formed to include an oxide, e.g., silicon oxide. The contact plug 170 may be formed by forming a contact hole through the first insulating interlayer 160 to expose the first impurity region 105, forming a conductive layer on the exposed first impurity region 105 and the first insulating interlayer 160 to fill the contact hole, and planarizing an upper portion of the conductive layer until a top surface of the first insulating interlayer 160 may be exposed. The conductive layer may be formed to include, e.g., a metal, a metal nitride, a metal silicide, doped polysilicon, etc.
Referring to
The second insulating interlayer 180 may be formed to include a low-k dielectric material, e.g., silicon oxide doped with fluorine or carbon, a porous silicon oxide, a spin on organic polymer, or an inorganic polymer, e.g., hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc.
In an exemplary embodiment of the inventive concept, the wiring 190 may be formed by a double damascene process as follows.
After partially removing the second insulating interlayer 180 to form a via hole therethrough, which may expose top surfaces of the first insulating interlayer 160 and the contact plug 170, an upper portion of the second insulating interlayer 180 may be removed to form a first trench in communication with the via hole and having a diameter greater than that of the via hole. Alternatively, after forming the first trench, the via hole may be formed later. A first barrier layer may be formed on inner walls of the via hole and the first trench and the exposed top surfaces of the first insulating interlayer 160 and the contact plug 170, and a first conductive layer may be formed on the first barrier layer to sufficiently fill remaining portions of the via hole and the first trench. Upper portions of the first barrier layer and the first conductive layer may be planarized until a top surface of the second insulating interlayer 180 may be exposed to form the wiring 190 contacting the top surface of the contact plug 170 in the first region REG1. The wiring 190 may be formed to include a first conductive pattern 194 and a first barrier layer pattern 192 surrounding a bottom and a sidewall of the first conductive pattern 194.
The first barrier layer may be formed to include a metal nitride, e.g., titanium nitride, tantalum nitride, tungsten nitride, copper nitride, aluminum nitride, etc., and the first conductive layer may be formed to include a metal, e.g., copper, aluminum, tungsten, titanium, tantalum, etc. When the first conductive layer is formed using copper or aluminum, a seed layer may be formed on the first barrier layer, and the first conductive layer may be formed by an electroplating process.
As described above, the wiring 190 may be formed by a double damascene process, and thus, may be formed to have a lower portion and an upper portion connected thereto. Alternatively, the wiring 190 may be formed by a single damascene process. In this case, the wiring 190 may have a substantially constant thickness from a bottom portion toward a top portion thereof.
In
Referring to
For example, a first photoresist pattern covering the first region REG1 and the third region REG3 of the substrate 100 and partially exposing the second region REG2 of the substrate 100 may be formed on the second insulating interlayer 180 and the wiring 190, and the first and second insulating interlayers 160 and 180 and the substrate 100 may be etched using the first photoresist pattern as an etching mask to form a second trench. The second trench may be formed through the first and second insulating interlayers 160 and 180 and the portion of the substrate 100.
An insulation layer 200 and a second barrier layer 210 may be sequentially formed on an inner wall of the second trench, and a second conductive layer 220 may be formed on the second barrier layer 210 to sufficiently fill the second trench. The insulation layer 200 may be formed to include an oxide, e.g., silicon oxide or a nitride, e.g., silicon nitride, and the second barrier layer 210 may be formed to include a metal nitride, e.g., titanium nitride, tantalum nitride, tungsten nitride, copper nitride, aluminum nitride, etc. The second conductive layer 220 may be formed to include a metal, e.g., copper, aluminum, tungsten, etc., or doped polysilicon. When the second conductive layer 220 is formed to include copper or aluminum, a second seed layer may be formed on the second barrier layer 210, and the second conductive layer 220 may be formed by an electroplating process.
The second conductive layer 220, the second barrier layer 210 and the insulation layer 200 may be planarized until a top surface of the second insulating interlayer 180 may be exposed to form the via structure 230 filling the second trench. The via structure 230 may include the insulation layer 200, the second barrier layer 210 and the second conductive layer 220.
Referring to
The third insulating interlayer 240 may be formed to include a low-k dielectric material, e.g., silicon oxide doped with fluorine or carbon, a porous silicon oxide, a spin on organic polymer, or an inorganic polymer, e.g., hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc.
The pad structures 260 may be formed by a double damascene process or a single damascene process, like the wiring 190. In an exemplary embodiment of the inventive concept, the pad structure 260 in the second region REG2 may be formed to contact a top surface of the via structure 230. The pad structures 260 may be formed to include a conductive pattern 264 and a barrier layer pattern 262 covering a bottom and a sidewall of the conductive pattern 264.
Referring to
After the bumps SBMP and TMBMP are formed on the third insulating interlayer 240, the fourth insulating interlayer 270 may be formed on the second surface 102 of the substrate 100 and the pad structures 280 may be formed through the fourth insulating interlayer 270 in the second and third regions REG2 and REG3, respectively, in the same way as described with reference to
The substrate 100 may be overturned using a handling substrate so that the second surface 102 of the substrate 100 may face upward. A portion of the substrate 100 adjacent to the second surface 102 may be removed to expose a portion of the via structure 230. Thus, the substrate 100 may be partially removed by, e.g., an etch back process.
The fourth insulating interlayer 270 may be formed to include a low-k dielectric material, e.g., silicon oxide doped with fluorine or carbon, a porous silicon oxide, a spin on organic polymer, or an inorganic polymer, e.g., hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc.
The pad structures 280 may be formed by a double damascene process or a single damascene process, like the wiring 190. In an exemplary embodiment of the inventive concept, the pad structure 280 in the second region REG2 may be formed to contact a bottom surface of the via structure 230. The pad structures 280 may be formed to include a conductive pattern 284 and a barrier layer pattern 282 covering a bottom and a sidewall of the conductive pattern 284.
In comparison with
In an exemplary embodiment of the inventive concept, the bump pads in the bump layer in the upward direction +Z or in the downward direction −Z from the semiconductor die including a heat source may be removed at an area near the heat source.
For example, the bump pads at a first area may be removed as illustrated in
The structure of
In an exemplary embodiment of the inventive concept, the heat block layer HBL may be coated on the top surface and/or the bottom surface of the semiconductor die including the heat source.
For example, as illustrated in
Referring to
In an exemplary embodiment of the inventive concept, a heat conduction line HCL may be formed on a top surface or a bottom surface of the semiconductor die SD1 including the heat source HS such that a first end of the heat conduction line HCL contacts a portion near the heat source HS and a second end of the heat conduction line HCL is far from the heat source HS. The thermal-mechanical bump TMBMP may be removed from the first end of the heat conduction line HCL and the thermal-mechanical bump TMBMP may be disposed at the second end of the heat conduction line HCL.
For example, as illustrated in
Referring to
In an exemplary embodiment of the inventive concept, a heat conduction line HCL may be formed on a top surface or a bottom surface of the semiconductor die SD1 including the heat source HS such that a first end of the heat conduction line HCL contacts a portion near the heat source HS and a second end of the heat conduction line HCL is far from the heat source HS. The thermal-mechanical bump TMBMP may be removed from the first end of the heat conduction line HCL and a bonding wire BW may be disposed at the second end of the heat conduction line HCL.
For example, as illustrated in
Referring to 28, a memory device 400 may include a control logic 410, an address register 420, a bank control logic 430, a row address multiplexer 440, a column address latch 450, a row decoder 460, a column decoder 470, a memory cell array 480, a sense amplifier unit 485, an input/output (I/O) gating circuit 490, a data input/output (I/O) buffer 495 and a refresh counter 445.
The memory cell array 480 may include a plurality of bank arrays 480a˜480h. The row decoder 460 may include a plurality of bank row decoders 460a˜460h respectively coupled to the bank arrays 480a˜480h, the column decoder 470 may include a plurality of bank column decoders 470a˜470h respectively coupled to the bank arrays 480a˜480h, and the sense amplifier unit 485 may include a plurality of bank sense amplifiers 485a˜485h respectively coupled to the bank arrays 480a˜480h.
The address register 420 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from a memory controller. The address register 420 may provide the received bank address BANK_ADDR to the bank control logic 430, may provide the received row address ROW_ADDR to the row address multiplexer 440, and may provide the received column address COL_ADDR to the column address latch 450.
The bank control logic 430 may generate bank control signals in response to the bank address BANK_ADDR. One of the bank row decoders 460a˜460h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of the bank column decoders 470a˜470h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.
The row address multiplexer 440 may receive the row address ROW_ADDR from the address register 420, and may receive a refresh row address REF_ADDR from the refresh counter 445. The row address multiplexer 440 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA that is output from the row address multiplexer 440 may be applied to the first through eighth bank row decoders 460a˜460h.
The activated one of the bank row decoders 460a˜460h may decode the row address RA that is output from the row address multiplexer 440, and may activate a word-line corresponding to the row address RA. For example, the activated bank row decoder may apply a word-line driving voltage to the word-line corresponding to the row address RA.
The column address latch 450 may receive the column address COL_ADDR from the address register 420, and may temporarily store the received column address COL_ADDR. In an exemplary embodiment of the inventive concept, in a burst mode, the column address latch 450 may generate column addresses that increment from the received column address COL_ADDR. The column address latch 450 may apply the temporarily stored or generated column address to the bank column decoders 470a˜470h.
The activated one of the bank column decoders 470a˜470h may decode the column address COL_ADDR that is output from the column address latch 450, and may control the input/output gating circuit 490 to output data corresponding to the column address COL_ADDR.
The I/O gating circuit 490 may include a circuitry for gating input/output data. The I/O gating circuit 490 may further include read data latches for storing data that is output from the bank arrays 480a˜480h, and write drivers for writing data to the bank arrays 480a˜480h.
Data to be read from one bank array of the bank arrays 480a˜480h may be sensed by a sense amplifier coupled to the one bank array from which the data is to be read, and may be stored in the read data latches. The data stored in the read data latches may be provided to the memory controller via the data I/O buffer 495. Data DQ to be written in one bank array of the bank arrays 480a˜480h may be provided to the data I/O buffer 495 from the memory controller. The write driver may write the data DQ in one bank array of the first through eighth bank arrays 480a˜480h.
The control logic 410 may control operations of the memory device 400. For example, the control logic 410 may generate control signals for the memory device 400 to perform a write operation or a read operation. The control logic 410 may include a command decoder 411 that decodes a command CMD received from the memory controller via a buffer chip and a mode register set 412 that sets an operation mode of the memory device 400.
Referring to
In a general technique, the components of the system may be mounted on a board in a package level, or all of the components may be integrated in a single semiconductor die to form a system on chip (SOC). In a system formed with multiple packages, the size of the system may be increased and the signal paths may be lengthened. This, however, may degrade power efficiency and performance of the system. In addition, the SOC has a limit in chip size and high manufacturing cost. In an exemplary embodiment of the inventive concept, the components of the system may be integrated and distributed in the independent semiconductor dies and then the semiconductor dies may be stacked to form the system as illustrated in
In implementing the three-dimensional stack structure of
Referring to
The stacked semiconductor memory chips SMC may be mounted on the module substrate 510 and each of the stacked semiconductor memory chips SMC may include a plurality of semiconductor dies stacked vertically. As described with reference to
The stacked semiconductor memory chips SMC may receive data DQ from an external device such as a memory controller through data buses 512 and 515 in a write mode, or transmit the data DQ to the external device through the data buses 512 and 515 in a read mode.
The buffer chip BC may be mounted on the module substrate 510 and the buffer chip BC may receive command signals CMD, address signals ADD and control signals IN1˜INk through a control bus 511 to provide internal signals ICS1˜ICSr to the stacked semiconductor memory chips SMC through internal buses 513 and 514. The buffer chip BC may include a register REG to store control information of the memory module 501.
Referring to
The first through kth semiconductor integrated circuit layers LA1 through LAk may transmit and receive signals between the layers by through-substrate vias (e.g., through-silicon vias) TSVs. The first semiconductor integrated circuit layer LA1 as the master layer may communicate with an external device (e.g., a memory controller) through a conductive structure formed on an external surface. A description will be made regarding a structure and an operation of the stacked semiconductor memory device 601 by mainly referring to the first semiconductor integrated circuit layer LA1 or 610 as the master layer and the kth semiconductor integrated circuit layer LAk or 620 as the slave layer.
The first semiconductor integrated circuit layer 610 and the kth semiconductor integrated circuit layer 620 may include memory regions 621 and various peripheral circuits 622 for driving the memory regions 621. For example, the peripheral circuits may include a row (X)-driver for driving wordlines of the memory regions 621, a column (Y)-driver for driving bit lines of the memory regions 621, a data input/output unit (Din/Dout) for controlling input/output of data, a command buffer (CMD) for receiving a command CMD from outside and buffering the command CMD, and an address buffer (ADDR) for receiving an address from outside and buffering the address.
The stacked semiconductor memory device 601 may, as described with reference to
Referring to
The first through kth semiconductor integrated circuit layers LA1 through LAk may transmit and receive signals between the layers by through-substrate vias (e.g., through-silicon vias) TSVs. The first semiconductor integrated circuit layer LA1 as the interface layer may communicate with an external memory controller through a conductive structure formed on an external surface. A description will be made regarding a structure and an operation of the stacked semiconductor memory device 602 by mainly using the first semiconductor integrated circuit layer LA1 or 610 as the interface layer and the kth semiconductor integrated circuit layer LAk or 620 as the memory layer.
The first semiconductor integrated circuit layer 610 as the master layer may include various peripheral circuits for driving the memory regions 621 in the kth semiconductor integrated circuit layer 620 as the memory layer. For example, the first semiconductor integrated circuit layer 610 may include a row (X)-driver 6101 for driving wordlines of the memory regions 621, a column (Y)-driver 6102 for driving bit lines of the memory regions 621, a data input/output circuit (Din/Dout) 6103 for controlling the input/output of data, a command buffer (CMD buffer) 6104 for receiving a command CMD from the outside and buffering the command CMD, an address buffer (ADDR buffer) 6105 for receiving an address from the outside and buffering the address and a refresh controller (REFC) 6106.
The first semiconductor integrated circuit layer 610 may further include a control circuit 6107 and the control circuit 6107 may generate control signals to control the memory regions 621 in the kth semiconductor integrated circuit layer 620 based on the command-address signals provided from the memory controller.
The stacked semiconductor memory device 602 may, as described with reference to
Referring to
The memory module 710 may communicate with the memory controller 720 via a system bus. Data DQ, command/address CMD/ADD, a clock signal CLK and control signals IN1˜INk may be transmitted and received between the memory module 710 and the memory controller 720 via the system bus.
Referring to
The base substrate 810 may be a printed circuit board (PCB). External connecting members 820, e.g., package terminals comprised of conductive bumps, may be formed on a lower surface of the base substrate 810. Internal connecting members 830, e.g., chip terminals comprised of conductive bumps, may be formed on a upper surface of the base substrate 810 and between the semiconductor dies SD1˜SDr. In an exemplary embodiment of the inventive concept, the semiconductor dies SD1˜SDr may be connected to each other and to the base substrate 810 by through-substrate vias TSVs 840 and the conductive bumps. In an exemplary embodiment of the inventive concept, the semiconductor dies SD1˜SDr may be connected to the base substrate 810 by bonding wires 850 and the conductive bumps. In an exemplary embodiment of the inventive concept, the semiconductor dies SD1˜SDr may be connected to the base substrate 810 by a combination of the through-substrate vias 840, the conductive bumps, and the bonding wires 850. The stacked semiconductor dies SD1˜SDr may be packaged using the sealing member 860.
According to an exemplary embodiment of the inventive concept, thermal-mechanical bumps 835 not use in the transfer of the electrical signals may be disposed between the semiconductor dies SD1˜SDr. As described with reference to
Referring to
For example, the first subsystem SSYSa and the second subsystem SSYSb may be mounted on an interposer 920 that is mounted on the board 910, and the first subsystem SSYSa and the second subsystem SSYSb may be connected through signal lines or signal paths that are formed at the interposer 920. For example, the fourth subsystem SSYSd may be stacked on the third subsystem SSYSc to form a structure of a package on package (PoP). The interposer 920 and the PoP may be connected through signal bus lines that are formed at the board 910.
At least one of the subsystems SSYSa, SSYSb, SSYSc and SSYSd may be a stacked semiconductor device in which a plurality of semiconductor dies are stacked. As described with reference to
Referring to
The application processor 1210 may execute applications such as a web browser, a game application, a video player, etc. In an exemplary embodiment of the inventive concept, the application processor 1210 may include a single core or multiple cores. For example, the application processor 1210 may be a multi-core processor such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. The application processor 1210 may include an internal or external cache memory.
The connectivity unit 1220 may perform wired or wireless communication with an external device. For example, the connectivity unit 1220 may perform Ethernet communication, near field communication (NFC), radio frequency identification (RFID) communication, mobile telecommunication, memory card communication, universal serial bus (USB) communication, etc. In an exemplary embodiment of the inventive concept, the connectivity unit 1220 may include a baseband chipset that supports communications, such as global system for mobile communications (GSM), general packet radio service (GPRS), wideband code division multiple access (WCDMA), high speed downlink/uplink packet access (HSxPA), etc.
The volatile memory device 1230 may store data processed by the application processor 1210, or may operate as a working memory. For example, the volatile memory device 1230 may be a DRAM, such as double data rate (DDR) synchronous DRAM (SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, rambus DRAM (RDRAM), etc.
The nonvolatile memory device 1240 may store a boot image for booting the mobile system 1200. For example, the nonvolatile memory device 1240 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc.
The user interface 1250 may include at least one input device, such as a keypad, a touch screen, etc., and at least one output device, such as a speaker, a display device, etc. The power supply 1260 may supply a power supply voltage to the mobile system 1200. In an exemplary embodiment of the inventive concept, the mobile system 1200 may further include a camera image processor, a CMOS image sensor (CIS), and/or a storage device, such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a compact disk read only memory (CD-ROM), etc.
In an exemplary embodiment of the inventive concept, the mobile system 1200 and/or components of the mobile system 1200 may be packaged in various forms, such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi-chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP), etc.
At least one of the application processor 1210, the connectivity unit 1220, the volatile memory device 1230, the nonvolatile memory device 1240 and the user interface 1250 may be a stacked semiconductor device in which a plurality of semiconductor dies are stacked. As described with reference to
Referring to
The processor 1310 may perform various computing functions such as executing specific software for performing specific calculations or tasks. For example, the processor 1310 may be a microprocessor, a central processing unit (CPU), a digital signal processor, or the like. In an exemplary embodiment of the inventive concept, the processor 1310 may include a single core or multiple cores. For example, the processor 1310 may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. Although
The processor 1310 may include a memory controller 1311 for controlling operations of the memory module 1340. The memory controller 1311 included in the processor 1310 may be referred to as an integrated memory controller (IMC). A memory interface between the memory controller 1311 and the memory module 1340 may be implemented with a single channel including a plurality of signal lines, or may be implemented with multiple channels, to each of which at least one memory module 1340 may be coupled. In an exemplary embodiment of the inventive concept, the memory controller 1311 may be located inside the input/output hub 1320, which may be referred to as memory controller hub (MCH).
The memory module 1340 may include a plurality of memory devices that store data provided from the memory controller 1311. At least one of the memory devices may be a stacked semiconductor device in which a plurality of semiconductor dies are stacked. As described with reference to
The input/output hub 1320 may manage data transfer between the processor 1310 and other devices, such as the graphics card 1350. The input/output hub 1320 may be coupled to the processor 1310 via various interfaces. For example, the interface between the processor 1310 and the input/output hub 1320 may be a front side bus (FSB), a system bus, a HyperTransport, a lightning data transport (LDT), a QuickPath interconnect (QPI), a common system interface (CSI), etc. Although
The graphics card 1350 may be coupled to the input/output hub 1320 via AGP or PCIe. The graphics card 1350 may control a display device for displaying an image. The graphics card 1350 may include an internal processor for processing image data and an internal memory device. In an exemplary embodiment of the inventive concept, the input/output hub 1320 may include an internal graphics device along with or instead of the graphics card 1350 outside the graphics card 1350. The graphics device included in the input/output hub 1320 may be referred to as integrated graphics. Further, the input/output hub 1320 including the internal memory controller and the internal graphics device may be referred to as a graphics and memory controller hub (GMCH).
The input/output controller hub 1330 may perform data buffering and interface arbitration to efficiently operate various system interfaces. The input/output controller hub 1330 may be coupled to the input/output hub 1320 via an internal bus, such as a direct media interface (DMI), a hub interface, an enterprise Southbridge interface (ESI), PCIe, etc. The input/output controller hub 1330 may provide various interfaces with peripheral devices. For example, the input/output controller hub 1330 may provide a universal serial bus (USB) port, a serial advanced technology attachment (SATA) port, a general purpose input/output (GPIO), a low pin count (LPC) bus, a serial peripheral interface (SPI), PCI, PCIe, etc.
In an exemplary embodiment of the inventive concept, the processor 1310, the input/output hub 1320 and the input/output controller hub 1330 may be implemented as separate chipsets or separate integrated units. In an exemplary embodiment of the inventive concept, at least two of the processor 1310, the input/output hub 1320 and the input/output controller hub 1330 may be implemented as a single chipset. In addition, while many features of the exemplary embodiments are disclosed as units, in other embodiments those features may be implemented as other forms of logic including but not limited to code-based operations performed by a processor.
As described above, a stacked semiconductor device and a method of manufacturing the stacked semiconductor device according to exemplary embodiments of the inventive concept may efficiently dissipate an excessive amount of heat from a heat source by changing the disposition or the structure of thermal-mechanical bumps in view of the location of the heat source. The thermal characteristics of the stacked semiconductor device may be optimized by the dissipation of the excessive amount of heat, and thus, performance and productivity of the stacked semiconductor device may be increased.
Exemplary embodiments of the inventive concept may be applied to various devices and systems. For example, the inventive concept may be applied to systems such as a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc.
While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2015-0172996 | Dec 2015 | KR | national |
