Patent Application
20160005705
Embodiments of the invention are related in general to the field of semiconductor devices and processes, and more specifically to the structure and fabrication method of batch-packaging low pin count embedded semiconductor chips.
It is common practice to manufacture the active and passive components of semiconductor devices into round wafers sliced from elongated cylinder-shaped single crystals of semiconductor elements or compounds. The diameter of these solid state wafers may reach up to 12 inches. Individual devices are then typically singulated from the round wafers by sawing streets in x- and y-directions through the wafer in order to create rectangularly shaped discrete pieces from the wafers; commonly, these pieces are referred to as die or chips. Each chip includes at least one device coupled with respective metallic contact pads. Semiconductor devices include many large families of electronic components; examples are active devices such as diodes and transistors like field-effect transistors, passive devices such as resistors and capacitors, and integrated circuits with sometimes far more than a million active and passive components.
After singulation, one or more chips are attached to a discrete supporting substrate such as a metal leadframe or a rigid multi-level substrate laminated from a plurality of metallic and insulating layers. The conductive traces of the leadframes and substrates are then connected to the chip contact pads, typically using bonding wires or metal bumps such as solder balls. For reasons of protection against environmental and handling hazards, the assembled chips may be encapsulated in discrete robust packages, which frequently employ hardened polymeric compounds and are formed by techniques such as transfer molding. The assembly and packaging processes are usually performed either on an individual basis or in small groupings such as a strip of leadframe or a loading of a mold press.
In order to increase productivity by a quantum jump and reduce fabrication cost, technical efforts have recently been initiated to re-think certain assembly and packaging processes with the goal to increase the volume handled by each batch process step. These efforts are generally summarized under the title panelization. As an example, adaptive patterning methods have been described for fabricating panel-based package structures. Other technical efforts are directed to keep emerging problems such as panel warpage under control.
Applicant realized that successful methods and process flows for large-scale panels from sets of few contiguous chips to sets of larger numbers of contiguous chips, as intended for semiconductor packaging, have to resolve key technical challenges. Among these challenges are achieving planarity of panels and avoiding warpage and mechanical instability, extending the spacing of contact pads for easy connection to external parts, achieving low resistance connections and reaching high reliability backside chip connects, avoiding expensive laser process steps, especially through metal layers and epoxy layers, and improved thermal characteristics. For metallic seed layers, uniformity of the layers across the selected panel size should be achieved, yet electroless plating technology should be avoided.
Applicant solved the challenges when he discovered a process flow for a whole set of chips to embed the chips in the packages. The method uses adhesive tapes instead of epoxy chip attach procedures, re-usable carriers, and a sputtering methodology for replacing electroless plating. Furthermore, the new process technology is free of the need to use lasers. As a result, the new process flow preserves clean chip contact pads and processes a set of four chips concurrently, thus greatly increasing productivity. In addition, the packaged devices offer improved reliability. A key contributor to the enhanced reliability is reduced thermo-mechanical stress achieved by laminating gaps with insulating fillers having high modulus and a glass transition temperature for a coefficient of thermal expansion approaching the coefficient of silicon.
Applicant developed a sputtering technology with plasma-cleaned an cooled panels, which produces uniform sputtered metal layers across a panel and thus avoids the need for electroless plating. Since the sputtering procedure also serves to clean and roughen the substrate surface, the sputtered layers adhere equally well to dielectrics, silicon, and metals; they may be employed as connective traces, or may serve as seed layers for subsequent electro-plated metal layers.
One embodiment based on the modified processes can be applied to a set of contiguous chips with small numbers of terminals; it is a technical advantage that another embodiment lends itself to a plurality of sets of semiconductor chips. Many modified flows are applicable to any transistor or integrated circuit; other modified flows are particularly suitable for higher numbers of terminals. It is another technical advantage that some of the packaged devices offer flexibility with regard to the connection to external parts: they can be finished to be suitable as devices with land grid arrays, or as ball grid arrays, or as and QFN (Quad Flat No-Lead) terminals.
An embodiment of the invention is a method for fabricating packaged semiconductor devices in panel format, certain processes of which are illustrated in
The capability to process a set of four semiconductor chips as a single batch, enhances the productivity of the involved process steps fourfold.
In the process step of
In the next process step, depicted in
During the processes summarized in
Preferably, the step of sputtering includes the sputtering of a first layer of a metal selected from a group including titanium, tungsten, tantalum, zirconium, chromium, molybdenum, and alloys thereof, wherein the first layer is adhering to chip and lamination surfaces; and without delay sputtering at least one second layer of a metal selected from a group including copper, silver, gold, and alloys thereof, onto the first layer, wherein the second layer is adhering to the first layer. The sputtered layers have the uniformity, strong adhesion, and low resistivity needed to serve, after patterning, as conductive traces for rerouting, see
In an optional step, at least one layer of metal is electroplated onto the sputtered layers 540. A preferred metal is copper. The plated layer is preferably thicker than the sputtered metal to lower the sheet resistance and thus the resistivity of the rerouting traces after patterning the plated and sputtered metal layers. The steps of patterning the sputtered and plated metal layers in order to create connecting traces between the bumps and enlarged package contact pads are preferably executed with a laser direct-imaging technology. The laser direct-imaging technology uses an out-alignment correcting technique.
In another optional step, one or more layers of solderable metal, such as tin, tin alloy, nickel followed by palladium, may be deposited.
The result of the metal layer patterning for rerouting and enlarged contact pads is illustrated in
In addition, it is preferred, as shown in
In the next process step, the temperature is raised so that the temperature-sensitive first adhesive of layer 110 allows to remove panel 110 (substrate 101 and tape 102) from the assembly of packaged chip set.
The next process step, illustrated in
Another embodiment is an exemplary packaged semiconductor device 700. The device has a semiconductor chip 701 with a first surface 701a and a parallel second surface 701b. First surface 701 a has a plurality of terminals 710 with metal bumps such as copper pillars or copper squashed balls.
Device 700 has a frame of insulating material 730 adhering to at least one sidewall of the chip. The insulating material of the frame includes glass fibers impregnated with a gluey resin, which has a high modulus and a coefficient of thermal expansion (CTE) close to the CTE of silicon. Frame 730 has a first surface 730a planar with the insulating material between the bumps 710, and a parallel second surface 730b planar with the second chip surface 701b.
Device 700 further has at least one film 740 of sputtered metal extending from the bumps 710 across the surface 730a of the layer of insulating material close to the edge of the insulating frame. Film 740 is patterned to form extended contact pads 610 over the frame, and, wherever necessary, rerouting traces between the chip bumps 710 and the extended contact pads 610. Since film 740 has been created by sputtering, it is adhering to all the surfaces mentioned.
Dependent on the size, contour, and metallurgical configuration of the extended contact pads 610, they can be employed as ball grid array terminals, land grid array terminals, and QFN-type terminals.
While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description.
As an example, dependent on the size of the chip and the package, enough area can be utilized to lay out the redistributed contact pads for a considerably higher number of terminals than the eight contact pads discussed. As another example, for a set of four chips the configuration of chips as well as packages may be rectangular instead of square; the layout of the redistributed contact pads can be accommodated.
It is therefore intended that the appended claims encompass any such modifications or embodiments.
