Patent Application
20170243803
The present invention relates to a semiconductor assembly and, more particularly, to a thermally enhanced semiconductor assembly with three dimensional integration in which a semiconductor chip is wire bonded to and thermally conductible to a wiring board having a heat spreader integrated with dual wiring structures, and a method of making the same.
Market trends of multimedia devices demand for faster and slimmer designs. However, as semiconductor devices are susceptible to performance degradation at high operational temperatures, assembling chips having stackable features for three-dimensional integration without proper heat dissipation measurements would worsen devices' thermal environment and may cause immediate failure during operation.
U.S. Pat. Nos. 8,132,320, 8,373,997, 8,400,776, 8,519,270, 8,530,751, 8,735,739, 8,850,701, 8,895,380, 8,942,003, 9,085,826, 9,159,713, 9,282,626, 9,340,003, 9,439,282 and 9,549,468 disclose various assembly structures having a cavity in the wiring board for slimmer or stackable considerations. However, as a dielectric layer is typically a thermally insulating material, circuitry disposed therein can only provide limited heat dissipation effect. Further, even if thermal vias are disposed in the board and underneath the cavity, the hot spot of a semiconductor chip may not be aligned with these thermal vias and render poor heat spreading efficiency.
Numerous attempts have been reported in the literature by inserting a metal or ceramic slug directly in the wiring board to compensate for this deficiency. However, this approach creates serious mechanical-related deficiencies. For example, wiring boards and their assemblies disclosed by U.S. Pat. Nos. 5,583,377, 6,861,750, 7,202,559, 7,462,933, 7,554,194, 7,919,853, 7,944,043, 7,968,371, 8,125,076, 8,188,379, 8,519,537, and 8,686,558 may render reliability and mechanical degradation problems. This is largely due to the heat sink disposed in the through opening is barely supported by the wiring board through flanges or adhesives, thermal expansion and shrinkage of the wiring board during operation would cause heat sink dislocation or distortion. Further, as the heat sink in the wiring board is often electrically and thermally isolated and its planar dimension is confined by the size of the through opening, the electrical and thermal performances of the assemblies are significantly limited.
For the reasons stated above, and for other reasons stated below, an urgent need exists to provide a three dimensional semiconductor assembly that can address high packaging density, high thermal dissipation and robust mechanical reliability requirements.
The objective of the present invention is to provide a thermally enhanced semiconductor assembly in which one or more semiconductor chips can be electrically connected to a wiring board through a plurality of bonding wires and at least one chip is thermally conductible to a heat spreader provided in the wiring board. The heat spreader is disposed in a through opening of a wiring structure and mechanically supported by, electrically connected with, and thermally dissipated through another wiring structure, thereby improving mechanical, thermal and electrical performances of the assembly.
In accordance with the foregoing and other objectives, the present invention provides a thermally enhanced semiconductor assembly having a first semiconductor chip electrically connected to a wiring board through bonding wires. The wiring board includes a heat spreader, a first wiring structure and a second wiring structure. In a preferred embodiment, the first semiconductor chip is attached on and thermally conductible to the heat spreader; the first wiring structure laterally surrounds peripheral edges of the heat spreader and the first semiconductor chip, and is electrically coupled to the first semiconductor chip by bonding wires to provide fan-out routing; and the second wiring structure covers the first wiring structure and the heat spreader to provide mechanically support, and is thermally conductible to the heat spreader and electrically coupled to the first wiring structure.
Accordingly, the present invention provides a method of making a thermally enhanced semiconductor assembly with three dimensional integration, comprising: providing a wiring board, that includes (i) inserting a heat spreader into a through opening of a first wiring structure, with a backside surface of the heat spreader being substantially coplanar with a first surface of the first wiring structure, and (ii) forming a second wiring structure on the backside surface of the heat spreader and the first surface of the first wiring structure, wherein the second wiring structure is electrically coupled to the first wiring structure and thermally conductible to the heat spreader through metallized vias; disposing a first semiconductor chip in the through opening of the first wiring structure and over the heat spreader; and providing a plurality of bonding wires that electrically couple the first semiconductor chip to a second surface of the first wiring structure opposite to the first surface.
Unless specifically indicated or using the term “then” between steps, or steps necessarily occurring in a certain order, the sequence of the above-mentioned steps is not limited to that set forth above and may be changed or reordered according to desired design.
The semiconductor assembly and the method of making the same according to the present invention have numerous advantages. For instance, inserting the heat spreader in the through opening of the first wiring structure and forming the second wiring structure on the heat spreader and the first wiring structure is particularly advantageous as the heat spreader provided in the through opening of the first wiring structure can be mechanically supported by and thermally dissipated through the second wiring structure to enhance heat dissipation for the first semiconductor chip and mechanical reliability of the assembly. Inserting the first semiconductor chip into the through opening of the first wiring structure of the wiring board can provide mechanical housing for the first semiconductor chip and place the first semiconductor chip on the heat spreader for effective thermal dissipation. Additionally, attaching the bonding wires to the first semiconductor chip and the wiring board can offer a reliable channel for connecting the first semiconductor chip in a cavity of the wiring board to terminal pads provided in the wiring board.
These and other features and advantages of the present invention will be further described and more readily apparent from the detailed description of the preferred embodiments which follows.
The following detailed description of the preferred embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which:
Hereafter, examples will be provided to illustrate the embodiments of the present invention. Advantages and effects of the invention will become more apparent from the following description of the present invention. It should be noted that these accompanying figures are simplified and illustrative. The quantity, shape and size of components shown in the figures may be modified according to practical conditions, and the arrangement of components may be more complex. Other various aspects also may be practiced or applied in the invention, and various modifications and variations can be made without departing from the spirit of the invention based on various concepts and applications.
At this stage, a wiring board 10 is accomplished and includes a first wiring structure 11, a heat spreader 15 and a second wiring structure 16. As the depth of the through opening 115 is more than the thickness of the heat spreader 15, the exterior surface of the heat spreader 15 and the sidewall surface of the through opening 115 of the first wiring structure 11 forms a cavity 116 in the through opening 115 of the first wiring structure 11. As a result, the heat spreader 15 can provide thermal dissipation for a device accommodated in the cavity 116, whereas the combination of the first wiring structure 11 and the second wiring structure 16 offers electrical contacts for next connection from two opposite sides of the wiring board 10.
Accordingly, as shown in
The heat spreader 15 of the wiring board 10 is thermally conductible to and covers the first semiconductor chip 22 from below. The first wiring structure 11 laterally surrounds peripheral edges of the first semiconductor chip 22 and the heat spreader 15, and is electrically coupled to the first semiconductor chip 22 by the bonding wires 31. The second wiring structure 16 covers the first wiring structure 11 and the heat spreader 15 from below, and is electrically coupled to the first wiring structure 11 and thermally conductible to the heat spreader 15 through metallized vias 164. As a result, the first wiring structure 11 and the second wiring structure 16 can provide fan-out routing for the first semiconductor chip 22.
For purposes of brevity, any description in Embodiment 1 above is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
Accordingly, as shown in
The heat spreader 15 covers the inactive surface of the first semiconductor chip 22 and is thermally conductible to the first semiconductor chip 22, whereas the metal layer 17 surrounds peripheral edges of the first semiconductor chip 22 and contacts the heat spreader 15. The first wiring structure 11 is electrically coupled to the first semiconductor chip 22 through bonding wires 31. The second wiring structure 16 covers the first wiring structure 11 and the heat spreader 15 from below, and is electrically coupled to the first wiring structure 11 for signal routing and to the heat spreader 15 for ground connection through metallized vias 164. Accordingly, the combination of the first wiring structure 11 and the second wiring structure 16 can provide fan-out routing for the first semiconductor chip 22 and electrical contacts for next-level connection, whereas the combination of the heat spreader 15 and the metal layer 17, electrically connected to the second wiring structure 16 through metallized vias 164, provides thermal dissipation and EMI (electromagnetic interference) shielding for the first semiconductor chip 22.
For purposes of brevity, any description in Embodiments above is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
The semiconductor assembly 410 is similar to that illustrated in
The semiconductor assembly 510 is similar to that illustrated in
The semiconductor assembly 610 is similar to that illustrated in
The semiconductor assemblies described above are merely exemplary. Numerous other embodiments are contemplated. In addition, the embodiments described above can be mixed-and-matched with one another and with other embodiments depending on design and reliability considerations. For instance, the first wiring structure may have multiple through openings in an array and each first semiconductor chip is accommodated in its corresponding through opening. Also, the first wiring structure of the wiring board can include additional conductive traces to receive and route additional first semiconductor chips.
For the convenience of below description, the direction in which the first surface of the first wiring structure faces is defined as the first direction, and the direction in which the second surface of the first wiring structure faces is defined as the second direction.
As illustrated in the aforementioned embodiments, a distinctive semiconductor assembly is configured by providing a first wiring structure, then inserting a heat spreader into a through opening of the first wiring structure, and then forming a second wiring structure on the heat spreader and the first wiring structure. Accordingly, the semiconductor assembly includes a first semiconductor chip electrically coupled to a wiring board by bonding wires. The wiring board includes a heat spreader, a first wiring structure and a second wiring structure. The first wiring structure includes electrical contacts at its second surface for chip connection and next-level connection from the second direction, whereas the second wiring structure includes electrical contacts at its exterior surface for next-level connection from the first direction. The heat spreader is laterally surrounded by the first wiring structure and covered by the second wiring structure from the first direction, and can provide a thermal dissipation pathway for the first semiconductor chip. Additionally, a second semiconductor chip may be stacked over first semiconductor chip by an adhesive and electrically coupled to the first wiring structure by a plurality of additional bonding wires. Optionally, an encapsulant may be further provided to cover the bonding wires.
The first wiring structure has a through opening extending from its first surface to its second surface to accommodate the heat spreader and the first semiconductor chip therein. The first wiring structure is not limited to a particular structure, and may be a multi-layered routing circuitry that laterally surround peripheral edges of the first semiconductor chip and the heat spreader. For instance, the first wiring structure may include an interconnect substrate, a first buildup circuitry and a second buildup circuitry. The first and second buildup circuitries are disposed on both opposite sides of the interconnect substrate. The interconnect substrate can include a core layer, first and second routing layers respectively on both opposite sides of the core layer, and metallized through vias formed through the core layer to provide electrical connection between the first and second routing layers. Each of the first and second buildup circuitries typically includes a dielectric layer and one or more conductive traces. The dielectric layers of the first and second buildup circuitries are respectively deposited on opposite sides of the interconnect substrate. The conductive traces extend laterally on the dielectric layer and include conductive vias in contact with first and second routing layers of the interconnect substrate. Further, the first and second buildup circuitries can include additional dielectric layers, additional via openings, and additional conductive traces if needed for further signal routing. Accordingly, the outmost conductive traces at both the first and second surfaces of the first wiring structure can provide electrical contacts for the chip connection and next-level connection from its second surface and for the second wiring structure connection from its first surface, and are electrically connected to each other.
The heat spreader is disposed in the through opening of the first wiring structure and has a thickness less than that of the first wiring structure so that a cavity is formed in the wiring board to accommodate the first semiconductor chip therein. Further, the heat spreader has peripheral edges adjacent to and attached to sidewalls of the through opening of the first wiring structure, and thus no electrical contacts are provided at the bottom of the cavity. In a preferred embodiment, the heat spreader is a metal layer that completely covers an inactive surface of the first semiconductor chip from the first direction to provide effective thermal dissipation and vertical EMI shielding for the first semiconductor chip attached thereto using a thermally conductive material. Further, the cavity may have metallic sidewalls by forming a metal layer that covers sidewalls of the through opening of the first wiring structure and is electrically coupled to the second wiring structure by the metallized vias in contact with the backside surface of the heat spreader. Preferably, the metal layer contacts sidewalls of the through opening of the first wiring structure, and completely covers sidewalls of the first semiconductor chip to provide effective lateral EMI shielding for the first semiconductor chip.
The second wiring structure may be a multi-layered routing circuitry and laterally extends to peripheral edges of the first wiring structure. Preferably, the second wiring structure is formed by direct build-up process on the first wiring structure and the heat spreader and electrically coupled to the heat spreader and the first wiring structure by metallized vias embedded in a dielectric layer of the second wiring structure and in contact with the backside surface of the heat spreader and the first surface of the first wiring structure. More specifically, the second wiring structure can be a multi-layered buildup circuitry without a core layer, and includes dielectric layers and conductive traces in repetition and alternate fashion. The innermost dielectric layer covers the backside surface of the heat spreader and the first surface of the first wiring structure. The conductive traces include metallized vias in the dielectric layer and extend laterally on the dielectric layer. Accordingly, the heat spreader, covered by the dielectric layer of the second wiring structure from the first direction, can be mechanically supported by the second wiring structure and electrically coupled to the second wiring structure by the metallized vias for ground connection.
The outmost conductive traces of the first and second wiring structures can respectively accommodate conductive joints, such as solder balls or bonding wires, for electrical communication and mechanical attachment with an assembly, an electronic device, an additional heat spreader or others. For instance, a semiconductor device may be a semiconductor chip and mounted over and electrically coupled to the second wiring structure through a plurality of bonding wires, or be a ball grid array package or a bumped chip and mounted over and electrically coupled to the first wiring structure or the second wiring structure through a plurality of solder balls. For the aspect of the semiconductor device being flip-chip mounted on the second wiring structure, an additional heat spreader may be mounted over the second wiring structure, and the semiconductor device can be disposed in a cavity of the additional heat spreader and thermally conductible to the additional heat spreader through a thermally conductive material. Further, the additional heat spreader may be electrically coupled to the second wiring structure for ground connection by, for example, solder balls in contact with the additional heat spreader and the outmost conductive traces of the second wiring structure. Additionally, when the first semiconductor chip or/and the optional second semiconductor chip is an optical chip, a lens optically transparent to at least one range of light wavelengths may be stacked over the first semiconductor chip and the optional second semiconductor chip, and mounted on the first wiring structure of the wiring board.
The bonding wires provide electrical connections between the first semiconductor chip and the first wiring structure and between the optional second semiconductor chip and the first wiring structure. In a preferred embodiment, the bonding wires contact and are attached to an active surface of the first/second semiconductor chip exposed from the through opening of the first wiring structure and the second surface of the first wiring structure. As a result, the first semiconductor chip and the optional second semiconductor chip can be electrically connected to the wiring board for external connection through the bonding wires.
Optionally, an array of vertical connecting elements may be further provided in electrical connection with the wiring board for next-level connection. Preferably, the vertical connecting elements contact and are electrically coupled to the first wiring structure from the second surface of the first wiring structure. The vertical connecting elements can include metal posts, solder balls or others, and may be laterally covered by an encapsulant. As the vertical connecting elements have a selected portion not covered by the encapsulant, a semiconductor device can be further provided to be electrically coupled to the vertical connecting elements.
The term “cover” refers to incomplete or complete coverage in a vertical and/or lateral direction. For instance, in a preferred embodiment, the heat spreader covers the first semiconductor chip in the first direction regardless of whether another element such as the thermally conductive material is between the first semiconductor chip and the heat spreader.
The phrases “attached to”, “attached on”, “mounted to” and “mounted on” includes contact and non-contact with a single or multiple element(s). For instance, in a preferred embodiment, the peripheral edges of the heat spreader are attached to the sidewalls of the through opening regardless of whether the peripheral edges of the heat spreader contact the sidewalls of the through opening or are separated from the sidewalls of the through opening by an adhesive.
The phrases “electrical connection”, “electrically connected” and “electrically coupled” refer to direct and indirect electrical connection. For instance, in a preferred embodiment, the bonding wires directly contact and are electrically connected to the first wiring structure, and the first semiconductor chip is spaced from and electrically connected to the first wiring structure by the bonding wires.
The “first direction” and “second direction” do not depend on the orientation of the semiconductor assembly, as will be readily apparent to those skilled in the art. For instance, the first surface of the first wiring structure faces the first direction and the second surface of the first wiring structure faces the second direction regardless of whether the semiconductor assembly is inverted. Thus, the first and second directions are opposite one another and orthogonal to the lateral directions. Furthermore, the first direction is the upward direction and the second direction is the downward direction when the outer surface of the second wiring structure faces in the upward direction, and the first direction is the downward direction and the second direction is the upward direction when the outer surface of the second wiring structure faces in the downward direction.
The semiconductor assembly according to the present invention has numerous advantages. For instance, as the first semiconductor chip is connected to the first wiring structure of the wiring board by bonding wires, not by direct build-up process, the simplified process steps result in lower manufacturing cost. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier for the first semiconductor chip. The second wiring structure can provide mechanical support for the heat spreader and dissipate heat from the heat spreader. The semiconductor assembly made by this method is reliable, inexpensive and well-suited for high volume manufacture.
The manufacturing process is highly versatile and permits a wide variety of mature electrical and mechanical connection technologies to be used in a unique and improved manner. The manufacturing process can also be performed without expensive tooling. As a result, the manufacturing process significantly enhances throughput, yield, performance and cost effectiveness compared to conventional techniques.
The embodiments described herein are exemplary and may simplify or omit elements or steps well-known to those skilled in the art to prevent obscuring the present invention. Likewise, the drawings may omit duplicative or unnecessary elements and reference labels to improve clarity.
This application is a continuation-in-part of U.S. application Ser. No. 15/462,536 filed Mar. 17, 2017 and a continuation-in-part of U.S. application Ser. No. 15/473,629 filed Mar. 30, 2017. The U.S. application Ser. No. 15/462,536 is a continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016, continuation-in-part of U.S. application Ser. No. 15/289,126 filed Oct. 8, 2016 and continuation-in-part of U.S. application Ser. No. 15/353,537 filed Nov. 16, 2016. The U.S. application Ser. No. 15/473,629 is a continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016, continuation-in-part of U.S. application Ser. No. 15/289,126 filed Oct. 8, 2016, continuation-in-part of U.S. application Ser. No. 15/353,537 filed Nov. 16, 2016, a continuation-in-part of U.S. application Ser. No. 15/415,844 filed Jan. 25, 2017, a continuation-in-part of U.S. application Ser. No. 15/415,846 filed Jan. 25, 2017 and a continuation-in-part of U.S. application Ser. No. 15/462,536 filed Mar. 17, 2017. The U.S. application Ser. No. 15/166,185 claims the priority benefit of U.S. Provisional Application Ser. No. 62/166,771 filed May 27, 2015. The U.S. application Ser. No. 15/289,126 is a continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016. The U.S. application Ser. No. 15/353,537 is a continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016 and a continuation-in-part of U.S. application Ser. No. 15/289,126 filed Oct. 8, 2016. The U.S. application Ser. Nos. 15/415,844 and 15/415,846 are continuation-in-part of U.S. application Ser. No. 15/166,185 filed May 26, 2016, continuation-in-part of U.S. application Ser. No. 15/289,126 filed Oct. 8, 2016 and continuation-in-part of U.S. application Ser. No. 15/353,537 filed Nov. 16, 2016. The entirety of each of said Applications is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62166771 | May 2015 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15462536 | Mar 2017 | US |
| Child | 15591957 | US | |
| Parent | 15473629 | Mar 2017 | US |
| Child | 15462536 | US | |
| Parent | 15353537 | Nov 2016 | US |
| Child | 15473629 | US | |
| Parent | 15415844 | Jan 2017 | US |
| Child | 15353537 | US | |
| Parent | 15415846 | Jan 2017 | US |
| Child | 15415844 | US | |
| Parent | 15462536 | Mar 2017 | US |
| Child | 15415846 | US | |
| Parent | 15166185 | May 2016 | US |
| Child | 15462536 | US | |
| Parent | 15289126 | Oct 2016 | US |
| Child | 15166185 | US | |
| Parent | 15166185 | May 2016 | US |
| Child | 15353537 | US | |
| Parent | 15289126 | Oct 2016 | US |
| Child | 15166185 | US | |
| Parent | 15166185 | May 2016 | US |
| Child | 15415844 | US | |
| Parent | 15289126 | Oct 2016 | US |
| Child | 15166185 | US | |
| Parent | 15353537 | Nov 2016 | US |
| Child | 15289126 | US | |
| Parent | 15166185 | May 2016 | US |
| Child | 15415846 | US | |
| Parent | 15289126 | Oct 2016 | US |
| Child | 15166185 | US | |
| Parent | 15353537 | Nov 2016 | US |
| Child | 15289126 | US | |
| Parent | 15166185 | May 2016 | US |
| Child | 15462536 | US | |
| Parent | 15289126 | Oct 2016 | US |
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| Parent | 15353537 | Nov 2016 | US |
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| Parent | 15166185 | May 2016 | US |
| Child | 15289126 | US |
