Thermally enhanced semiconductor package and method of producing the same

Abstract

This invention includes a heat sink structure for use in a semiconductor package that includes a ring structure with down sets and a heat sink connected to the ring structure. The down sets can be slanted or V-shaped. The invention also includes a method of manufacturing a semiconductor package that includes inserting a substrate with an attached semiconductor chip in a first mold portion, placing a heat sink structure on top of a portion of the substrate, placing a mold release film onto a second mold portion, clamping a second mold portion onto a portion of the heat sink structure, injecting an encapsulant into a mold cavity, wherein the encapsulant surrounds portions of the substrate, semiconductor chip and heat sink structure, curing the encapsulant, whereby the heat sink structure adheres to the encapsulant and singulating the encapsulated assembly to form a semiconductor package.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 illustrates a conventional method of producing the thermally enhanced semiconductor package.

FIG. 2 illustrates another conventional method of producing a thermally enhanced semiconductor package.

FIGS. 3-9 illustrate a method according to the present invention of producing a thermally enhanced semiconductor package.

FIG. 10 illustrates an embodiment of a thermally enhanced semiconductor package.

FIGS. 11-12 illustrate another method according to the present invention of producing a thermally enhanced semiconductor package.

FIGS. 13 and 14 show top views of 2×2 array and 3×3 array of heat sinks.

FIG. 15 shows a partial plan view of a heat sink frame carrier.

FIG. 16 shows a flash free molded package with a heat sink 203.

FIG. 17 shows a completely assembled thermally enhanced semiconductor package with an embedded heat sink.

FIG. 18 shows an example of a mold release film being forced up against the top mold portion by a vacuum and conforming to the mold cavity.

FIGS. 19 and 20 show cross-sectional views of 2×2 and 3×3 array heat sinks.

FIGS. 21 and 22 show an assembly concept of a QFN package with an integrated heat sink.

Claims

1. A heat sink structure for use in a semiconductor package comprising: a ring structure with down sets; anda heat sink connected to said ring structure.

2. The heat sink structure of claim 1 wherein said down sets are slanted.

3. The heat sink structure of claim 1 wherein said down sets are V-shaped.

4. The heat sink structure of claim 1 wherein the heat sink structure comprises a plurality of heat sinks.

5. The heat sink structure of claim 4 wherein the plurality of heat sinks are arranged in an array.

6. The heat sink structure of claim 5 further comprising a plurality of heat sink arrays.

7. The heat sink structure of claim 1 wherein the heat sink is connected to the ring structure by etched tie bars.

8. The heat sink structure of claim 1 further comprising alignment elements.

9. The heat sink structure of claim 8, wherein the alignment elements are holes.

10. A method of manufacturing a semiconductor package comprising: inserting a substrate with an attached semiconductor chip in a first mold portion;placing a heat sink structure on top of a portion of the substrate;placing a mold release film onto a second mold portion;clamping the second mold portion onto a portion of the heat sink structure;injecting an encapsulant into a mold cavity formed by the first and second mold portions, wherein the encapsulant surrounds portions of the substrate, semiconductor chip and heat sink structure;curing the encapsulant, whereby the heat sink structure adheres to the encapsulant;removing the encapsulated assembly from the mold;singulating the encapsulated assembly to form a semiconductor package.

11. The method of claim 10 wherein a vacuum is used to force the mold release film onto the second mold portion.

12. The method of claim 10 wherein the substrate with attached semiconductor chip and heat sink structure are aligning in the first mold portion.

13. The method of claim 12 wherein the substrate and heat sink structure are aligned through the use of guide pins.

14. The method of claim 10 wherein the heat sink structure comprises a ring structure and a heat sink.

15. The method of claim 14 wherein the heat sink is connected to the ring structure by etched tie bars.

16. The method of claim 15 wherein the encapsulated package is singulated through an etched tie bar.

17. The method of claim 10 wherein the heat sink structure comprises down sets.

18. The method of claim 17 wherein said down sets comprise slanted elements.

19. The method of claim 17 wherein said down sets are V-shaped.

20. The method of claim 17 wherein said down sets create a lifting force when the encapsulant is injected in the mold cavity.

21. The method of claim 17 wherein the encapsulated package is singulated through a down-set.

22. The method of claim 10 wherein heat sink structure comprises down sets that provide a cushioning effect and keep a heat sink on said heat sink structure engaged with said mold release film while said encapsulant is being injected in to the mold cavity.

23. The method of claim 10 wherein said substrate has a plurality of attached semiconductor chips.

24. The method of claim 10 wherein the heat sink structure comprises a ring structure with a plurality of heat sinks.

25. The method of claim 24 wherein the plurality of heat sinks are arranged in an array.

26. The method of claim 25 wherein the heat sink structure comprising a plurality of heat sink arrays.

27. The method of claim 10 wherein the semiconductor package is a ball grid array package.

28. The method of claim 10 wherein the semiconductor package is a quad flat nonleaded package.

29. The method of claim 10 wherein the semiconductor package is a multi chip module package.

30. The method of claim 10 further comprising attaching a high temperature tape on a bottom portion of the substrate.

31. The method of claim 30 wherein the high temperature tape fits into a relief slot in the first mold portion.

32. The method of claim 10 further comprising attaching solder balls to the substrate.

33. A semiconductor package comprising: a semiconductor chip attached to a substrate;an encapsulant covering portions of the semiconductor chip and substrate and comprising a top surface; anda heat sink in direct contact with the entire top surface of the encapsulant;wherein the heat sink becomes adhered to the top surface of the encapsulant as the encapsulant cures;wherein a notch at a top corner of semiconductor package is filled with the encapsulant' andwherein notch acts as an interlock for the heat sink.

34. The package of claim 33, wherein said notch is defined by a side of the heat sink and a down-set.

35. The package of claim 33, wherein said notch is defined by a side of the heat sink and a tie bar.

36. The package of claim 33, further comprising solder balls connected to the substrate.

37. The package of claim 33, wherein the semiconductor chip is wire bonded to the substrate.

38. The package of claim 33, wherein the substrate is a laminate structure.

39. The package of claim 33, wherein the substrate is a metal lead-frame structure.

40. The package of claim 33, wherein the semiconductor package is a ball grid array package.

41. The package of claim 33, wherein the semiconductor package is a quad flat nonleaded package.

42. The package of claim 33, wherein the semiconductor package is a multi chip module package.