Patent Application
20240170393
This application relates to the field of semiconductor technology and, specifically, to a three-dimensional (3D) memory device and fabrication method thereof.
Not-AND (NAND) memory is a non-volatile type of memory that does not require power to retain stored data. The growing demands of consumer electronics, cloud computing, and big data bring about a constant need of NAND memories of larger capacity and better performance. As conventional two-dimensional (2D) NAND memory approaches its physical limits, three-dimensional (3D) NAND memory is now playing an important role. 3D NAND memory uses multiple stack layers on a single die to achieve higher density, higher capacity, faster performance, lower power consumption, and better cost efficiency.
A staircase contact (SCT) is a structure used to contact a word line in some NAND memory devices. Improvements of the process to fabricate SCTs for NAND memory devices are desirable.
In one aspect of the present disclosure, a 3D memory device includes a conductor/insulator stack containing a first conductive layer and a first dielectric layer alternatingly stacked, a channel hole structure extending through the conductor/insulator stack, a staircase contact (SCT), and a second dielectric layer. The SCT includes a conductive structure, extends through the first dielectric layer, and is electrically connected to the first conductive layer. The second dielectric layer is parallel to the first conductive layer. The SCT contacts the second dielectric layer.
In another aspect of the present disclosure, a method for fabricating a 3D memory device includes forming a dielectric stack that has a first dielectric layer and a second dielectric layer alternately stacked, forming a channel hole structure through the dielectric stack, removing a first portion of the first dielectric layer to form a first cavity, filling the first cavity with a first filling structure, removing a second portion of the first dielectric layer to form a second cavity in which the channel hole structure is exposed, removing the first filling structure, forming a combined cavity including the first and second cavities, and depositing a first conductive material in the combined cavity to form a conductive layer. The combined cavity extends from the channel hole structure to a bottom of a first opening for a staircase contact (SCT). The conductive layer extends from the channel hole structure to the bottom of the first opening.
In another aspect of the present disclosure, a system includes a memory device, and a memory controller for controlling the memory device. The memory device includes a conductor/insulator stack containing a first conductive layer and a first dielectric layer alternatingly stacked, a channel hole structure extending through the conductor/insulator stack, a staircase contact (SCT), and a second dielectric layer. The SCT includes a conductive structure, extends through the first dielectric layer, and is electrically connected to the first conductive layer. The second dielectric layer is parallel to the first conductive layer. The SCT contacts the second dielectric layer.
Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
The following describes the technical solutions according to various aspects of the present disclosure with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Apparently, the described aspects are merely some but not all of the aspects of the present disclosure. Features in various aspects may be exchanged and/or combined.
As shown in
In some aspects, layers 111-116 are deposited over the substrate 110 by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. The layers 111 and 115 are undoped or lightly doped polysilicon layers. The layers 112, 114 and 116 are silicon oxide layers. The layer 113 may be another silicon oxide layer in some cases. Optionally, the layer 113 may be a layer of another material such as aluminum oxide.
Further, a dielectric stack 140 is formed over the substrate 110 or silicon oxide layer 116, and a dielectric layer 117 is formed over the dielectric stack 140. The layer 117 may include silicon oxide. The dielectric stack 140 may be considered as a dielectric stack structure that includes multiple pairs of stack layers, for example, including first dielectric layers 141 and second dielectric layers 142, stacked alternately over each other. Some layers of the dielectric stack 140 are used to form memory cells. In some cases, the layers for fabricating memory cells may include 64 pairs, 128 pairs, or more than 128 pairs of the first and second dielectric layers 141 and 142.
In some aspects, the first dielectric layers 141 and the second dielectric layers 142 are made of different materials. In descriptions below, the first dielectric layer 141 includes a silicon oxide layer exemplarily, which may be used as an isolation stack layer, while the second dielectric layer 142 includes a silicon nitride layer exemplarily, which may be used as a sacrificial stack layer. The sacrificial stack layer will be subsequently etched out and replaced by a conductive stack layer. The first dielectric layers 141 and second dielectric layers 142 may be deposited via CVD, PVD, ALD, or a combination thereof.
As shown in
Further, a functional layer 151 is deposited on the sidewall of the channel hole and in the cavity 150A. The functional layer 151 includes a blocking layer 152 on the sidewall to block an outflow of charges, a charge trap layer 153 on a surface of the blocking layer 152 to store charges during an operation of the 3D array device 100, and a tunneling layer 154 on a surface of the charge trap layer 153. In some aspects, when the tunneling layer 154 is deposited, the opening of the cavity 150A may pinch off and the cavity 150A may become a void 150A. The blocking layer 152 may include one or more layers that may include one or more materials. The material for the blocking layer 152 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, or another wide bandgap material. The charge trap layer 153 may include one or more layers that may include one or more materials. The materials for the charge trap layer 153 may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, a high-k dielectric material such as aluminum oxide or hafnium oxide, or another wide bandgap material. The tunneling layer 154 may include one or more layers that may include one or more materials. The material for the tunneling layer 154 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, or another wide bandgap material.
Further, a semiconductor channel 155 is deposited on a surface of the tunneling layer 154. The semiconductor channel 155 includes a polysilicon layer in some aspects. Optionally, the semiconductor channel 155 may include an amorphous silicon layer. The semiconductor channel 155 may extends through the dielectric stack 140 and into the layer 114 in certain cases. The blocking layer 152, the charge trap layer 153, the tunneling layer 154, and the semiconductor channel 155 may be deposited by, e.g., CVD and/or ALD. The structure formed in a channel hole, including the functional layer 151 and semiconductor channel 155, is referred to as the channel hole structure.
After the semiconductor channel 155 is formed, the opening of the channel hole is filled by an oxide material 156 and a conductive plug is formed at the top of the channel hole structure, as shown in
In some cases, the functional layer 151 includes an oxide-nitride-oxide (ONO) structure. That is, the blocking layer 152 is a silicon oxide layer, the charge trap layer 153 is a silicon nitride layer, and the tunneling layer 154 is another silicon oxide layer.
Optionally, the functional layer 151 may have a structure different from the ONO configuration. In the following descriptions, the ONO structure is used exemplarily for the blocking layer 152, the charge trap layer 153, and the tunneling layer 154.
The opening 120 may be formed by, for example, a dry etch process or a combination of dry and wet etch processes. As shown in
Further, a selective etch, such as a selective wet etch, is performed to etch out a portion of the target second dielectric layer 142 (i.e., a silicon nitride layer). In some embodiments, the selective wet etch is conducted for a predetermined etch time. A cavity 122 is formed after the portion of the layer 142 is removed, as shown in
After the cavity 122 is formed, a filling material such as polysilicon is deposited to fill the opening 120 and the cavity 122. The opening 120 is filled with a filling structure 123 and the cavity 122 is filled by a layer 122A, as shown in
With methods and processes similar to those used to make the structures around the SCT region 124, structures around another SCT region 134 are formed. As shown in
The opening 161 may be formed by, for example, a dry etch process or a combination of dry and wet etch processes. As shown in
After the opening 161 is etched, an oxidation process is performed. The exposed portions of the polysilicon layers 111 and 115 are changed into silicon oxide regions 162 and 163, as shown in
Further, a dielectric material (e.g., silicon oxide) is deposited over the top surface of the 3D array device 100 by CVD and/or ALD. A dielectric layer 117A is grown, as shown in
Further, a selective etch is performed for a predetermined time period to remove certain portions of the second dielectric layers 142, leaving cavities 143A between the first dielectric layers 141, as shown in
Further, a filling material (e.g., polysilicon) is deposited to fill the opening 161B and cavities 143A. A filling structure 161C is formed to fill the opening 161B, while layers 143B are formed to fill the cavities 143A, as illustrated in
The opening 161D represents a section of the opening 161 in the GLS region 160B, and may be formed by, for example, a selective etch process that removes the remaining part of the filling structure 161A. At the bottom of the opening 161D, the polysilicon layer 111 is exposed.
After the opening 161D is formed, a selective etch is performed for a predetermined time period to remove certain portions of the second dielectric layers 142, leaving cavities 143 between the first dielectric layers 141, as shown in
Further, a selective etch, such as a selective wet etch, is performed to etch out the filling structures 123, 133, and 161C During the selective etch, the layers 122A and 132A are also etched away, creating cavities 122B and 132B, as shown in
Further, a conductive material such as tungsten (W) is deposited to fill the cavities 143 left by the removal of the second dielectric layers 142 and the combined cavities. A layer of the conductive material is also formed on the sidewalls and bottoms of the openings 125, 135, and 161D. The layer of the conductive material is subsequently etched away in an etch process, leaving the conductive material in the cavities. As such, conductive layers 145 are formed between the first dielectric layers 141 and contact the blocking layers 152 of the channel hole structures, respectively. Conductive layers 122C and 132C are formed in the cavities 122B and 132B. Conductive layers (not shown) are also formed in the cavities 143A that reappears. After the conductive layers 145 are made, the dielectric stack 144 is converted into a conductor/insulator stack 146, as shown in
The conductive layer 122C, a conductive layer 145 on the same level, and a conductive layer grown in a cavity 143A of the same level are connected electrically and form a combined conductive layer in one of the combined cavities. Similarly, the conductive layer 132C, a conductive layer 145 on the same level, and a conductive layer grown in a cavity 143A on the same level are connected and form another combined conductive layer. The combined conductive layer extends from the functional layers 151 (or the channel hole structures) in the channel hole structure regions 150 to the bottom of one of the openings for SCT (e.g., the opening 125 or 135). As such, each combined conductive layer is electrically connected with a corresponding conductive layer 145.
In some aspects, before metal W is deposited in the cavities 143, 143A, 122B, and 132B, a layer (not shown) of a high-k dielectric material such as aluminum oxide may be deposited. Thereafter, a layer of a conductive material such as titanium nitride (TiN) (not shown) is deposited. Further, metal W is deposited to form the conductive layers 145, 122C, and 132C. CVD and/or ALD may be used in the deposition processes. Alternatively, another conductive material, such as molybdenum (Mo), ruthenium (Ru), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), doped silicon, or any combination thereof, may be used to form these conductive layers.
Referring to
Referring to
Referring to
Further, a silicon oxide layer 118 is deposited over the top surface including the SCT regions 124 and 134, the channel hole structure regions 150, and the GLS region 160B. CVD, PVD, and/or ALD may be performed. A portion of the silicon oxide layer 118 that covers the SCT regions 124 and 134 is removed in an etch process (e.g., dry and/or wet etch), exposing the filling structures 127 and 137. After a selective etch process (e.g., a selective wet etch process), the filling structures 127 and 137 are removed and openings 128 and 138 are formed in the SCT regions, as depicted in
The SCT regions 124 and 134, channel hole structure regions 150, and GLS region 160B are covered by layers of silicon oxide. These silicon oxide layers are etched away in a selective etch process such as a selective wet etch process. As shown in
Further, a conductive material is deposited by CVD and/or ALD. The conductive material may include a metallic material such as W, Co, Cu, or Al in some aspects. The deposition creates SCT layers 129A and 139A in the openings 128 and 138. The SCT layers 129A and 139A may be considered as SCTs 129 and 139 that are electrically connected to corresponding conductive layers 145 (i.e., word lines) via the conductive layers 122C and 132C, respectively. Take the SCT 129 for example. As the second dielectric layer 142 underneath the layer 122C is exposed in the openings 128, the SCT 129 is deposited on and contact the second dielectric layer 142 underneath the layer 122C, forming an interface between the SCT 129 and the second dielectric layer 142. The interface is parallel to the substrate 110 and layer 122C. The SCT 129 extends through the dielectric stack structure formed by the first and second dielectric layers 141 and 142, and passes through the layer 122C and the first dielectric layer 141 underneath the layer 122C in the Z direction or a direction perpendicular to the substrate 110 and layer 122C. In such cases, a section of the SCT layer 129A is formed at the bottom of the opening 128. This section of the SCT layer 129A contacts the second dielectric layer 142 underneath the layer 122C, and is at a level below that of the layer 122C or a corresponding conductive layer 145 it is connected with.
In some cases, before forming the SCT layers 129A and 139A, a conductive material such as TiN may be deposited first to grow thin layers 129B and 139B as a contact and/or barrier layer on the sidewalls and bottom surfaces of the openings 128 and 138. In such cases, the SCT layers 129A and 139A may be deposited on the layers 129B and 139B, respectively, as shown in
After the SCTs 129 and 139 are formed, a dielectric material such as silicon oxide is deposited by CVD to fill the openings 128 and 138, producing dielectric filling structures 147 and 148 in the openings 128 and 138, respectively. The filling structures 147 and 148 are horizontally surrounded by the SCTs 129 and 139, respectively. Voids (e.g., a void 147A) may form in the filling structures 147 and 148 in certain cases.
In some aspects, the SCTs 129 and 139 have a 3D pocket structure (or surrounding structure) in the SCT regions 124 and 134. The pocket structure may have any shape (e.g., a square or circular shape) in an X-Y plane and extend toward the substrate along the Z direction. The bottom of the pocket structure contacts the second dielectric layer 142, and the side of the pocket structure electrically contacts the layer 122C or 132C. The dielectric filling structures 147 and 148 are formed in and surrounded by the pocket structures.
As illustrated above, an SCT (e.g., the SCT 129 or 139) is electrically connected with a conductive layer 145 (i.e., a word line), while other conductive layers 145 are isolated from the SCT by portions of the first and second dielectric layers 141 and 142 that are around the SCT. Optionally, a CMP process is performed after the openings are filled. Besides openings 125 and 135 and cavities 122B and 132B, when additional openings and cavities are formed in other SCT regions, additional SCTs may be fabricated simultaneously in the process illustrated above. These additional SCTs may connect with corresponding conductive layers 145, respectively.
Referring to
Further, conductor layers 175 for interconnect are grown by CVD, PVD, and/or ALD. The conductor layers 175 are deposited over and connected to the vias 171-174, respectively, and include a conductive material such as W, Co, Cu, Al, Mo, Ru, or a combination thereof. Optionally, a contact layer (e.g., TiN) may be deposited before the conductive material is deposited to create the conductor layers 175.
Further, vias 176 are formed over the conductor layers 175. For example, a dielectric material may be deposited to cover the conductor layers 175 and make the dielectric layer 117 thicker. After openings for vias 176 are formed, a thin layer of TiN may be deposited in some cases. The openings are then filled with a conductive material to form the vias 176. The conductive material of the vias 176 may include W, Co, Cu, Al, Mo, or Ru.
Further, a CVD or PVD process is performed to deposit a dielectric material (e.g., silicon oxide) to cover the vias 176 and thicken the dielectric layer 117 further. Openings are made and then filled to form connecting pads 177, 178, and 179 that serve as interconnects with a periphery device. As shown in
For the 3D array device 100 and periphery device 180, the bottom side of the substrate 110 or 181 may be referred to as the back side, and the side with the connecting pads 177-179 or 183-185 may be referred to as the front side or face side.
The 3D array device 100 and periphery device 180 are bonded by a flip-chip bonding method to form the 3D memory device 190, as shown in
Thereafter, other fabrication steps or processes are performed to complete fabrication of the 3D memory device 190. The other fabrication steps and processes are not reflected in
Further, channel hole structures are formed that extend through the dielectric stack and the multiple layers. For example, channel holes are etched. A functional layer is deposited on the sidewall and bottom surface of each channel hole. The functional layer includes a blocking layer, a charge trap layer, and a tunneling layer that are deposited sequentially. Thereafter, a semiconductor channel is grown on a surface of the tunneling layer. The channel hole structure includes the functional layer and semiconductor layer.
At 211, a first opening is formed for an SCT in an SCT region. The first opening extends through a portion of the dielectric stack to expose a target first dielectric layer, i.e., a silicon oxide layer. CVD or ALD is performed to deposit silicon oxide on the sidewall and bottom of the first opening. An etch is conducted to etch the bottom of the first opening to expose a second dielectric layer underneath, that is, a sacrificial silicon nitride layer.
At 212, the exposed sacrificial layer is etched in a selective wet etch, creating a first cavity below the first opening and between two adjacent first dielectric layers. The selective wet etch is carried out for a predetermined etch time to control the depth of the first cavity. The first cavity and first opening are filled with a material such as polysilicon in a deposition process. A first filling structure is formed to fill the first opening and first cavity.
At 213, a second opening is formed for a GLS of the 3D array device. Along a direction vertical to the substrate, the second opening extends through the dielectric stack and the multiple layers between the dielectric stack and the substrate. The second opening extends through a first GLS region and a second GLS region horizontally. The first GLS region is close to the SCT region and dummy channel hole structures, while the second GLS region is close to channel hole structures. The dummy channel hole structures may provide mechanical support for the dielectric stack. When the multiple layers contain one or more polysilicon layers, an oxidation process is performed to oxidize the exposed polysilicon. The second opening is then filled with a material such as polysilicon by CVD and/or ALD. A second filling structure is formed in the second opening. Thereafter, a part of the second filling structure in the first GLS region is etched away to form a third opening. The third opening exposes second dielectric layers that are sacrificial silicon nitride layers on the sidewall.
At 214, the exposed sacrificial layers are etched to form second cavities in a selective wet etch. Each second cavity is between two adjacent first dielectric layers. The selective wet etch is performed for a predetermined etch time to control the depth of the second cavity. One of the second cavities exposes a part of the first filling structure, while rest of the second cavities is separated from the first filling structure by sections of the sacrificial layers. The third opening and second cavities are filled with a material such as polysilicon in a deposition process. A third filling structure is formed to fill the third opening and second cavities. The first and third filling structures contact each other through the exposed part of the first filling structure.
At 215, the remaining part of the second filling structure in the second GLS region is etched out to form a fourth opening. Along a direction vertical to the substrate, the fourth opening extends through the dielectric stack and the multiple layers between the dielectric stack and the substrate. The fourth opening exposes second dielectric layers that are sacrificial silicon nitride layers on the sidewall.
At 216, the exposed sacrificial layers are etched to form third cavities in a selective wet etch. Each third cavity is between two adjacent first dielectric layers. The selective wet etch is performed for a certain etch time to control the depth of the third cavities. The third cavities expose parts of the third filling structure, while the third cavities are separated from the first filling structure by sections of the sacrificial layers.
At 217, the first and third filling structures are etched away in one or more selective wet etches. The first opening and first cavity are recreated, so are the third opening and second cavities. Each second cavity merges with a corresponding third cavity on the same level with respect to the substrate. The first cavity, a second cavity on the same level, and a third cavity on the same level merge to form a combined cavity.
The first, second, and third cavities are filled with conductive materials to form conductive layers in a cavity filling process. The conductive layers may be referred to as word lines. The cavity filling process may include depositing a layer of a high-k dielectric material, a layer of TiN, and a metallic material (e.g., W) consecutively. The materials deposited in the cavity filling process, which may include the high-k dielectric material, TiN, and W, are removed from the sidewalls and bottoms of the first, third, and fourth openings by etch. The dielectric stack is transformed into a conductor/insulator stack.
At 218, a dielectric material (e.g., silicon oxide) is deposited on the sidewalls and bottom surfaces of the first, third, and fourth openings, followed by one or more depositions of polysilicon that fill these openings, respectively. The GLS is formed in the third and fourth openings. Optionally, CMP may be performed to flatten the top surface. Further, a silicon oxide layer is grown to cover the SCT and GLS regions on the top surface. The silicon oxide layer covering the SCT region is removed by etch. A selective etch process is carried out to respectively remove materials (e.g., polysilicon and silicon oxide) that fill the first opening. The first opening reappears. At the bottom of the first opening, the second dielectric layer and a conductive layer are exposed. The exposed conductive layer is formed in the combined cavity during the cavity filling process, and extends from the bottom of the first opening to the channel hole structures.
A conductive material, such as W, Co, Cu, or Al, is deposited on the sidewall and bottom of the first opening to form an SCT in the SCT region. The SCT electrically contacts the exposed conductive layer and thus is electrically connected with a word line. Optionally, a layer of TiN may be grown as a contact layer and/or barrier layer before depositing the conductive material to make the SCT. As such, the SCT is formed in the first opening and contains one or more layers made from conductive materials. In some aspects, the one or more layers of the SCT form a 3D pocket shape. The bottom of the pocket contacts a second dielectric layer, and the side of the pocket electrically contacts a conductive layer. The SCT or the pocket is filled with materials such as a dielectric material and polysilicon sequentially.
At 219, etching and deposition processes are performed to form other contacts including through silicon contacts that extend from the top surface towards the substrate. These contacts may be made of a conductive material such as W, Co, Cu, or Al. Further, silicon oxide is deposited to form a silicon oxide layer that covers the top surface. Openings are formed and filled in the silicon oxide layer to make vias. The vias may connect with the SCT, the channel hole structures, the through silicon contacts, etc. Thereafter, conductor layers, additional vias, and connecting pads are fabricated for the 3D array device.
Further, a flip-chip bonding process is performed to bond the 3D array device and a periphery device to create a 3D memory device. In some aspects, the 3D array device is flipped upside down and positioned above the periphery device. The connecting pads of the 3D array device and the periphery device are aligned and then bonded. After the substrate of the 3D array device is thinned, etching and deposition processes are performed to form vias, conductor layers, and contact pads for the 3D memory device. The contact pads are configured for wire bonding for connection with other devices.
As illustrated above, the conductor/insulator stack and GLS are made after some structures for the SCT are formed. A combined cavity for a conductive layer is created between an opening for the SCT and the channel hole structures. The conductive layer that extends between the opening for the SCT and the channel hole structures is grown in the combined cavity in one deposition. The fabrication process is relatively simple and has certain reliability and cost advantages.
The memory controller 306 is coupled to the memory devices 304 and host 308 and is configured to control the memory devices 304, according to some implementations. The memory controller 306 may manage the data stored in the memory devices 304 and communicate with the host 308. In some embodiments, the memory controller 306 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some other embodiments, the memory controller 306 is designed for operating in a high duty-cycle environment, such as solid-state drives (SSDs) or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. The memory controller 306 may be configured to control operations of the memory device 304, such as read, erase, and program operations.
The memory controller 306 may also be configured to manage various functions with respect to the data stored or to be stored in the memory device 304 including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, the memory controller 306 is further configured to process error correction codes (ECCs) with respect to the data read from or written to the memory device 304. Any other suitable functions may be performed by the memory controller 306 as well, for example, formatting the memory device 304. The memory controller 306 may communicate with an external device (e.g., the host 308) according to a particular communication protocol. For example, the memory controller 306 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.
The memory device 304 may be any memory device disclosed in the present disclosure, such as the 3D memory device 190 shown in
The memory controller 306 and one or more memory devices 304 may be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, the memory system 302 may be implemented and packaged into different types of end electronic products.
Although the principles and implementations of the present disclosure are described by using specific aspects in the specification, the foregoing descriptions of the aspects are only intended to help understand the present disclosure. In addition, features of aforementioned different aspects may be combined to form additional aspects. A person of ordinary skill in the art may make modifications to the specific implementations and application range according to the idea of the present disclosure. Hence, the content of the specification should not be construed as a limitation to the present disclosure.
