Patent Application
20070010072
The present invention relates generally to depositing a layer of silicon-nitrogen, silicon-oxygen, or silicon-nitrogen-oxygen material simultaneously on a plurality of substrates and in particular to the use of a silylamine precursor in combination with a across-flow liner to achieve a degree of within-wafer and wafer-to-wafer uniformity while improving impurity profiles to form silicon-oxygen, silicon-nitrogen, or silicon-nitrogen-oxygen materials.
Thermal processing apparatuses are commonly used in the manufacture of integrated circuits (ICs) or semiconductor devices from semiconductor substrates or wafers. Thermal processing of semiconductor wafers include, for example, heat treating, annealing, diffusion or driving of dopant material, deposition or growth of layers of material, and etching or removal of material from the substrate. These processes often call for the wafer to be heated to a temperature as high as 1300° C. and as low as 300° C. before and during the process, and that one or more fluids, such as a process gas or reactant, be delivered to the wafer. Moreover, these processes typically require that the wafer be maintained at a uniform temperature throughout the process, despite variations in the temperature of the process gas or the rate at which it is introduced into the process chamber.
Silicon nitride, silicon dioxide, and silicon oxynitride are dielectric materials widely used in the manufacture of semiconductor devices. These films are typically deposited from silicon sources such as silane (SiH4), disilane (Si2H6), dichlorosilane (DCS) (SiCl2H2), organosilanes and others with various reactant sources such as ammonia (NH3), oxygen (O2), ozone (O3), nitrous oxide (N2O), nitrogen dioxide (NO2), nitric oxide (NO), and others depending on the desired material composition. Additionally, ozone (O3) has been investigated as a potential species for the direct formation of SiO2 when reacted with exposed Si surfaces. The temperatures of these processes are typically greater than 600° C. The high speed requirements of advanced semiconductor devices dictate that the overall thermal budget of the device manufacture be lowered. This is driving the need to reduce the processing temperature of dielectric layers to below 550° C. and preferably below 500° C. The most desired deposition temperature would be 400° C. or lower. Several new silicon precursors have been developed to address the need for lower temperature dielectric deposition.
In addition to high deposition temperatures associated with conventional batch process chemical vapor deposition, there is a growing appreciation that contaminants associated with these processes limit the effectiveness of the deposited materials to perform as intended barrier or insulative layers. By way of example, the use of a chlorinated silane precursor or co-reactant leads to chlorine incorporation into a deposited layer to the detriment of the material performance. In the case of silicon nitride deposition, reaction of a chlorinated silane with ammonia yields ammonium chloride that clogs reactor exhaust ports and also condenses on deposited layers thereby forcing the wafer substrate to remain at elevated temperatures subsequent to deposition so as to increase the thermal budget, reduce throughput, and invariably still incorporate a diffusible chlorine contaminant.
Efforts to address the process and performance limitations associated with chlorinated deposition precursors have led to the usage of various organosilanes. Unfortunately, these precursors have met with limited acceptance owing to coking during material deposition. The inclusion of carbon within a deposited material as a result of incomplete pyrolysis not only diminishes the electrically insulative properties of the resulting material but also creates a concern about diffusion of carbon that can poison device semiconductor elements.
These problems associated with chlorine and carbon inclusion have led to the exploration of various silylamines. As silylamines contain a silicon-nitrogen bond, these precursors have garnered attention as typically having lower deposition temperatures and have better contaminant inclusion profiles than analogous chlorosilanes and organosilanes. In the case of the unsubstituted silylamines, neither carbon nor chlorine is present and the resulting deposited layer of material is free of carbon and chlorine contaminants. Silylamines tend to incorporate hydrogen as an impurity that migrates readily and diminishes material performance. While deposition of silicon nitride and silicon oxynitride from silylamines such as trisilylamine has been reported, little attention has been paid to hydrogen content of the resulting films or batch deposition of such materials. US 2005/0100670 A1 is representative of these efforts.
A conventional batch thermal processing apparatus typically includes a process chamber positioned in or surrounded by a furnace. Substrates to be thermally processed are sealed in the process chamber and heated to a desired temperature at which the deposition reaction is performed. For many processes, such as Chemical Vapor Deposition (CVD), the sealed process chamber is first evacuated to a desired process pressure, and once the process chamber has reached the desired temperature, reactive or process gases are introduced to form or deposit reactant species on the substrates. Various forms of CVD can be performed including low pressure (LPCVD), plasma enhanced (PECVD), and thermal CVD to name but a few with the choice of technique specifics involving a balancing of factors inclusive of thermal budget, desired film uniformity and porosity, and contaminant limits. To date, efforts to achieve satisfactory batch material layer deposition with satisfactory within-wafer (WIW) and wafer-to-wafer (WTW) uniformity have met with limited success.
Thermal oxidation produces high quality silicon dioxide films, which are important for electrical isolation of active regions of electronic devices. Typically, thermal oxidation is carried out using O2 (dry oxidation) or steam (wet oxidation) at temperatures ranging from 750° C. to 1150° C. at atmospheric pressure or slightly below atmospheric pressure.
Thermal oxidation, however, has several limitations. The rate of thermal oxidation depends strongly on the crystal orientation of silicon surfaces. Due to the high packing density of (111) surfaces, oxidation on the (111) surfaces is significantly higher than that on (100) surfaces. Shallow trench isolation (STI) for logic applications and trench isolation for DRAM applications involve (100), (110) and (111) silicon surfaces in the trench. It has been very difficult to produce a uniform oxide liner on trench surfaces with rounded and stress-released trench corners, which in turn causes leakage in logic devices and reduction of data retention time in DRAM devices. Additionally, the rate of thermal oxidation is sensitive to the nature and amount of implanted dopants and also differs between single-crystal and polycrystalline silicon surfaces, so as to hamper further scaling of flash memory devices. To improve thermal oxidation uniformity requires oxidation at low pressures of about 5 torr, thereby limiting throughput.
Thus, there exists a need for a process able to yield a wafer substrate batch having a layer of silicon nitride, silicon oxide, or silicon oxynitride thereon with WIW and WTW uniformity at moderate temperature and tolerable contaminant profiles.
A batch of wafer substrates is provided with each wafer substrate having a surface. Each surface is coated with a layer of material applied simultaneously to the surface of each of the batch of wafer substrates. The layer of material is applied to a thickness that varies less than four thickness percent across the surface and exclusive of an edge boundary and having a wafer-to-wafer thickness variation of less than three percent. The layer of material so applied is a silicon oxide, silicon nitride or silicon oxynitride with the layer of material being devoid of carbon and chlorine. The material deposition occurs ideally below 600° C. A silicon nitride layer of material is formed from a precursor having the Formula I or II alone or in combination with a coreactant:
where R1, R2 and R3 are each independently hydrogen or C1-8 alkyl, R1 is SiH3 when R2 and R3 are both hydrogen, and R4 is hydrogen, C1-8 alkyl, or Si bonded to R1, R2 and R3. Formation of silicon oxide or a silicon oxynitride requires the inclusion of a co-reactant. Silicon nitride is also formed with the inclusion of a nitrification co-reactant.
A process for forming such a batch of wafer substrates involves feeding the precursor into a reactor containing a batch of wafer substrates and reacting the precursor at a wafer substrate temperature, total pressure, and precursor flow rate sufficient to create such a layer of material. The delivery of a precursor and co-reactant as needed, through vertical tube injectors having multiple orifices with at least one orifice in registry with each of the batch of wafer substrates and exit slits within the reactor creates flow across the surface of each of the wafer substrates in the batch to yield the aforementioned within-wafer and wafer-to-wafer uniformity.
The present invention has utility as a batch of semiconductor wafer substrates having deposited thereon a layer of a silicon nitride material, silicon oxide material, or silicon oxynitride material, the material layer exhibiting within-wafer uniformity of less than four thickness percent three sigma and a wafer-to-wafer uniformity of less than three thickness percent that are simultaneously produced absent carbon and chloride contamination. A process to achieve such a batch of wafer substrates is provided utilizing across-flow dispersion of reactants relative to a wafer substrate surface.
As used herein within-wafer (WIW) variation is defined as the topological thickness variation across a 300 mm planar wafer substrate between the thinnest and thickest material layer deposited exclusive of an edge zone of 3 mm edge exclusion and shadow regions associated with a wafer carrier boat rail.
As used herein, wafer-to-wafer (WTW) variation is defined as the maximal difference in average thickness in a material layer between a batch of multiple wafers simultaneously processed for layer deposition.
A silicon-nitrogen-silicon (Si—N—Si) structure containing precursor is used to produce an inventive layer of a material simultaneously to a batch of wafer substrates. Preferably, the precursor is stable under an inert atmosphere at 20° C. An inventive precursor in acyclic form has the general formula:
Preferably, when the precursor has the structure according to Formula I, R1, R2 and R3 in every occurrence are identical. More preferably, R1, R2 and R3 are all hydrogen. Most preferably, R4 is the silicon bonded to R1, R2 and R3 where R1, R2 and R3 are all hydrogen and Formula (I) corresponds to trisilylamine (TSA).
A silicon-nitrogen-silicon structure containing cyclic precursor has the structure:
where R1, R2 and R4 have the identities as detailed above with respect to the acyclic precursor of Formula I. Preferably, R1 and R2 in every occurrence are identical and R4 in every occurrence is identical. More preferably, R1 in every occurrence is hydrogen, R2 in every occurrence is hydrogen, and R4 is hydrogen or SiH3. It is noted that the inventive precursors of Formulas (I) and (II) are devoid of halogen moieties specifically exclusive of chlorine, and as a result the resulting layer of material deposited is independent of chlorine contaminants and chlorine/chloride containing volatile byproducts. A layer of material is deposited according to the present invention that is substantially devoid of carbon inclusion even though the precursor of Formula I or II includes alkyl moieties. However, the avoidance of carbon infiltrates into a deposited inventive layer of material typically requires that deposition rates be adjusted to under 10 Angstroms per minute. The deposition of inventive material layers devoid of carbon was readily accomplished through the selection of a precursor containing only silicon, nitrogen and hydrogen atoms.
Mixtures of multiple precursors as detailed above are appreciated to be operative herein as well as the use of an inventive precursor with traditional silicon containing precursor compounds. Additionally, it is recognized that inventive precursor compounds may contain minor amounts of impurities that may be incorporated into an inventive material layer. Such impurity incorporation is diminished to acceptable levels through additional precursor purification prior to usage and storage under nonreactive conditions. Additionally, it is appreciated that an inventive precursor is stored with an inert diluent or metered through a reaction chamber with such a diluent with conventional techniques such as the employ of a mass flow controller (MFC).
Formation of a layer SiyN where y is between 0.75 and 1 is noted to readily occur upon injecting a precursor into a reaction chamber with the wafer batch typically held at a temperature range of between 450° C. and 800° C. In instances where y is less than 1 and the precursor of Formula I or II is devoid of alkyl moieties, y-1 corresponds to the amount of hydrogen intercalation into the resultant silicon nitride material layer.
It is appreciated that annealing a hydrogen containing silicon nitride material layer in the presence of a nitrogen source such as ammonia subsequent to deposition removes hydrogen from the layer and increases the nitrogen content of the resulting layer to the point where nitrogen-rich silicon nitride (Si3N4) is achieved. While the hydrogen depleting annealing can occur at temperatures above 400° C., the kinetics of such anneal increase with temperature. In instarices where thermal budget of a wafer substrate is an issue, rapid thermal processing and other flash annealing techniques are appreciated to be operative.
In addition to pyrolysis of a precursor of Formula I or II, the deposition mechanism and/or film composition is altered by reacting a precursor of Formulas (I) and (II) with a nitrifying or oxidizing co-reactant. Such co-reactants illustratively include NH3, HN3, H2N2, secondary amines, tertiary amines, NH* radicals, NH2*radicals, O2, O3, O* radicals, OH* radicals, H2O, H2O2, NO, N2O, and NO2. Preferably, the co-reactant is devoid of carbon atoms and chlorine atoms. The co-reactant, if present, is injected into a reaction chamber either in concert with the precursor of Formula I or II, in an alternating pulsatile flow relative to the precursor, or after deposition of a material layer from the precursor has occurred. Post deposition introduction of the coreactant results in a post-processing modification. In instances where one desires to deposit a layer of silicon dioxide, preferably an oxygen containing co-reactant such as oxygen, ozone, water or a combination thereof is injected into the reactor volume in concert with the precursor of Formula I or II. Likewise, a layer of a material having a stoichiometry with little variation through the thickness of the layer is produced by injecting nitrogen and oxygen containing co-reactants into the reactor with the precursor of Formula I or II. Silicon oxynitride precursors include NOx molecules; a combination of an oxidizing precursor and a nitrifying precursor, such as ammonia; or combinations thereof. Production of a batch of wafer substrates containing a layer of material applied simultaneously thereto according to the present invention typically occurs at a pressure of less than 50 Torr and preferably less than 10 Torr. More preferably, the reactor pressure is maintained between 100 millitorr and 7 Torr total pressure through resort to an inert diluent gas to deposit a material layer. Inert diluent gases illustratively include the noble gases, dinitrogen or combinations thereof. It is appreciated that deposition rates of a layer of material vary considerably based not only on the material being deposited but also on flow rates, total reaction pressure, and temperature. One of skill in the art will appreciate that deposition rates of the deposition of all the inventive materials tend to increase with increases in temperature, precursor flow rate, and total pressure. The nature of such parameters will be further detailed with respect to the following examples.
The deposition of various material layers according to the present invention and the conditions under which such deposition occurs where the precursor of Formula I or II is supplied at a flow rate of between 1 and 50 sccm is detailed in Table 1 where the units for the coreactant flow rate and inert diluent flow rate are in multiples of precursor flow rate.
It is appreciated that a number of co-reactants detailed herein are in equilibrium with radical species. Without intending to be bound to a particular mechanistic theory, such radical species are believed to be involved in material layer deposition at the comparatively low temperatures of the present invention as compared to the prior art. The singlet oxygen (O*) formation from ozone and NO* formation from N2O are exemplary of known radical species formed under the temperature and pressure conditions detailed in Table 1. Optionally, radical species concentration generation is enhanced through the inclusion of the radical generator with which a precursor of Formula I or II, a co-reactant, or a combination thereof is exposed in the course of the material layer deposition process. Conventional radical generating sources operable within the context of the present invention include plasma discharge electrodes, photolysis sources, and rapid thermal in-situ steam generation (ISSG) processing. One of ordinary skill in the art will appreciate that while radical species concentration increase associated with the addition of a free radical generator tends to decrease the required deposition temperature, care is required to maintain reaction condition uniformity across a wafer surface and throughout a wafer batch reactor volume.
A reactor well suited to yield material layer deposition in a batch process such that a batch of wafer substrates each receive a layer of material on a deposition surface simultaneously to a thickness of greater than 15 Angstroms such that the thickness of the material layer applied to each wafer surface varies less than four percent three sigma WIW and less than three percent in layer thickness WTW. Such a reactor overcomes problems associated with uniform precursor distribution within a batch chamber and utilizes elongated injector tubes rotatable about a tube axis with the injector tubes including orifices in registry with wafer carrier positions and a series of exit slits so as to create a flow across the multiple wafer surfaces of a batch in a laminar across flow pattern. Such a reactor is disclosed in WO 2005/031233 filed Sep. 22, 2004. Such a reactor is currently commercially available from Aviza Technology (Scotts Valley, Calif.).
As shown in
Additionally, across-flow injectors 116 can serve other purposes, including the injection of diluent gases between the wafers 108. Use of across-flow injectors 116 results in a more uniform cooling between wafers 108 whether a wafer substrate is disposed at the bottom, top or middle of the stack of wafers, as compared with earlier gas flow configurations. Preferably, the injector 116 orifices 180 are sized, shaped and positioned to provide a spray pattern that promotes forced convective cooling between the wafers 108 in a manner that does not create a large temperature gradient across the wafer.
Generally, the vessel 101 is sealed by a seal, such as an O-ring 122, to a platform or base plate 124 to form the process chamber 102, which completely encloses the wafers 108 during thermal processing. The dimensions of the process chamber 102 and the base plate 124 are selected to provide a rapid evacuation, rapid heating and a rapid backfilling of the process chamber. Advantageously, the vessel 101 and the base plate 124 are sized to provide a process chamber 102 having dimensions selected to enclose a volume substantially no larger than necessary to accommodate the liner 120 with the carrier 106 and wafers 108 held therein. Preferably, the vessel 101 and the base plate 124 are sized to provide a process chamber 102 having dimensions of from about 125% to about 150% of that necessary to accommodate the liner 120 with the carrier 106 and wafers 108 held therein, and more preferably, the process chamber has dimensions no larger than about 125% of that necessary to accommodate the liner 120 and the carrier 106 and wafers 108 in order to minimize the chamber volume and thereby reduce pump down and backfill time required.
Openings for the injectors 116, T/Cs 114 and vents 118 are sealed using seals such as o-rings, VCR®, or CF® fittings. Gases or vapor released or introduced during processing are evacuated through a foreline or exhaust port 126 formed in a wall of the process chamber 102 (not shown) or in a plenum 127 of the base plate 124, as shown in
In another embodiment, shown in
The vessel 101 and liner 254 can be made of any metal, ceramic, crystalline or glass material that is capable of withstanding the thermal and mechanical stresses of high temperature and high vacuum operation, and which is resistant to erosion from gases and vapors used or released during processing. Preferably, the vessel 101 and liner 120 are made from an opaque, translucent or transparent quartz glass having a sufficient thickness to withstand the mechanical stresses of the thermal processing operation and resist deposition of process byproducts. By resisting deposition of process byproducts, the vessel 101 and liner 254 reduce the potential for contamination of the processing environment. More preferably, the vessel 101 and liner 254 are made from quartz that reduces or eliminates the conduction of heat away from the process zone in which the wafers 108 are processed.
The thermal processing apparatus 100 further includes a magnetically coupled wafer rotation system 162 that rotates the support 104 and the boat 106 along with the wafers 108 supported thereon during processing. In the alternative, the thermal apparatus 100 uses a rotational ferrofluidics seal (not shown) to rotate the support 104 and the boat 106 along with the wafers 108 supported thereon during processing. Rotating the wafers 108 during processing improves within-wafer (WIW) uniformity by averaging out any nonuniformities in temperature and process gas flow to create a uniform wafer temperature and species reaction profile. Generally, the wafer rotation system 162 is capable of rotating the wafers 108 at a speed of from about 0.1 to about 10 revolutions per minute (RPM).
The wafer rotation system 162 includes a drive assembly or rotating mechanism 164 having a rotating motor 166, such as an electric or pneumatic motor, and a magnet 168 encased in a chemically resistive container, such as annealed polytetrafluoroethylene or stainless steel. A steel ring 170 located just below the insulating block 140 of the pedestal 130, and a drive shaft 172 with the insulating block transfer the rotational energy to another magnet 174 located above the insulating block in a top portion of the pedestal. The steel ring 170, drive shaft 172 and second magnet 174 are also encased in a chemically resistive container compound. The magnet 174 located inside of the pedestal 130 magnetically couples through the crucible 142 with a steel ring or magnet 176 embedded in or affixed to the support 104 in the process chamber 102.
Magnetically coupling the rotating mechanism 164 through the pedestal 130 eliminates the need for locating the rotating mechanism 164 within the processing environment or for having a mechanical feedthrough, thereby eliminating a potential source of leaks and contamination. Furthermore, locating rotating mechanism 164 outside and at some distance from the process chamber 102 minimizes the maximum temperature to which it is exposed, thereby increasing the reliability and operating life of the wafer rotation system 162.
In addition to the above, the wafer rotation system 162 can further include one or more sensors (not shown) to ensure proper boat 106 position and proper magnetic coupling between the steel ring or magnet 176 in the process chamber 102 and the magnet 174 in the pedestal 130. A boat position verification sensor which determines the relative position of the boat 106 is particularly useful. In one embodiment, the boat position verification sensor includes a sensor protrusion (not shown) on the boat 106 and an optical or laser sensor located below the base plate 124. In operation, after the wafers 108 have been processed the pedestal 130 is lowered about 3 inches below the base plate 124. There, the wafer rotation system 162 is commanded to turn the boat 106 until the boat sensor protrusion can be seen. Then, the wafer rotation system 162 is operated to align the boat so that the wafers 108 can be unloaded. After this is done, the boat is lowered to the load/unload height.
Stepped liners are typically used in traditional up-flow vertical furnaces to increase process gas velocities and diffusion control. They are also used as an aid to improve within-wafer uniformity. Unfortunately, stepped liners do not correct down-the-stack-depletion problems, which occur due to single injection point of reactant gases forcing all injected gases to flow past all surfaces down the stack. In prior art vertical across-flow furnaces, the down-the-stack-depletion problem is solved. However, a flow path of least resistance may be created in the gap region between the wafer carrier and the liner inner wall instead of between the wafers. This least resistance path may cause vortices or stagnation which are detrimental to manufacturing processes. Vortices and stagnation in a furnace may create across-wafer nonuniformity problems for some process chemistries.
The present invention provides an across-flow liner that significantly improves the within-wafer uniformity by providing uniform gas flow across the surface of each substrate supported in a carrier. In general, the across-flow liner of the present invention includes a longitudinal bulging section to accommodate an across-flow injection system so that the liner can be patterned and sized to conform to the wafer carrier. The gap between the liner and the wafer carrier is significantly reduced, and as a result, vortices and stagnation as occurred in prior art furnaces can be reduced or avoided.
Referring to
The across-flow liner can be made of any metal, ceramic, crystalline or glass material that is capable of withstanding the thermal and mechanical stresses of high temperature and high vacuum operation, and which is resistant to erosion from gases and vapors used or released during processing. Preferably, the across-flow liner 232 is made from an opaque, translucent or transparent quartz glass. In one embodiment, the liner is made from quartz that reduces or eliminates the conduction of heat away from the region or process zone in which the wafers are processed.
In general, the across-flow liner 232 includes a cylinder 256 having a closed end 258 and an open end 260. The cylinder 256 is provided with the longitudinal bulging section 262 having an inner wall 270 to accommodate an across-flow injection system (not shown). Preferably the bulging section 262 extends the substantial length of the cylinder 256. The plurality of latitudinal slots 254 are radial in their length and longitudinally located along the cylinder 256.
The across-flow liner 232 is sized and patterned to conform to the contour of the wafer carrier 106 and the carrier support 104. In one embodiment, the liner 232 comprises a first section 261 sized to conform to the wafer carrier 100 and a second section 263 sized to conform to the carrier support 104. The diameter of the first section 261 may differ from the diameter of the second section 263, i.e., the liner 232 may be “stepped” to conform to the wafer carrier 106 and carrier support 104 respectively. In one embodiment, the first section 261 of the liner 232 has an inner diameter that constitutes about 104% to 110% of the wafer carrier 106 outer diameter. In another embodiment, the second section 263 of the liner 232 has an inner diameter that constitutes about 115% to 120% of the outer diameter of the carrier support 104. The second section 263 may be provided with one or more heat shields 264 to protect seals such as O-rings from being overheated by heating elements.
Referring to
In one embodiment, the elongated tubes 116 or 251 include an index pin 253 for locking the elongated tube in one of the notches 268 in the openings 266, and the injection ports or orifices 252 are formed in line with the index pin. Therefore, when the elongated tube is installed, the index pin 253 can be locked in one of the notches 268 and the injection orifices 180 or 252 are oriented in a direction as indicated by the appropriate notch 268. An indicator (not shown) located on the opposite end of tubes 251 further allows a user to adjust the location of the injection ports 252. This adjustment is performed before, during and after a thermal processing run without removal of the across-flow liner 232 from the vessel 234.
Of advantage, the bulging section 262 of the across-flow liner 232 accommodates the across-flow injection system 116 or 250 therein and the liner 232 is made conformal to the contour of the wafer carrier 106. This confirming of the liner 232 to the wafer carrier 106 reduces the gap between the liner and the wafer carrier, thereby reducing the vortices and stagnation in the gap regions between the liner inner wall and the wafer carrier 106, improving gas flow uniformity and the quality, uniformity, and repeatability of the deposited film.
The base plate 124 has an opening 266 to receive the tube injectors. Notches 268 are formed in the base plate 124 to orient the injection ports 116-1, 116-2, 251-2 or 252-2 to a specific direction. Any number of notches 268 can be formed so that the elongated injection tubes can be adjusted 360 degrees relative to a fixed position and the injection ports 252 can be oriented in any direction as desired. For example, the index pin 253 the elongated tube injector 251-2 can be received in notch 268A so that the injection ports 252′ are oriented to face wafer substrates and the exit slots. As indicated in
In operation, a vacuum system produces a vacuum pressure in the reaction chamber 102. The vacuum pressure acts in the vertical direction of the vessel 101. The across-flow liner 232 is operative in response to the vacuum pressure to create a second vacuum inside the across-flow liner 232. The second vacuum pressure acts in a horizontal direction and across the surface of each substrate 108. Two gases, for example a first gas and a second gas, are introduced into the two elongated tubes 251 of the injection system 116 or 250 from two different gas sources. The gases exit the injection ports 252 on one side of the wafer 108 and pass as laminar flow across the wafer 242 to the slots 254 and between two adjacent wafers 108. Excessive gases or reaction byproducts are exhausted through the latitudinal slots 254 in the liner wall 232 cooperative with the injection orifices 180 or 252 in the elongated tube injectors.
An exemplary gas flow schematic for a two injector reactor is depicted in
The ability to deposit a layer of material on a wafer substrate batch with uniformity WIW and WTW of the batch is provided in additional detail in the following working examples. These exemplary, nonlimiting examples are intended to illustrate the conditions under which inventive deposition might occur.
A batch of 20 wafers was dispersed along a 120 wafer carrier with substrate blanks filling the unused 100 positions. After stabilizing a wafer substrate temperature and an inert dinitrogen atmosphere, trisilylamine and ammonia gas are introduced into the reactor at flow rates of 15 and 225 sccm while the reactor total pressure is maintained at 3 Torr with a controlled flow of argon gas. The deposition is allowed to proceed for 30 minutes at a reaction temperature of 515° C. A deposition rate of 1.8 Angstroms per minute is noted. WIW uniformity for the resultant silicon nitride film is 2.3 thickness percent (three sigma) while WTW thickness variation is 2.6 percent. Auger spectroscopy indicated the resultant deposited layer of material to be devoid of carbon and chlorine and having less than 8 atomic percent substitution hydrogen for the silicon counterions.
The process of Example 1 is repeated with a change in wafer substrate temperature. Comparable uniformity to that of Example 1 is noted while variations in deposition rate as a function of temperature are provided in Table 2 along with the comparative temperature and deposition rates for prior art precursors. Auger spectroscopy indicated the resultant deposited layer of material to be devoid of carbon and chlorine and having less than 10 atomic percent substitution hydrogen for the silicon counterions.
A low temperature oxide material layer is deposited with the reactor according to
A silicon oxynitride deposition layer is applied to a batch of wafer substrates with a total pressure of 2 Torr using dinitrogen as an inert gas, trisilylamine and N2O flowing at rates of 15 and 300 sccm, respectively. With the simultaneous flow of trisilylamine and N2O for a period of 30 minutes at a wafer substrate temperature of 525° C., silicon oxynitride deposition is noted to have occurred at a deposition rate of greater than 100 Angstroms per minute in a composition SiOmNn where m is reproducibly 0.77 and n is 0.33. WIW variation is less than 3% three sigma and WTW thickness variation is less than 2.8%. Auger spectroscopy indicated the resultant deposited layer of material to be devoid of carbon and chlorine and having less than 10 atomic percent substitution hydrogen for the silicon counterions. The resultant deposited layer of material is observed to have an index of refraction of between 1.7 and 1.9 for various batches.
Patent documents and publications mentioned in the specification are indicative of the levels of those skilled in the art to which the invention pertains. These documents and publications are incorporated herein by reference to the same extent as if each individual document or publication was specifically and individually incorporated herein by reference.
The foregoing description is illustrative of particular embodiments of the invention, but is not meant to be a limitation upon the practice thereof. The following claims, including all equivalents thereof, are intended to define the scope of the invention.
This application claims priority of U.S. Provisional Patent Application Ser. No. 60/697,784 filed Jul. 9, 2005, which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60697784 | Jul 2005 | US |
