BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a partial plan view of a tape carrier substrate according to one embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line A-A of FIG. 1A and FIG. 1C is a cross-sectional view taken along the line B-B of FIG. 1A.
FIG. 2 is a partial perspective view of the tape carrier substrate.
FIG. 3 shows the first half process of a manufacturing process of the tape carrier substrate.
FIG. 4 shows the last half process of the manufacturing process of the tape carrier substrate.
FIG. 5A schematically shows the relationship between the width of conductive wirings and the height of protrusion electrodes formed by the above manufacturing method, and FIG. 5B is a cross-sectional view showing the heights of the protrusion electrodes formed by metal plating conducted with respect to conductive wirings having different widths.
FIG. 6A is a plan view of a semiconductor device employing a tape carrier substrate as a disadvantageous example formed by the above manufacturing method, and FIG. 6B is a cross-sectional view taken along the line D-D of FIG. 6A.
FIG. 7A is a plan view of a semiconductor device employing a tape carrier substrate as an advantageous example formed by the above manufacturing method, and FIG. 7B is a cross-sectional view taken along the line E-E of FIG. 7A.
FIG. 8 shows a result of the experiment for verifying the relationship between the width of the conductive wirings and the height of the protrusion electrodes on the above-stated tape carrier substrate.
FIGS. 9A to 9B are cross-sectional views showing a process for mounting a semiconductor element on the tape carrier substrate to manufacture a semiconductor device.
FIG. 10 is a cross-sectional view showing another process for mounting a semiconductor element on the tape carrier substrate to manufacture a semiconductor device.
FIG. 11 is a cross-sectional view showing an exemplary conventional semiconductor device.
FIG. 12A is a partial plan view of an exemplary conventional tape carrier substrate, and FIG. 12B is a cross-sectional view taken along with the line F-F of FIG. 12A.
FIG. 13A is a plan view for explaining a break occurring at a connection portion between a protrusion electrode of an exemplary conventional tape carrier substrate and an electrode pad of a semiconductor element, and FIG. 13B is a cross-sectional view taken along the line G-G of FIG. 13A.
FIG. 14 is a plan view showing the positions susceptible to influences of a stress when a semiconductor element is mounted to a conventional tape carrier substrate.