William R. McKee

Person

Plano, Collin County, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for positioning sub-resolution assist features
- Patent number 7,694,269
- Issue date Apr 6, 2010
- Texas Instruments Incorporated
- Nagaraj Savithri
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Verifying a process margin of a mask pattern using intermediate sta...
- Patent number 7,458,058
- Issue date Nov 25, 2008
- Texas Instruments Incorporated
- Ashesh Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Line-to-line reliability enhancement using a dielectric liner for a...
- Patent number 7,402,514
- Issue date Jul 22, 2008
- Texas Instruments Incorporated
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 7,323,727
- Issue date Jan 29, 2008
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 7,211,842
- Issue date May 1, 2007
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,967,371
- Issue date Nov 22, 2005
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,831,317
- Issue date Dec 14, 2004
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,815,742
- Issue date Nov 9, 2004
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit capacitor
- Patent number 6,653,676
- Issue date Nov 25, 2003
- Texas Instruments Incorporated
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for high thermal stable contact formation in manufacturing...
- Patent number 6,559,050
- Issue date May 6, 2003
- Texas Instruments Incorporated
- William R. McKee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and method
- Patent number 6,528,888
- Issue date Mar 4, 2003
- Texas Instruments Incorporated
- Chih-Chen Cho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,512,257
- Issue date Jan 28, 2003
- Hitachi, Inc.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Yield improvement of dual damascene fabrication through oxide filling
- Patent number 6,461,955
- Issue date Oct 8, 2002
- Texas Instruments Incorporated
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,396,088
- Issue date May 28, 2002
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit capacitor
- Patent number 6,294,420
- Issue date Sep 25, 2001
- Texas Instruments Incorporated
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,288,925
- Issue date Sep 11, 2001
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of fabricating and operating single polysilicon flash EEPROM...
- Patent number 6,261,884
- Issue date Jul 17, 2001
- Texas Instruments Incorporated
- Chi-Chien Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Thermal neutron shielded integrated circuits
- Patent number 6,239,479
- Issue date May 29, 2001
- Texas Instruments Incorporated
- Ming Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post-etch treatment of a semiconductor device
- Patent number 6,218,311
- Issue date Apr 17, 2001
- Texas Instruments Incorporated
- Jeffrey A. McKee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,115,279
- Issue date Sep 5, 2000
- Hitachi Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple level conductor wordline strapping scheme
- Patent number 6,100,588
- Issue date Aug 8, 2000
- Texas Instruments Incorporated
- Hugh P. McAdams
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating an integrated circuit structure
- Patent number 6,096,597
- Issue date Aug 1, 2000
- Texas Instruments Incorporated
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,069,813
- Issue date May 30, 2000
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
In-situ doped rough polysilicon storage cell structure formed using...
- Patent number 6,060,354
- Issue date May 9, 2000
- Texas Instruments Incorporated
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single polysilicon flash EEPROM with low positive programming and e...
- Patent number 6,054,732
- Issue date Apr 25, 2000
- Texas Instruments Incorporated
- Chi-Chien Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 5,953,242
- Issue date Sep 14, 1999
- Hitachi Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for making channel stop structure for CMOS devices
- Patent number 5,441,902
- Issue date Aug 15, 1995
- Texas Instruments Incorporated
- ' Shiow-Ming Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic memory storage capacitor having reduced gated diode leakage
- Patent number 5,352,913
- Issue date Oct 4, 1994
- Texas Instruments Incorporated
- Gishi Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to eliminate gate filaments on field plate isolated devices
- Patent number 5,252,506
- Issue date Oct 12, 1993
- Texas Instruments Incorporated
- Duane E. Carter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Boundary cells for improving retention time in memory devices
- Patent number 5,251,168
- Issue date Oct 5, 1993
- Texas Instruments Incorporated
- Gishi Chung
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR POSITIONING SUB-RESOLUTION ASSIST FEATURES
- Publication number 20080203518
- Publication date Aug 28, 2008
- Nagaraj Savithri
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY
- Publication number 20070158695
- Publication date Jul 12, 2007
- Hitachi, Ltd
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
Verifying a process margin of a mask pattern using intermediate sta...
- Publication number 20060281015
- Publication date Dec 14, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Ashesh Parikh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20050237778
- Publication date Oct 27, 2005
- HITACHI, LTD.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20050035403
- Publication date Feb 17, 2005
- HITACHI, LTD.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
Line-to-line reliability enhancement using a dielectric liner for a...
- Publication number 20040147112
- Publication date Jul 29, 2004
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY
- Publication number 20040129974
- Publication date Jul 8, 2004
- Hitachi, Ltd
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20030067018
- Publication date Apr 10, 2003
- Hitachi, Ltd
- Goro Kitsukawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20020140015
- Publication date Oct 3, 2002
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit capacitor
- Publication number 20020014646
- Publication date Feb 7, 2002
- Robert Tsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20020000583
- Publication date Jan 3, 2002
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit and method
- Publication number 20010005058
- Publication date Jun 28, 2001
- Isamu Asano
- H01 - BASIC ELECTRIC ELEMENTS

William R. McKee

Person

Patents Grantslast 30 patents

Method for positioning sub-resolution assist features

Verifying a process margin of a mask pattern using intermediate sta...

Line-to-line reliability enhancement using a dielectric liner for a...

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

Integrated circuit capacitor

Process for high thermal stable contact formation in manufacturing...

Integrated circuit and method

System with meshed power and signal buses on cell array

Yield improvement of dual damascene fabrication through oxide filling

System with meshed power and signal buses on cell array

Integrated circuit capacitor

System with meshed power and signal buses on cell array

Method of fabricating and operating single polysilicon flash EEPROM...

Thermal neutron shielded integrated circuits

Post-etch treatment of a semiconductor device

System with meshed power and signal buses on cell array

Multiple level conductor wordline strapping scheme

Method for fabricating an integrated circuit structure

System with meshed power and signal buses on cell array

In-situ doped rough polysilicon storage cell structure formed using...

Single polysilicon flash EEPROM with low positive programming and e...

System with meshed power and signal buses on cell array

Method for making channel stop structure for CMOS devices

Dynamic memory storage capacitor having reduced gated diode leakage

Method to eliminate gate filaments on field plate isolated devices

Boundary cells for improving retention time in memory devices

Patents Applicationslast 30 patents

METHOD FOR POSITIONING SUB-RESOLUTION ASSIST FEATURES

SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY

Verifying a process margin of a mask pattern using intermediate sta...

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

Line-to-line reliability enhancement using a dielectric liner for a...

SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

Integrated circuit capacitor

System with meshed power and signal buses on cell array

Integrated circuit and method