Claims
- 1. In combination,
- a flexible circuit having a layer of flexible material and having a plurality of first raised bumps formed by said flexible material and a plurality of second raised bumps formed of said flexible material, and a first plurality of circuit traces having circuit ends which terminate on said first raised bumps and which are arrayed in a first pattern,
- an integrated circuit chip having a second plurality of circuit traces terminating in contact ends which are arrayed in a second pattern identical to that of the first pattern,
- said contact ends of said integrated circuit chip being in engagement with said circuit end on said first raised bumps,
- wherein said plurality of second raised bumps comprise a metal having a hollow portion and are higher than said first raised bumps and spaced from said first raised bumps, said second bumps having tapered side surfaces for engaging vertically extending surfaces on said chip so that said chip is guided into place on said substrate and so that its contact ends are aligned with the first raised bumps on said substrate.
- 2. The combination of claim 1 wherein the hollow portion is filled with a solid material.
- 3. In combination,
- a flexible circuit having a layer of flexible material and having a plurality of first raised bumps formed by said flexible material and a plurality of second raised bumps formed of said flexible material, and a first plurality of circuit traces having circuit ends which terminate on said first raised bumps and which are arrayed in a first pattern,
- an integrated circuit chip having a second plurality of circuit traces terminating in contact ends which are arrayed in a second pattern identical to that of the first pattern,
- said contact ends of said integrated circuit chip being in engagement with circuit ends on said first raised bumps,
- wherein said plurality of second raised bumps comprise a metal and are higher than said first raised bumps and spaced from said first raised bumps, said integrated circuit chip having a plurality of blind vias extending upwardly from an underside of the chip and which are defined by a side surface, said second bumps having tapered side surfaces for engaging said side surface so that said chip is guided into place on said substrate and so that its contact ends are aligned with the first raised bumps on said substrate.
- 4. The combination as defined in claim 3 and wherein the second raised bumps are conically shaped and have diameters which progressively decrease proceeding from said substrate to their free ends.
Parent Case Info
This is a continuation of application Ser. No. 08/409248 filed on Mar. 24, 1995 now abandoned.
US Referenced Citations (16)
Foreign Referenced Citations (4)
Number |
Date |
Country |
312217 |
Apr 1989 |
EPX |
58-125853 |
Jul 1983 |
JPX |
4-743 |
Jan 1992 |
JPX |
5-82921 |
Apr 1993 |
JPX |
Non-Patent Literature Citations (1)
Entry |
IBM Technical Disclosure Bulletin "Chip-to-Pin Carrier Interconnection System", vol. 21 No. 7, Dec. 1978 pp. 2707 and 2708. |
Continuations (1)
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Number |
Date |
Country |
Parent |
409248 |
Mar 1995 |
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